Signal Or Phase Comparator Patents (Class 331/25)
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Patent number: 7714669Abstract: The present disclosure relates to circuits and methods for accelerating a new frequency lock-in process of a digital phase-locked loop.Type: GrantFiled: June 16, 2008Date of Patent: May 11, 2010Assignee: Infineon Technologies AGInventors: Edmund Gotz, Klaus Peter Meiser
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Publication number: 20100109786Abstract: a power supply voltage output circuit includes: a power supply voltage generation unit generating a power supply voltage to be supplied into a ring oscillator; a reference clock oscillator oscillating a reference clock with respect to a clock oscillated by the ring oscillator; a phase difference detection unit detecting a phase difference between the clock from the ring oscillator and the reference clock from the reference clock oscillator; a filter unit smoothing an output of the phase difference detection unit; and a PWM signal generation unit generating a PWM signal based on an output of the filter unit such that the phase difference approaches zero.Type: ApplicationFiled: October 28, 2009Publication date: May 6, 2010Applicant: FUJITSU LIMITEDInventors: Masazumi Maeda, Yoshito Koyama
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Publication number: 20100097151Abstract: A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component.Type: ApplicationFiled: February 6, 2008Publication date: April 22, 2010Inventor: Jungo Arai
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Publication number: 20100097150Abstract: A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.Type: ApplicationFiled: October 16, 2008Publication date: April 22, 2010Inventors: Keisuke Ueda, Toshiya Uozumi, Satoru Yamamoto, Mitsunori Samata, Russell P. Mohn, Aleksander Dec, Ken Suyama
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Patent number: 7701299Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency.Type: GrantFiled: September 5, 2008Date of Patent: April 20, 2010Assignee: Phase Matrix, Inc.Inventor: Oleksandr Chenakin
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Patent number: 7696832Abstract: A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.Type: GrantFiled: October 22, 2008Date of Patent: April 13, 2010Assignee: National Chiao Tung UniversityInventors: Chen-yi Lee, Ching-che Chung
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Patent number: 7696831Abstract: Phase locked loop and method for controlling the same includes a phase/frequency detector configured to detect a phase difference between an input clock and a feedback clock to generate an up signal or a down signal depending on the detected phase difference, a charge pump configured to variably control a bandwidth according to a bandwidth control signal input thereinto, the charge pump operating in response to the up signal or the down signal and a voltage controlled oscillator configured to change a frequency according to an output of the charge pump.Type: GrantFiled: March 26, 2008Date of Patent: April 13, 2010Assignee: Hynix Semiconductor Inc.Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon
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Publication number: 20100085121Abstract: An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency.Type: ApplicationFiled: October 3, 2008Publication date: April 8, 2010Applicant: ATMEL CORPORATIONInventors: Sebastien Fievet, Michel Cuenca
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Patent number: 7692497Abstract: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of a charge pump and provides a signal to a digital control circuit to choose a suitable load circuit for the PLL voltage controlled oscillator (VCO). The analog comparator with the digital control circuit changes the VCO loads to select the best VCO range to achieve the incoming signal frequency lock. A single PLL with the VCO load selection method disclosed, with use of built-in hysteresis, in addition to the phase and frequency feedback of the prior art, allows multiple overlapping frequency ranges to be covered in a stable fashion. This enables frequency locking of the PLL over a wide range of frequencies with a small die size and low power consumption.Type: GrantFiled: February 12, 2007Date of Patent: April 6, 2010Assignee: Analogix Semiconductor, Inc.Inventors: Jianbin Hao, Ning Zhu, Yanjing Ke
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Patent number: 7692501Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.Type: GrantFiled: September 14, 2007Date of Patent: April 6, 2010Inventors: Yu-Li Hsueh, Miaobin Gao, Chien-Chang Liu
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Patent number: 7692498Abstract: A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.Type: GrantFiled: October 26, 2007Date of Patent: April 6, 2010Assignee: Infineon Technologies AGInventors: Thomas Mayer, Christian Wicpalek, Thomas Bauernfeind, Linus Maurer
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Patent number: 7689191Abstract: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge/discharge node, and a second capacitive element connected to the charge/discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.Type: GrantFiled: March 30, 2007Date of Patent: March 30, 2010Assignees: Renesas Technology Corp., Epoch Microelectronics, Inc.Inventors: Yasuyuki Kimura, Satoshi Shimizu, Masakatsu Yokota, Ken Suyama, Aleksander Dec
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Publication number: 20100073094Abstract: A circuit includes phase detection circuitry, a clock signal generation circuit, a first frequency divider, and a second frequency divider. The phase detection circuitry compares an input clock signal to a feedback signal to generate a control signal. The clock signal generation circuit generates a periodic output signal in response to the control signal. The first frequency divider divides a frequency of the periodic output signal by a first value to generate a first frequency divided signal. The second frequency divider divides the frequency of the periodic output signal by a second value to generate a second frequency divided signal. The first and the second frequency divided signals are routed to the phase detection circuitry as the feedback signal during different time intervals.Type: ApplicationFiled: September 19, 2008Publication date: March 25, 2010Applicant: Altera CorporationInventors: Tim Tri Hoang, Wilson Wong, Sergey Shumarayev
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Patent number: 7683723Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.Type: GrantFiled: October 2, 2007Date of Patent: March 23, 2010Assignee: Renesas Technology Corp.Inventors: Yukinori Akamine, Manabu Kawabe, Satoshi Tanaka, Yasuo Shima, Ryoichi Takano
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Publication number: 20100059355Abstract: An electronic device used for measuring and detecting the variations of at least one input signal, comprising a first component (OSC1) providing an output signal, the oscillation frequency of which is representative of the input signal, a reference oscillator (OSC2), a phase comparison component (CP) providing a comparison between the oscillations of the first component (OSC1) and the reference oscillator (OSC2), in particular for a loop control of the reference oscillator on the first component, or of the first component on the reference oscillator, or for a mutual control, and elastic coupling means (C) between the first component (OSC1) and the reference oscillator (OSC2).Type: ApplicationFiled: November 12, 2007Publication date: March 11, 2010Inventor: Jean-Noel Lefebvre
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Patent number: 7675334Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.Type: GrantFiled: January 15, 2009Date of Patent: March 9, 2010Assignee: Renesas Technology Corp.Inventor: Takashi Kawamoto
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Patent number: 7675328Abstract: A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.Type: GrantFiled: January 27, 2009Date of Patent: March 9, 2010Assignee: Fujitsu LimitedInventor: Tszshing Cheung
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Patent number: 7675335Abstract: A phase detecting module includes a phase detecting unit, a comparator and a counter. The phase detecting unit is arranged to compare a first input signal and a second input signal to generate a phase detecting result. The comparator is arranged to compare the phase detecting result and a predetermined voltage to generate a comparing result. The counter is arranged to count one of the first input signal and the second input signal to generate a counting value. The phase detecting result and the counting value are reset if the counting value reaches a predetermined value, and the comparing result is outputted to a target device from the comparator if the counting value reaches a predetermined value.Type: GrantFiled: March 19, 2009Date of Patent: March 9, 2010Assignee: Nanya Technology Corp.Inventor: Wen-Chang Cheng
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Patent number: 7667545Abstract: A lock loop circuit (216) includes a precharge circuit (304), an oscillator circuit (306), and a calibration circuit (309). The calibration circuit includes at least one register (362). The precharge circuit provides a precharge signal (347). The oscillator circuit provides an output frequency signal (228) in response to a steering signal (334) that is based on the precharge signal. The calibration circuit, prior to the lock loop circuit entering a disabled mode of operation, determines a calibration value (368) for the precharge circuit based on the precharge signal and the steering signal. The calibration circuit stores the calibration value as a digital calibration value (370) in the register.Type: GrantFiled: March 4, 2008Date of Patent: February 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: David M. Schlueter, Michael C. Doll
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Publication number: 20100026395Abstract: Techniques for mitigating VCO pulling are described. In an aspect, VCO pulling may be mitigated by (i) injecting an oscillator signal, which is a version of a VCO signal from a VCO, into a transmitter and (ii) using coupling paths from the transmitter to the VCO to re-circulate the oscillator signal back to the VCO. In one design, an apparatus includes a VCO and a coupling circuit. The VCO generates a VCO signal at N times a desired output frequency. The coupling circuit receives an oscillator signal generated based on the VCO signal and injects the oscillator signal into a transmitter to mitigate pulling of the frequency of the VCO due to undesired coupling from the transmitter to the VCO. The apparatus may include a phase adjustment circuit that adjusts the phase of the oscillator signal and/or an amplitude adjustment circuit that adjusts the amplitude of the oscillator signal.Type: ApplicationFiled: August 1, 2008Publication date: February 4, 2010Applicant: QUALCOMM INCORPORATEDInventor: Mark Vernon Lane
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Patent number: 7656206Abstract: A voltage controlled oscillator 8 is configured to include a plurality of variable delay circuits 30 that are connected to one another so as to form a ring. Output fixing units 31 each of which fixes, when the voltage controlled oscillator 8 stops operating, the output of a corresponding one of the variable delay circuits 30 are provided. As a result, even if the voltage controlled oscillator 8 that operates by following the frequency of an input clock has changed into an operation stop state, because the output fixing units 31 fix the outputs of the variable delay circuits 30, the output of the voltage controlled oscillator 8 is prevented from being in an inconstant state. Thus, it is possible to ensure that the voltage controlled oscillator 8 oscillates properly when the voltage controlled oscillator 8 resumes or starts its operation.Type: GrantFiled: October 25, 2007Date of Patent: February 2, 2010Assignee: Thine Electronics, Inc.Inventor: Kazuyuki Omote
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Patent number: 7656237Abstract: An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.Type: GrantFiled: December 2, 2004Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Mack Wayne Riley, Daniel Lawrence Stasiak, Michael Fan Wang, Stephen Douglas Weitzel
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Patent number: 7652540Abstract: A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an operation clock generated by a clock generator at a prescribed time. An output clock generating device outputs output clock time data per the one cycle in accordance with frequency control data. The output clock time data has a value corresponding to a phase of a virtual output clock generated by dividing the operation clock in accordance with the time resolution. A phase difference detecting device detects a difference between phases of the input signal and the virtual output clock, and outputs a phase difference signal in accordance with the detection result. The frequency control device changes the frequency control data in accordance with the phase difference signal.Type: GrantFiled: October 5, 2007Date of Patent: January 26, 2010Assignee: Ricoh Company, Ltd.Inventor: Toshihiro Shigemori
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Patent number: 7642862Abstract: A digital phase locked loop includes a phase acquisition unit for producing a digital representation of the phase of a reference signal, a digital phase detector having a first input receiving a digital signal from, or derived from, the output of the phase acquisition unit, digital loop filter filtering the output of the digital phase detector, and a digital controlled oscillator generating an output signal under the control of the digital loop filter. A digital feedback loop provides a second input to the digital phase detector from the output of the digital controlled oscillator.Type: GrantFiled: November 14, 2007Date of Patent: January 5, 2010Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paul Hendricus Lodewijk Maria Schram, Johannes Hermanus Aloysius de Rijk
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Patent number: 7642863Abstract: Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.Type: GrantFiled: December 7, 2007Date of Patent: January 5, 2010Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Masaaki Kaneko, David W. Boerstler, Eskinder Hailu, Jieming Qi
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Patent number: 7642821Abstract: A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period. The method includes generating a phase difference signal which is proportional to a phase difference between the clock signal and the reference signal, filtering the phase difference signal and providing a filtered phase difference signal, driving a digital oscillator in such a manner that the frequency of the clock signal is changed on the basis of the filtered phase difference signal, the phase of the clock signal within a clock period being corrected by a value corresponding to the fraction of the clock period at an end of the pause in the reference signal.Type: GrantFiled: February 15, 2007Date of Patent: January 5, 2010Assignee: Infineon Technologies AGInventors: Guenter Krasser, Thomas Duda
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Publication number: 20090322432Abstract: A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal.Type: ApplicationFiled: September 10, 2009Publication date: December 31, 2009Applicants: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITYInventors: Shen-Iuan Liu, Chih-Hung Lee
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Patent number: 7639088Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.Type: GrantFiled: April 25, 2008Date of Patent: December 29, 2009Assignee: NanoAmp Mobile, Inc.Inventors: David H. Shen, Ann P. Shen, Axel Schuur
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Patent number: 7639090Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.Type: GrantFiled: November 26, 2008Date of Patent: December 29, 2009Assignee: Micron Technology, Inc.Inventor: Feng Lin
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Publication number: 20090309665Abstract: A low phase noise PLL synthesizer is described in which an initial tuning mechanism uses a conventional divider loop to lock a VCO to a desired output frequency. Once initial lock is achieved, the divider loop is switched out of the circuit in favor of a low phase noise mixer loop. The local oscillator signal for the mixer is derived from the same low phase noise source as the phase comparison frequency.Type: ApplicationFiled: September 5, 2008Publication date: December 17, 2009Applicant: Phase Matrix, Inc.Inventor: Oleksandr Chenakin
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Patent number: 7633347Abstract: An apparatus and method for operating a phase-locked loop circuit are disclosed. The phase locked loop circuit includes a plurality of resistive elements and a plurality of capacitive elements that are distributed in a charge pump, a loop filter and a voltage controlled oscillator. The plurality of resistive elements have a plurality of resistances that vary in proportion to each other. The plurality of capacitive elements have a plurality of capacitive elements that vary in proportion to each other. A damping factor of the phase-locked loop circuit is maintained substantially constant by the plurality of resistive elements and the plurality of capacitive elements.Type: GrantFiled: May 30, 2007Date of Patent: December 15, 2009Assignee: 02Micro International LimitedInventors: Seeteck Tan, Meng Chu
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Patent number: 7626469Abstract: An electric circuit, for use in a phase lock loop circuit, the electric circuit comprising: a first circuit element, being a phase frequency detector or a charge pump; at least one LC resonant loop, the first circuit element forming part of the loop; and means arranged to reduce ringing in said at least one LC resonant loop.Type: GrantFiled: April 17, 2008Date of Patent: December 1, 2009Assignee: GloNav Ltd.Inventors: Ramesh Chokkalingam, Matteo Conta
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Patent number: 7626464Abstract: A multi-frequency signal source and a method for providing a multi-frequency signal source with phase-lock capability are provided. The multi-frequency signal source includes a plurality of single-section filters each configured to provide oscillation of a signal at a different frequency. The multi-frequency signal source further includes a phase lock component providing a reference signal to control the oscillation at each of the frequencies.Type: GrantFiled: July 21, 2004Date of Patent: December 1, 2009Inventor: Kenneth Vincent Puglia
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Patent number: 7619483Abstract: A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.Type: GrantFiled: November 14, 2007Date of Patent: November 17, 2009Assignee: Zarlink Semiconductor Inc.Inventors: Robertus Laurentius van der Valk, Paulus Hendricus Lodewijk Maria Schram, Douglas Robert Sitch
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Patent number: 7616069Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.Type: GrantFiled: December 29, 2006Date of Patent: November 10, 2009Assignee: Broadcom CorporationInventor: Dandan Li
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Patent number: 7616065Abstract: A method of generating a correction signal for a voltage controlled oscillator (VCO) includes receiving a first signal in a correction current generator, changing a state of a first error signal substantially simultaneously with a first changing state of the first signal, receiving a second signal in the correction current generator, changing a state of a second error signal substantially simultaneously with a first changing state of the second signal, changing the state of the first error signal substantially simultaneously with a second changing state of the second signal, changing the state of the second error signal substantially simultaneously with a second changing state of the first signal, combining the first error signal and the second error signal to generate the correction signal substantially equal to a difference between the first error signal and the second error signal and applying the correction signal to a loop filter coupled to a correction signal input of the VCO.Type: GrantFiled: June 15, 2006Date of Patent: November 10, 2009Assignee: Sun Microsystems, Inc.Inventor: Francisco Fernandez
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Publication number: 20090273402Abstract: The present invention concerns a phase-locked loop comprising: a variable oscillator connected to a first resonator, said oscillator being able to deliver an output signal at a first output frequency Fout1, a first frequency divider receiving said output signal and able to convert it into a divided frequency signal Fout1/n, a reference oscillator connected to a second so-called reference resonator, delivering a reference signal at a low reference frequency Fref, generating an electrical dissipation lower than a microampere, a phase comparator measuring the phase error between the divided frequency signal Fout1/n and the reference signal and being able to produce a test signal, a low-pass filter or an integrating circuit able to filter the test signal and able to generate a voltage or a control word designed to control the voltage-controlled or digitally controlled oscillator.Type: ApplicationFiled: May 1, 2008Publication date: November 5, 2009Applicant: CSEM CENTRE SUISSE D' ELECTRONIQUE ET DE MICROTECHNIQUE SA- RECHERCHE ET DEVELOPMENTInventor: David Ruffieux
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Patent number: 7612625Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.Type: GrantFiled: February 19, 2008Date of Patent: November 3, 2009Assignee: Intel CorporationInventors: Miaobin Gao, Yu-Li Hsueh, Chien-Chang Liu
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Patent number: 7612617Abstract: A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.Type: GrantFiled: March 1, 2008Date of Patent: November 3, 2009Assignee: Skyworks Solutions, Inc.Inventors: Rajasekhar Pullela, Morten Damgaard, Shahrzad Tadjpour, John E. Vasa, Hoon Lee
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Patent number: 7612619Abstract: A device and method for phase detection are disclosed. The device includes a phase differential module that provides a phase difference signal based on the phase difference between a data signal and a reference signal. The phase difference signal is provided to a first gate of a multi-gate fin-type field effect transistor (multi-gate FinFET) of the device. A second gate of the multi-gate FinFET transistor receives a bias signal that provides a phase detection threshold. A phase adjustment signal is provided at one or both of the FinFET current electrodes based on the phase difference signal and the bias signal.Type: GrantFiled: March 23, 2006Date of Patent: November 3, 2009Assignee: Freescale Semiconductor, IncInventors: Mohamed S. Moosa, Leo Mathew, Sriram S. Kalpat
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Patent number: 7605666Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=ΒΌ*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.Type: GrantFiled: January 20, 2009Date of Patent: October 20, 2009Inventor: Chris Karabatsos
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Patent number: 7605665Abstract: An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal.Type: GrantFiled: May 25, 2007Date of Patent: October 20, 2009Assignee: Broadcom CorporationInventors: Mark Chambers, Natarajan Ramachandran, Karapet Khanoyan, Tong Zhu
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Patent number: 7605667Abstract: A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal.Type: GrantFiled: December 7, 2007Date of Patent: October 20, 2009Assignees: Mediatek Inc., National Taiwan UniversityInventors: Shen-Iuan Liu, Chih-Hung Lee
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Patent number: 7605662Abstract: An oscillator controller has a phase frequency detector that compares a reference signal and a frequency-divided signal and outputs a phase difference signal; a charge pump; a loop filter that filters the phase error signal output from the charge pump and outputs an oscillation frequency controlling voltage; a voltage-controlled oscillator; a first counter that counts the number of waves of the reference signal to a desired number and outputs a first flag signal; a second counter that counts the number of waves of the frequency-divided signal to the desired number and outputs a second flag signal; a first comparator that compares the first flag signal and the second flag signal and outputs a frequency comparison signal; and a control circuit that controls the voltage-controlled oscillator, the first counter, the second counter and the frequency divider by outputting signals thereto.Type: GrantFiled: April 16, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Kobayashi, Shouhei Kousai
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Patent number: 7603095Abstract: The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into.Type: GrantFiled: February 17, 2006Date of Patent: October 13, 2009Assignee: Silicon Integrated Systems Corp.Inventors: Chia-hao Yang, Chia-jung Liu
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Publication number: 20090251225Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.Type: ApplicationFiled: March 31, 2009Publication date: October 8, 2009Inventors: Shuo-Wei Chen, David Kuochieh Su
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Patent number: 7599462Abstract: A hybrid analog/digital phase-lock loop with high-level event synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level and synchronizing the output clock to high-level events. A numerically-controlled analog oscillator provides a clock output and a counter divides the frequency of the clock output to provide input to a digital phase-frequency detector for detecting an on-going phase-frequency difference between the timing reference and the output of the counter. A synchronization circuit detects or receives a high-level event signal, and resets the on-going phase-frequency difference and optionally the counter to synchronize the clock output with the events. The synchronization circuit may have an arming input to enable the synchronization circuit to signal a next event. Another clock output divider may be included to generate a timing reference output, and the other clock divider also reset in response to a detected event.Type: GrantFiled: April 24, 2007Date of Patent: October 6, 2009Assignee: Cirrus Logic, Inc.Inventor: John L. Melanson
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Patent number: 7596052Abstract: Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line.Type: GrantFiled: August 30, 2007Date of Patent: September 29, 2009Assignee: Micron Technology Inc.Inventor: Yantao Ma
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Patent number: 7595699Abstract: A lock loop circuit (230) includes a floating ground loop filter circuit (302) and a precharge circuit (304). The floating ground loop filter circuit includes at least one capacitive element (326, 328). The floating ground loop filter circuit provides a steering signal (334) for a controllable oscillator circuit (306) in response to a precharge signal (347). The precharge circuit provides the precharge signal in response to lock loop enable information (226). The precharge circuit controls the floating ground loop filter to bypass the at least one capacitive element for a period of time (606) in response to the lock loop enable information.Type: GrantFiled: March 4, 2008Date of Patent: September 29, 2009Assignee: Freescale Semiconductor, Inc.Inventors: David M. Schlueter, Michael C. Doll
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Patent number: RE41235Abstract: A PLL circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between a reproduced data pulse and a clock generated by a VCO; a phase comparator for detecting a difference in phases between the reproduced data pulse and the VCO clock; a selector for selectively outputting a signal supplied from the frequency comparator, a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a VCO for generating a clock of a frequency corresponding to the output voltage of the loop filter.Type: GrantFiled: January 16, 2007Date of Patent: April 20, 2010Assignee: Panasonic CorporationInventors: Yoshinori Miyada, Seiji Watanabe