Abstract: A digital quadrature modulator holds local oscillator circuitry configured to provide local oscillator signals, and local oscillator polarity logic circuitry configured to select an In-phase and a Quadrature local oscillator signal according to a sign bit of an In-phase control word and a sign bit of a Quadrature control word, respectively. The modulator holds a number of local oscillator control logic circuits, each configured to generate a conditioned signal by gating one or both of the selected local oscillator signals according to values of the In-phase control word and/or values of the Quadrature control word. The modulator has one or more sets of switched-capacitor units, where each unit has an output provided by an output capacitor, and where a signal at the input side of the output capacitor is controlled by a conditioned signal. The outputs of at least two of the switched-capacitor units are combined in a common node.

Abstract: A first combination of frequency bands is selected for transmitting a first data packet, and a second, different combination of frequency bands is selected for transmitting a second data packet. A data stream is divided into a first set of data and a second set of data. The first set of data is allocated to the first combination of frequency bands, and the second set of data is allocated to the second combination of frequency bands.

Abstract: A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input.

Abstract: A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition of a pulse in the DCO clock output signal such that the code update may be achieved while the DCO delay chain remains in the same logic state. A state machine may provide the DCO code update and a pulsed update signal to a timing circuit. The DCO code update may be aligned with a pulse in the pulsed update signal. The timing circuit may generate a DCO code update enabled signal upon alignment of the pulse in the pulsed update signal with a state transition of a pulse in the pulsed DCO clock output. The DCO code update enabled signal may be aligned with a state transition in the pulsed DCO clock output to permit a glitch-free DCO code update.

Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.

Abstract: A voltage controlled oscillator (VCO) which can be configured with a smaller tuning range than is ordinarily required is presented. Ordinarily, the tuning range is selected much broader than the application warrants so that sufficient range is still provided despite VCO process variations. The inventive VCO is able to substantially eliminate the effects of process variation by utilizing a calibration circuit and process, so that variation in VCO device operation is minimized despite substantial process variation. Accordingly, the inventive VCO device is subject to reduced levels of jitter as its range need not be utilized for overcoming process variation arising during device fabrication.

Abstract: Even after power-down, distinction between a transition from a PLL normal-oscillation state and a transition from a PLL self-oscillation is allowed. A semiconductor device includes a first region which, after having transited from a power-supply state to a power-down state, returns to the power-supply state again, a second region which holds a power source voltage regardless of power-down of the first region, and an oscillator which generates a first clock signal supplied to the first region. The first region includes a PLL circuit. The second region includes an information holding unit capable of holding information which can distinguish whether the operation mode of the PLL circuit is a PLL normal-oscillation mode or a PLL self-oscillation mode, and determines the operation mode of the PLL circuit when the first region has returned from the power-down state to the power-supply state, according to the information held in the information holding unit.

Abstract: A tunable clock circuit has a dual overlapping digital to analog converter (DAC) and an oscillator. The dual overlapping DAC provides a first output selectable with a first resolution and a second output selectable with a second resolution. The first resolution is different from the second resolution. The oscillator has a first input coupled to the first output of the dual overlapping DAC, a second input coupled to the second output of the dual overlapping DAC, and an output providing a clock output signal.

Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.

Abstract: Because of associated disadvantages of narrow-band off-chip radio-frequency (RF) filtering, a mixer-first receiver front-end designed to tolerate blockers with minimal gain compression and noise factor degradation is disclosed. The mixer-first receiver front-end includes two separate down-conversion paths that help to minimize added noise and voltage gain prior to baseband filtering, which are critical factors in eliminating narrow-band off-chip RF filtering.

Abstract: The method of calibration of a second order intermodulation intercept point (IIP2) of a radio transceiver comprises the steps of: generating a second order intermodulation (IM2) reference signal (STXIM2-REF) from a transmission baseband signal (STXBB-REF); estimating a second order intermodulation power from the second order intermodulation reference signal (STXIM2-REF) and a radio transceiver output signal (Output); tuning a second order intermodulation intercept point tuner to find a lowest second order intermodulation power; extracting an optimum second order intermodulation intercept point corresponding to the lowest second order intermodulation power.

Abstract: One embodiment relates to an apparatus for regulating a voltage-controlled oscillator. The apparatus includes a digital-to-analog converter that has an input that receives a digital input signal and an output that outputs an analog control signal. A transistor receives the analog control signal so as to control an output voltage of the voltage-controlled oscillator. Control circuitry receives the output voltage and generates the digital input signal. Another embodiment relates to a method of regulating a voltage-controlled oscillator. A digital input signal is converted to an analog control signal using a digital-to-analog converter. The output voltage of the voltage-controlled oscillator is controlled using the analog control signal and monitored using a plurality of comparators. The digital input signal is changed depending on outputs of the plurality of comparators. Other embodiments, aspects, and features of the invention are also disclosed.

Abstract: A high-precision oscillator includes a voltage reference module which includes multiple measured Field Effect Transistors and arranged for detecting process corners for the measured Field Effect Transistors to generate a reference voltage containing process corner information of the measured Field Effect Transistors, a compensation current generating module which is arranged for receiving the reference voltage, making a temperature compensation for the reference voltage, and generating a compensation current which includes both the process compensation and temperature compensation, and a ring oscillator which is arranged for receiving the compensation current and outputting a clock with stable frequency.

Abstract: This disclosure relates to a divide-by-N frequency divider system and frequency dividing method. The system includes a ring oscillator having M stages, where M is an integer, and a zero mean current component coupled to one or more of the stages to provide a zero mean current flow path.

Abstract: The temperature compensated crystal oscillator has a rectangular substrate, a frame which is provided on an upper surface of the substrate, a mounting frame which has joining pads which are provided along an outer circumferential edge of the upper surface and which is provided on a lower surface of the substrate by bonding of joining terminals which are provided along the outer circumferential edge of the lower surface of the substrate and the joining pads, a crystal element which is mounted on an electrode pad which is provided on the upper surface of the substrate in a region surrounded by the frame, an integrated circuit element which has a temperature sensor and which is mounted on a connection pad which is provided on the lower surface of the substrate in a region surrounded by the mounting frame, and a lid which is joined to the upper surface of the frame.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: Various techniques for generating an output clock based on a reference clock. This disclosure relates to generating an output clock signal based on a reference clock signal. In one embodiment, a method includes generating, using information received from a control circuit, an output clock signal using both a first number of edges or an input clock signal and a second, different number of edges of the input clock signal. In this embodiment, the control circuit runs at a frequency that is less than a frequency of the input clock signal. The received information may indicate, for a pulse of the output clock signal, whether the pulse should be generated using the first number of edges or the second number of edges. In some cases, the second number of edges may be the first number of edges plus one. The first and second number of edges may be programmable quantities.

Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

Abstract: An oscillation circuit, an oscillator, an electronic device, and a moving object which are capable of adjusting an output frequency in a high modulation bandwidth with a high level of accuracy and adjusting a timing at which the output frequency is changed are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element and includes a communication unit that receives frequency setting data for setting a frequency of the oscillation signal and frequency change data which is given a timing at which the frequency of the oscillation signal is changed on the basis of the frequency setting data, by serial transfer, and registers in which the frequency setting data and the frequency change data received by the communication unit are stored, respectively. An address of the register storing the frequency setting data is continuous with an address of the register storing the frequency change data.

Abstract: According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter.

Abstract: A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal. The frequency-control circuit also includes a frequency divider that is configured to apply a correction voltage to a feedback of the output frequency signal, the correction voltage being a function of a pulling signal having one or more unwanted frequency components. The frequency-control circuit also includes a loop filter configured to filter the output detection signal including the correction voltage and generate a control voltage signal. The frequency-control circuit also includes a voltage-controlled oscillator configured to receive the control voltage signal and generate an output frequency signal.

Abstract: Clock synchronization error is corrected or minimized by fitting a parabolic f(T) function to the crystal's data, and compensating for sampling period drift in an Analog to Digital Converter (ADC) at various temperatures.

Abstract: There is provided an oscillator arrangement for generating a clock signal. The oscillator arrangement comprises a current controlled oscillator, a frequency to voltage converter, and an operational amplifier. The oscillator arrangement is connectable to a supply voltage source. In one embodiment, the oscillator arrangement may achieve a stable clock frequency insensitive to supply and temperature variation with low current consumption and low area. This may be achieved by using Vref and Vout as input signals to the operational amplifier, both signals being directly derived from the supply voltage. In a further embodiment, a trimming resistor may be used in the frequency to voltage converter for adjusting the frequency.

Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.

Abstract: A voltage controlled oscillator includes a voltage-to-current converter and a current controlled oscillator, where the voltage-to-current converter is used for converting an input voltage to generate an output current, and the current controlled oscillator is used for generating an output frequency signal according to the output current. In addition, the voltage-to-current converter includes an input terminal, a resistor, a current mirror and a current generating circuit, where the input terminal is for receiving the input voltage; the resistor is coupled to the input terminal; the current mirror is coupled to the resistor, and is used for mirroring a reference current to generate a mirrored current, where the reference current is formed according to at least a current flowing through the resistor; and the current generating circuit is coupled to the current mirror, and is used for generating the output current according to at least the mirrored current.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: A multi-input voltage-to-frequency conversion circuit, includes: a multi-input operational amplifier amplifying one of multiple voltage signals in response to multiple control signals to generate an amplified voltage; a voltage-to-current converter converting the amplified voltage into a sensed current, and generating an oscillation current based on the sensed current and on an offset voltage that is associated with a predetermined frequency range corresponding to the one of the voltage signals; and a current-controlled oscillator generating, based on the oscillation current, a periodic pulse signal that has a frequency linearly proportional to the magnitude of the one of the voltage signals.

Abstract: A system for generating a variable frequency is provided. The system includes a voltage controlled oscillator (VCO) and an integrator. The VCO is configured to output a frequency signal with a frequency value dependent on a voltage value of a control signal. The integrator is configured to vary the control signal provided to the VCO. The ramp rate of the integrator is varied so the frequency value changes at a substantially constant frequency rate over a period of time, i.e. is linearized. In one configuration, the ramp rate of the integrator is based on an input value of an input signal to the integrator determined by a digital to analog convertor (DAC).

Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.

Abstract: A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: Clock synchronization error is corrected or minimized by fitting a parabolic f(T) function to the crystal's data, and compensating for sampling period drift in an Analog to Digital Converter (ADC) at various temperatures.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.

Abstract: An oscillation device includes a voltage control oscillation unit, a dividing unit, an output phase comparison unit, and a control voltage supply unit. The voltage control oscillation unit is configured to oscillate an oscillation frequency signal with a frequency f1 according to a control voltage. The dividing unit is configured to divide the frequency of the oscillation frequency signal into 1/N (N is a natural number) to match with a frequency f2 of a reference frequency signal input from outside. The output phase comparison unit is configured to compare a phase of the divided oscillation frequency signal with a phase of the reference frequency signal and output a signal according to a phase difference. The control voltage supply unit is configured to generate a control voltage according to the signal according to the phase difference and supply the control voltage to the voltage control oscillation unit.

Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.

Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.

Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

Abstract: A system and method in accordance with the present invention provides a gyroscope incorporating an improved PLL technique. The improved PLL auto-corrects its own reference low-frequency noise, thereby eliminating this source of noise, improving the noise performance of the gyroscope and allowing a compact implementation. The net result is a gyroscope with improved bias stability that can meet noise requirements with a smaller footprint.

Abstract: A frequency synthesis device with a feedback loop includes: a phase-comparison control circuit; a frequency conversion unit voltage controlled by the control circuit; a feedback loop for supplying at least one signal issuing from the frequency conversion unit to the control circuit; at least one other control circuit for voltage control of the frequency conversion unit; and at least one other feedback loop for supplying at least one other signal issuing from the frequency conversion unit to the other control circuit.

Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.

Abstract: A calibration circuit for a DCO includes a signal-conditioning module configured for (i) receiving at input an oscillating signal generated by the DCO and a reference signal, both designed to oscillate between a high logic value (“1”) and a low logic value (“0”), and (ii) detecting a respective first and second stable logic value of the reference signal and of the oscillating signal; and a period-to-voltage converter module coupled to the signal-conditioning module and configured for (iii) generating a difference signal identifying a difference between the period of the reference signal and the period of the oscillating signal, and (iv) controlling, on the basis of the difference signal, the DCO so as to conform the duration of the period of the oscillating signal to the duration of the period of the reference signal. Likewise described is a calibration method implemented by the calibration circuit.

Abstract: A digitally-controlled oscillator includes a base frequency generator having an odd number of base inverters connected end-to-end to generate an output signal that oscillates at a predetermined frequency and a frequency-adjusting unit connected to the base frequency generator. The frequency-adjusting unit includes a first string of switchable inverters connected in series with each other, the switchable inverters having sizes that decrease from an input end of the first string to the output end of the first string.

Abstract: A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO.

Abstract: A frequency-locked loop circuit includes: a digital control oscillator that generates a clock; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator.