Abstract: The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.

Abstract: A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.

Abstract: A clock generator is provided, capable of automatically adjusting an output clock when process, voltage, or temperature variation occurs. The clock generator includes a current generator, for generating a first current and a second current according to a bias signal, an oscillator, coupled to the current generator, for generating a clock signal according to the first current, a frequency detector, coupled to the oscillator, for generating a control signal according to the clock signal and a reference signal, and a bias voltage adjuster, coupled to the current generator and the frequency detector, for adjusting the bias signal according to the control signal. When the signal frequency of the clock signal changes, the bias signal corresponds to the bias voltage adjuster, to adjust the first current and the second current.

Abstract: A clock signal generator comprising an input pin for receiving an oscillating signal and an output pin for providing a clock signal. The clock signal generator also comprises a frequency divider connected between the input pin and the output pin. The frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator further comprising a controller configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors.

Abstract: Precision measurement of a period(s) of an embedded clock oscillator using a charge time measurement unit (CTMU) maintains a desired frequency accuracy of the embedded clock oscillator over a range of time, temperature and operating condition changes. The CTMU determines the free running frequency of the embedded clock oscillator and provides very accurate frequency (period) information for confirmation that a desired frequency, e.g., within 0.25 percent of the desired frequency, is running or an indication of how much and which direction to adjustment the frequency of the clock oscillator to maintain the frequency precision desired. Automatic frequency adjustment of the embedded clock oscillator may be implemented so as to maintain the desired precision frequency thereof. Temperature and voltage compensation profiles for maintaining the accuracy of the CTMU may be stored in a table, e.g., nonvolatile memory, for a further improvement in absolute frequency accuracy of the embedded clock oscillator.

Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

Abstract: An oscillator circuit in accordance with an aspect of the present invention includes a filter capacitor that generates an oscillating frequency control voltage according to a charge amount accumulated based on an oscillating frequency setting current, an oscillator that changes a frequency of an oscillation signal to be output according to the oscillating frequency control voltage, a control circuit that generates a timing control signal, a frequency detection circuit that generates a frequency detection voltage based on the timing control signal, a voltage level of the frequency detection voltage being changed according to a length of the period of the oscillation signal, and a differential amplifier that continuously changes the oscillating frequency setting current according to a voltage difference between the frequency detection voltage and a reference voltage, and outputs the resultant oscillating frequency setting current to the filter capacitor.

Abstract: An oscillator circuit and method for gain and phase noise control. A gain and phase noise controlled oscillator circuit includes a variable electronic oscillator and a tuning loop circuit. In operation, the variable electronic oscillator generates a clock signal and has a clock signal frequency that is controlled by a sense voltage received by the variable electronic oscillator or by one or more capacitive loads coupled to the variable electronic oscillator. Further, the tuning loop circuit is coupled to the variable electronic oscillator and compares the sense voltage to a control voltage received by the tuning loop circuit and produces one or more correction signals based on the comparison, where the one or more capacitive loads change capacitance based on the one or more correction signals.

Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

Abstract: A high-accuracy clock signal is generated even when the settings of the clock frequency are changed or there is a variation in power supply, temperature, or the like. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency.

Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.

Abstract: A resonate power generator is provided. The resonate power generator may include a waveform and sequence memory to record a predetermined waveform and a predetermined sequence, a delta-sigma modulator to delta-sigma modulate an output signal of the waveform and sequence memory, and a waveform recovery unit to receive, as an input, an output radio frequency (RF) signal of the delta-sigma modulator, and to convert the input into a waveform in a form of an impulse.

Abstract: A receiver is provided. The receiver includes a differential amplifier amplifying differential input signals input to input terminals and outputting differential output signals through output terminals and an oscillator connected to the output terminals of the differential amplifier. The differential amplifier and the oscillator operate alternatively in response to an enable signal.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency, calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency at a first calibration frequency when at a steady state temperature and at a second calibration frequency when at a transient temperature, and circuitry configured to generate an output frequency from the oscillator frequency.

Abstract: A VCO device is described that has pre-compensation. Digitally switchable compensation capacitors are selectively activated to adjust operation of the VCO to mitigate undesirable operational effects. In some example embodiments, the digitally switchable compensation capacitors of the VCO are adjusted to compensate for the effects of activating (from a quiescent state) an output buffer driven by the VCO.

Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: Aspects of a method and system for frequency selection using microstrip transceivers for high-speed applications may include determining an operating frequency for operating one or both of a transmitter and a receiver. A frequency response and/or impedance of one or more transmission lines that may be utilized by the transmitter and/or the receiver may be controlled by adjusting one or more capacitances, communicatively coupled to the transmission lines based on the determined operating frequency. The capacitances may be coupled to the one or more transmission line at arbitrary physical spots, and may comprise capacitors and/or varactors. The capacitors and/or the varactors may be adjusted with a digital signal or an analog signal. The capacitances may comprise a matrix arrangement of capacitors and/or varactors. The one or more transmission lines may comprise a microstrip.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: This disclosure relates to a programmable wideband, LC Tuned, Voltage Controlled Oscillator with continuous center frequency select, and independent configuration of amplitude and tuning gain. The programmability can be via on chip non-volatile memory, or through data shifted into the part and stored via a data bus.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (gm) than if a single transistor were used while maintaining the same loop bandwidth and drain-to-source current through the transistor. As a result of a smaller transconductance in the VCO, a larger resistor can be used in the loop filter without increasing the noise. With a larger resistor, a smaller capacitor can be used in the loop filter as well. Alternatively, the transconductance can be reduced by a certain factor and the resistance value can be increased by the same factor to maintain a constant loop bandwidth but with a reduction in the amplitude of the noise. Thus, a smaller loop filter capacitor can be achieved albeit with the same noise level, or a lower noise level with the same size capacitor for the loop filter.

Abstract: A system and method for effectively generating an electronic control signal includes a loop filter that has a first capacitor, a second capacitor, and a damping resistor. The first capacitor typically has a significantly greater capacitance than said second capacitor. A primary charge pump provides a primary charge current to the loop filter, and a damping charge pump provides a damping charge current to the loop filter. The loop filter responsively generates the electronic control signal for regulating the output frequency of a voltage-controlled oscillator. All components of the loop filter are sized to be implemented as part of an integrated circuit device.

Abstract: An oscillator for use in generating a signal having a desired frequency includes a first inductor element being electrically coupled from one end of a first capacitive element to a first voltage connection point, a second inductor element being electrically coupled from one end of a second capacitive element to a second voltage connection point, a third inductor element being electrically coupled from another end of the first capacitive element to the first voltage connection point, a fourth inductor element being electrically coupled from another end of the second capacitive element to the second voltage connection point. The first, second, third, and fourth inductor elements being configured such that a first conductive trace loop formed by the first and third inductor elements is interleaved with a second conductive trace loop formed by the second and fourth inductor elements such that said conductive trace loops are configured to operate in substantially a same magnetic field.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

Abstract: An oscillator for use in generating a signal having a desired frequency includes a first inductor element being electrically coupled from one end of a first capacitive element to a first voltage connection point, a second inductor element being electrically coupled from one end of a second capacitive element to a second voltage connection point, a third inductor element being electrically coupled from another end of the first capacitive element to the first voltage connection point, a fourth inductor element being electrically coupled from another end of the second capacitive element to the second voltage connection point. The first, second, third, and fourth inductor elements being configured such that a first conductive trace loop formed by the first and third inductor elements is interleaved with a second conductive trace loop formed by the second and fourth inductor elements such that said conductive trace loops are configured to operate in substantially a same magnetic field.

Abstract: To provide a reference frequency generating device that can output a highly accurate reference frequency signal even if a reference signal becomes unable to be acquired. The reference frequency generating device includes a synchronization circuit, a temperature sensor, and a controller. The synchronization circuit controls a reference frequency signal outputted from a voltage controlled oscillator, by a control signal obtained based on a reference signal. The temperature detector detects a temperature of the voltage controlled oscillator being used. When the reference signal is unable to be acquired, the controller corrects a voltage controlled signal in consideration of a distortion in the aging characteristic of the voltage controlled oscillator based on a rate of change with time in a slope of the oscillator temperature, and generates a holdover control signal based on corrected contents to control the voltage controlled oscillator.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Abstract: In one embodiment, the present invention includes a method for determining if a frequency control instruction would cause a first capacitor bank to reach a limit and adjusting the first capacitor bank in a first direction using a calibration value and adjusting a second capacitor bank in a second direction if the first capacitor bank would reach the limit. Furthermore, the calibration value may be calculated and stored in accordance with other embodiments. In such manner, small changes in capacitance and correspondingly small changes in frequency may be effected.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.

Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.

Abstract: A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal.

Abstract: Aspects of a method and system for reduced clock feed-through in a phase locked loop are provided. In this regard, a control voltage for controlling a VCO may be generated via a filter comprising at least one switching element clocked via a clock booster circuit and comprising one or more thick oxide transistors to reduce clock feed-through. A first switching element of the filter may be a first transmission gate comprising thick oxide transistors. The first transmission gate may be part of a sample and hold circuit. A DC voltage on an input node of the sample and hold circuit may be periodically reset via a reset switching element, which may comprise thick oxide transistors. The reset switching element may be controlled via a clock booster circuit. The filter may also comprise a buffer having an input stage comprising one or more thick oxide transistors.

Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.

Abstract: An oscillator circuit having a source of an oscillating signal, a tank circuit including an inductor and a capacitor, and a discretely switchable capacitance module configured to control an amount of capacitance in the oscillator circuit. The discretely switchable capacitance module includes, in one embodiment, a capacitor coupled between a first node and a second node, a switch, having a control node, coupled between the second node and a third node; and a DC feed circuit, having a first end coupled to the second node and a second end configured to receive a first or second control signal. The control node of the switch is tied to a predetermined bias voltage. When the first control signal is applied, the capacitor is coupled between the first node and the third node via the switch such that the capacitor is coupled in parallel with the capacitor of the tank circuit, and when the second control signal is applied the capacitor is decoupled from the tank circuit.

Abstract: A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.

Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.

Abstract: A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).

Abstract: A first exemplary aspect of an embodiment of the present invention is a phase-locked loop circuit including: a voltage-current converter that converts a control voltage into a control current, the control voltage generated according to a phase difference between an input pulse signal and a feedback pulse signal fed back from an output side of a current controlled oscillator; the current controlled oscillator that generates an output pulse signal having a frequency according to the control current; a current detection unit that detects the control current; and a frequency range switch that switches a frequency range of the output pulse signal according to the detected control current.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code.

Abstract: Some embodiments disclosed herein relate to techniques for providing a relatively constant oscillation frequency. In some instances, these techniques can make use of a ring oscillator that is powered by an adaptive voltage supply. The adaptive voltage supply provides a temperature-dependent supply voltage to respective delay elements in the ring oscillator, such that the oscillation frequency of the ring oscillator is approximately constant over a predetermined temperature range. For example, if temperature increases, the supply voltage can be increased proportionally, thereby tending to limit variation in the oscillation frequency delivered by the ring oscillator.

Abstract: An FM radio with a wide frequency range operates in a cell phone without interfering with the VCO of the RF transceiver. The FM transceiver generates a VCO signal whose frequency varies by less than ±7% from the midpoint of a narrow first range. A synthesizer signal is generated by dividing the VCO frequency by a first divisor such that the synthesizer frequency varies over a lower frequency second range. The VCO frequency is also divided by a second divisor such that the synthesizer frequency varies over a third range. The upper limit of the second range falls at the lower limit of the third range. The lower limit of the second range is 85.5 MHz and the upper limit of the third range is 108.0 MHz. By also using a third divisor, a synthesizer signal with a range of 76-108 MHz is generated from the narrow first frequency range.

Abstract: A frequency-phase adjusting device includes a first controller, a second controller, and an oscillating circuit. The first controller generates a first control signal according to a target frequency and a current frequency. The second controller generates a second control signal according to the first control signal, wherein the second control signal is related to a first frequency difference, a second frequency difference, and a designated duration. The oscillating circuit adjusts the current frequency according to the first frequency difference, the second frequency difference, and the designated duration. The current frequency is set as a first frequency during a first duration, set as a second frequency during the designated duration, and set as a third frequency during a second duration. The first frequency difference equals a difference between the first frequency and the second frequency, and the second frequency difference equals a difference between the second frequency and the third frequency.