Abstract: A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.

Abstract: A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array (1-N) of cascaded folding amplifier stages, a distributed array of fine comparators, and an encoder. Each folding amplifier stage includes folding amplifiers that are configured to receive inputs from a prior stage, and also generate output signals for the next stage. The folding amplifiers output signals for a given stage are evaluated by a corresponding comparator stage, which may include multiple comparators, and also optionally coupled to an interpolator. The outputs of the comparators from all stages are collectively evaluated by the encoder, which generates the output of the folding ADC. Unlike conventional folding ADCs that require fine and coarse channels, the presently described folding ADC provides conversion without the need for a coarse channel. The encoder can also be arranged to facilitate recursive error correction.

Abstract: An intelligent electronic device (IED), e.g., an electrical power meter, having circuitry for an input structure of an analog-to-digital converter (ADC) that reduces noise of a signal from a sensor in the device, resulting in a highly accurate power measurement, is provided. The circuitry includes a first single-ended analog-to-digital converter with an input from a voltage signal and a second single-ended analog-to-digital converter with an input that is the reference voltage used by the voltage signal. A programmable device subtracts the digital output of the second single-ended analog-to-digital converter from the digital output of the first single-ended analog-to-digital converter to produce a digital result of the voltage signal that is free from common-mode noise.

Abstract: A circuit including an analog-to-digital converter having a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components.

Abstract: A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

Abstract: An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

Abstract: The invention provides an analog-to-digital converter (ADC) of the single ramp type, comprising a ramp generator (101), a clock (102), a digital counter (103) timed by the clock (102), and at least one channel (101, . . . , 10i, . . . , 10n) for data processing, the or each channel comprising a comparator (201, . . . , 20i, . . . , 20n) having an input connected to the ramp generator (101) and the output of which causes for each conversion cycle the storage of the current counter value as a coarse conversion data. According to the present invention, the or each channel (101, . . . , 10i, . . . , 10n) further comprises a delay-chain time interpolator (401, . . . , 40i, . . . , 40n, 501, . . . , 50i, . . .

Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with optical encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.

Abstract: An image processing method for obtaining digital data comprising the steps of obtaining a plurality of image signals under a condition of different accumulation periods as an initial value for a counting operation, comparing, by using digital data for a first image signal of the plurality of image signals, an electric signal corresponding to a second image signal of the plurality of image signals with a reference signal, obtaining digital data for the second image signal, performing a counting operation in a mode having the same sign as the sign of digital data for the first image signal between a down-counting mode and an up-counting mode while the comparing step is being performed, and storing a count value.

Abstract: A most significant bits analog to digital converter for determining a first P bits of an N bit analog to digital conversion, the most significant bits analog to digital converter comprising: a digital to analog converter a capacitive attenuator, and a switching arrangement for inhibiting action of the attenuator during sampling and enabling the attenuator during conversion.

Abstract: An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage.

Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: A Folding Comparator circuit which receives an analog input current and both compares it to a DC reference current while at the same time folding the input current around the reference current to be passed on as an output current which can then be passed on to another folding comparator stage. A series of such stages connected together with some XOR logic gates can perform an analog to digital conversion process as a pipeline of auto-folding stages which will instantly convert analog signal to digital signal.

Abstract: A pipelined analog-to-digital converter includes a plurality of stages each including a sample-and-hold circuit configured to output an analog signal having a current and a current mode analog-to-digital converter configured to compare the current of the analog signal output by the sample-and-hold circuit to current generated by a plurality of current sources and output a digital representation of the analog signal.

Abstract: The conventional A/D converter has a drawback that the conversion precision is degraded when the operation periods of the constituents of the A/D converter are shortened due to the duty ratio of an external input clock because the operation periods of the constituents of the A/D converter depend on the pulse width of the external input clock. However, a highly-precise A/D conversion operation independent of the duty ratio of the external input clock can be realized by providing a circuit for detecting the operation periods of the constituents of the A/D converter, and adjusting the duty ratio of the operation clock according to the detected operation periods of the constituents of the A/D converter.

Abstract: In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

Abstract: An analog to digital converter includes: a reference circuit adapted to generate reference voltages; differential amplifiers; normal phase circuits each of which samples a normal phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a first input terminal of one of the differential amplifiers when the input is differential and single-ended; and reversed phase circuits each of which samples a reversed phase analog input signal and transfers a comparison voltage, obtained by comparison with a reference voltage generated by the reference circuit, to a second input terminal of one of the differential amplifiers when the input is differential and which samples a ground level as a reference voltage of the reference circuit and supplies the reference voltage and comparison voltage to the second input terminal of the differential amplifier when the input is single-ended.

Abstract: A digital-to-analog converter circuit includes: a first subdecoder for receiving a first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving a second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving a third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages that have been selected by respective ones of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting a result of an operation applied to the two reference voltages.

Abstract: Systems and methods for processing a plurality of input signals are provided. A plurality of selection signals are received. Each of the plurality of selection signals is representative of one of a plurality of input signal characteristics. Each of the input signal characteristics is associated with one of the plurality of input signals. The plurality of input signals are converted into at least one digital waveform. A plurality of signal values may be extracted from the at least one digital waveform based on the plurality of input signal characteristics. An output signal may be generated based on each of the plurality of signal values.

Abstract: Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

Abstract: In a solid-state imaging device meeting color image pickup, which an AD converter is mounted on the same chip, the circuit scale and the number of transmission signal lines are reduced and a reference signal suitable for color image pickup is fed to an AD conversion comparing portion. DA converter circuits for two pixels of a repeat unit of a separation filter in the horizontal row direction in a unit of readout are prepared as a functional portion to generate a reference signal for AD conversion. The DA converter circuits generate the reference signals having a tilt in accordance with a color property and varying from an initial value based on a non-color property such as a black reference and a circuit offset. Each reference signal independently outputted from the DA converter circuits is basically directly transmitted through common signal lines to a voltage comparing portion which corresponds to color filters having a common color property through independent signal lines.

Abstract: A current measuring system has an electrical component configured to provide an electrical current representative of a parameter of interest at an output node; and an analog to digital converter having a current input node in electrical communication with the output node of the electrical component.

Abstract: An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.

Abstract: A two-step ADC is provided that achieves significant improvements in the settling time window available for CDAC conversion, FADC sub-ranging and FADC conversion without increasing the amount of chip area or power that are consumed by the ADC. The ADC uses interleaved sampler/buffer circuits to sample the incoming analog signal on different phases of the clock signal. MUXes provide the samples obtained by the sampler/buffer circuits to the CADC and FADC circuits in ping pong fashion in such a way that the CADC and FADC circuits are converting during every clock period. In addition, these improvements are achieved without increasing the number of potential sources of bit decision mismatches in the two-step sub-ranging ADC.

Abstract: A solid-state imaging device includes: pixel circuits arranged in a matrix which perform photoelectric conversion on received light; and an AD conversion unit converting the resultant signal voltage of the photoelectric conversion. The AD conversion unit includes: a reference voltage generation unit generating plural reference voltages which are different from each other within a possible range for a signal voltage; a most significant bit conversion unit that identifies a voltage section including the signal voltage from among the voltage sections each having a corresponding one of the reference voltages as a base point and determines the identified result as the value of the most significant bit of the digital signal; and a least significant bit conversion unit that converts, into the least significant bit of the digital signal, the difference voltage between the signal voltage and the reference voltage as the base point of the identified voltage section.

Abstract: The method and system for converting an analog value into a digital equivalent using a plurality of conversion engines are disclosed. In one embodiment the plurality of conversion engines comprise N DACs associated with M comparators, wherein M is substantially greater than N, wherein M and N are integers, wherein each of the N CAP DACs has an associated P CAP DAC and an N CAP DAC, a method includes generating voltage differences between P CAP DACs and N CAP DACs such that they produce M threshold voltages. The plurality of conversion engines operate in a first phase of the conversion by inputting the produced M threshold voltages to associated inputs of M comparators so that more than one bit can be determined from a sampled signal during each successive approximation trial.

Abstract: Intermediate digital signals Fi(?), Gi(?), i=1, . . . I, are generated, which result from a comparison of reference potentials of the first input analogue signal at a shifted value of its observed argument and with a suitably reduced amplitude to the potential, which is inverse to said potential, of the third input analogue signal at the same shifted value of the observed argument and with the amplitude reduced in said way, the shifted argument values being uniformly distributed within the first half-period. A value U of the voltage is measured at any value of the observed argument as at that time the highest one of the voltages at terminals with said reference potentials. An actual peak amplitude A of the input analogue signals is determined as A=kI,mU where the factor kI,m is a quotient of the peak amplitude of said input analogue signals and of the mean value of the voltage waveform envelope of the reference potentials pertaining to said peak amplitude.

Abstract: An analogue-to-digital (A/D) converter converts an analogue input signal to a digital code representing the analogue input signal. The A/D converter includes a comparator for comparing the input signal with a reference signal, a search logic block for determining the digital code, and an A/D converter arranged for receiving input from the search logic block and for providing the reference signal to be applied to the comparator. At least a first portion of the A/D converter is implemented with equal capacitors and may be controlled by a thermometer coded signal. Additionally, the A/D converter may include a second portion implemented using binary weighted capacitors controlled by a thermometer coded or binary coded signal. The A/D converter may also include a plurality of A/D converters coupled by an analogue addition circuit or a weighted summing amplifier.

Abstract: A system and method, including computer software, for storing digital information uses multiple NAND flash memory cells. Each memory cell is adapted to receive charge during a write operation to an analog voltage that corresponds to a data value having a binary representation of more than 4 bits. An analog-to-digital converter converts the analog voltage from each memory cell into a digital representation of the analog voltage during a read operation of each cell.

Abstract: A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors including a first set of capacitors and a second set of capacitors, a first side of each of the plurality of capacitors being coupled to a common node. The method includes sampling an input voltage on the first set of capacitors, after the step of sampling leaving a side of at least one capacitor of the first set of capacitors floating, coupling a capacitor of the first set of capacitors, which is not floating, with a capacitor of the second set of capacitors so as to redistribute the charge on the coupled capacitors, comparing the voltage on the common node with a comparator reference voltage level to receive a comparison result to be used for a bit decision, and switching the floating side of the floating capacitor of the first set of capacitors to either a first reference voltage or a second reference voltage in accordance with the bit decision.

Abstract: An analog to digital converter is provided in which the outputs of first and second digital to analog converters DAC1 and DAC2 are combined in a combining circuit so as to form a plurality of decision thresholds. This enables two or more bits to be determined in a single trial.

Abstract: There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.

Abstract: A coarse reference ladder provides a plurality of coarse references. A coarse ADC receives an input voltage. The coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output. A switch matrix is configured to close a switch based on the coarse output. An input line corresponding to a coarse reference is coupled to the switch matrix. The input line is precharged to the input voltage. The input line settles from the precharged input voltage to the coarse reference. A fine reference ladder provides a plurality of fine references based on the coarse reference. A fine ADC receives the input voltage and performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output. Logic outputs a digital output for the input voltage based on the coarse output and the fine output.

Abstract: First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

Abstract: An integrated circuit including a single input pin for determining a value associated with a resistor divider. The circuit includes first circuitry for determining a resistor ratio of the resistor divider through the single input pin. A first register stores a first group of bits representing the resistor ratio. The first group of bits comprises the least significant bits of the value. Second circuitry determines an equivalent resistance of the resistor divider through the single input pin. A second register stores a second group of bits representing the equivalent resistance. The second group of bits comprises the most significant bits of the value associated with the resistor divider.

Abstract: A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i?1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i?1)th period.

Abstract: In a pipelined analog-to-digital (AD) converter, if logically incongruent signals S1 and S2 are output from an AD converter section of a converter stage of the AD converter, a digital-to-analog converter (DAC) section is to be prevented from erroneously operating. When a logically incongruent combination of signals S1 and S2, such as S1=“H” and S2=“L”, is output from comparators that compare an input voltage VI to reference voltages +REF/4 and ?REF/4, an encoder outputs a signal corresponding to a normal signal combination (S1=“L” and S2=“H”) to generate signals X, Y and Z that control switches of the DAC section. This eliminates the risk that the switches shall be turned on simultaneously, thus preventing the erroneous operation of the DAC section.

Abstract: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (?) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.

Abstract: An analog-digital converter is provided. The analog-digital converter includes: a comparing section for comparing an input signal voltage and an analog ramp voltage in which a voltage level gradually increases; and a latch section for storing a digital value of a digital ramp signal, in which a digital value of a voltage level gradually increases in synchronization with the analog ramp voltage when the analog ramp voltage or a voltage corresponding to the analog ramp voltage and the input signal voltage are equal. A voltage in which part or all of a plurality of analog ramp signals are added is used as the analog ramp voltage so that a gain is selectable.

Abstract: The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

Abstract: A flash analog-to-digital converter comprising a resistive reference ladder, a set of comparators for comparing the analog input signal with the reference voltages of the ladder to provide a digital code representing a coarse quantization of the input signal, a set of switches connected to the reference ladder and controlled by said digital code to provide an analog representation of the coarse quantization of the input signal, means to derive from said analog representation of the coarse quantization and from the input signal one or more residue signals and a fine analog-to-digital converter stage to generate a digital code representing a fine quantization of the one or more residue signals.

Abstract: A peak detector provides repeatable and accurate measurements of the signal amplitude for variable frequencies of input signals. The peak detector includes a pulse edge generator circuit that generates a pulse edge signal in response to the signal peaks of an input signal and a sampler circuit that is triggered to sample the input signal by the pulse edge signal. The pulse edge generator circuit compares the input signal with a delayed version of the input signal to produce a differential signal and generates the pulse edge signal using the differential signal. An analog or digital sampler is triggered by the pulsed edge signal to measure the information, e.g., peak value, of the input signal. One or more delay circuits may be used to align the edges of the pulsed edge signal with the peaks of the input signal.

Abstract: A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

Abstract: A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.

Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

Abstract: Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.

Abstract: An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

Abstract: A self-tracking analog-to-digital converter includes a digital-to-analog converter (DAC) adapted to provide a variable reference voltage, a windowed flash analog-to-digital converter (ADC) adapted to provide an error signal ek corresponding to a difference between an input voltage Vi and the variable reference voltage, and digital circuitry adapted to generate suitable control signals for the DAC based on the error signal ek. More particularly, the digital circuitry includes a first digital circuit adapted to provide a first function value f(ek) in response to the error signal ek, the first function value f(ek) representing an amount of correction to be applied to the variable reference voltage. A second digital circuit is adapted to provide a counter that combines the first function value f(ek) with a previous counter state Nk to provide a next counter state Nk+1, the next counter state Nk+1 being applied as an input to the digital-to-analog converter.

Abstract: An analog to digital converter comprises a first stage for developing a set of most significant bits from an analog input signal and for producing analog residue signals (RA, RB) corresponding to respective differences between the analog input signal and threshold values directly above and below, respectively, the analog input signal, and a second stage (AMPA, AMPB, ADC2) for developing a set of lesser significant bits from the analog residue signals (RA, RB). According to the invention, the analog residue signals (RA, RB) are reversed (CA, CB). An offset detection unit (COD, DOD) coupled to the second stage (AMPA, AMPB, ADC2) retrieves offset data representative of offset errors, and an offset correction unit (AD1, AD2, OCA, OCB) corrects the offset errors on the basis of the offset data.