Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract: An encoder encoding a communication signal includes a first precoder to precode the communication signal. A signal buffer buffers a first signal associated with the communication signal. A DC tracking block generates a flip signal as function of a statistical measure of the precoded communication signal. The flip signal has a flip state and a nonflip state. A flip unit, responsive to the flip signal, flips an output of the signal buffer such that an average DC value of the precoded communication signal approaches zero.

Abstract: An encoder for enabling selection of output bits that reduce run-length includes classification circuitry, a disparity control circuit, encoding circuitry, and a run-length control circuit. The classification circuitry is configured to receive data in a first bitwidth. An output of the classification circuitry is in communication with the disparity control circuit. The encoding circuitry is configured to encode the data received in the first bitwidth into a second bitwidth. The run-length control circuit is included in the encoding circuit and is selectively triggered in one coding scheme when a contiguous portion of the data of the first bitwidth is of a particular sequence, e.g., all logic ones, to generate a control signal. The run-length control circuit receives as additional inputs outputs of a portion of the encoding circuitry and a disparity signal from the current encoding cycle. The control signal, when generated, reduces run-length of the second bitwidth.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: Techniques are disclosed for translating five-bit source vectors into six-bit coded vectors. A sixth bit having a default value is appended to the source vectors. Selected one to three individual source bits are complemented for a minority of the plurality of source vectors. The coded vectors are either disparity independent with a single representation or disparity dependent with a primary and an alternate representation, where the alternate representation is a complement of the primary representation. Additional techniques are disclosed for translating three-bit source vectors together with one or more control inputs, into nine four-bit coded vectors. A fourth bit having a default value is appended to the source vectors. A single individual bit is complemented for a minority of source vectors.

Abstract: A method of encoding digital information in order to suppress dc includes the steps of receiving a sequence of m message bits of a message word, and mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations. Multiple codeword candidates are generated from the m message bits using the algebraic operations to combine the m message bits with different periodic scrambling sequences. One of the codeword candidates is selected for mapping based upon an optimizing criteria. Second order digital sum sequences, corresponding to each of the plurality of codeword candidates, can be used as the optimizing criteria to select the codeword.

Abstract: A data conversion apparatus of this invention has a storage unit configured to store a conversion table to convert m-bit data into n-bit data, and a conversion unit configured to convert the m-bit data into the n-bit data by using the conversion table stored in the storage unit. The conversion table contains a plurality of bit conversion codes to convert the m-bit data into the n-bit data. The bit conversion code is a code which converts the m-bit data into the n-bit data that allows the minimum number d of consecutive “0” bits between “1” bits.

Abstract: A data dependent scrambler (DDS) for a communications channel that transmits a user data sequence having a plurality of symbols includes a scrambler that generates a scrambled user data sequence that is based on the user data sequence and a seed. A first encoder selectively interleaves adjacent symbols in the scrambled user data sequence if an all-zero symbol is produced by bit interleaving. The first encoder identifies a pivot bit that is adjacent to the all-zero symbol if interleaving is performed and replaces the all-zero symbol with an all-one symbol if the pivot bit is zero.

Abstract: A first set of signals is transformed into a second set of signals having a more stable set of current requirements. The more stable current requirements of the second set of signals are achieved by encoding the second set of signals with either an equal number, nearly an equal number, a constant number, or nearly a constant number of logic ones and logic zeros. A communication channel is provided for carrying the second set of signals from the first node to a second node.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: A system and method for the on-demand transcoding of media content from a source type to a destination type is provided, wherein the system includes a plurality of transcoders for transcoding from a plurality of source types to a plurality of destination types, and wherein the system receives a transcoding request for media content, fetches the media content in response to the transcoding request, sends the media content to one of the plurality of transcoders based on the source type and destination type, transcodes the media content from the source type to the destination type, thereby generating transcoded media content, and transmits the transcoded media content. The system fetches, sends, and transcodes the media content and transmits the transcoded media content in a pipelined fashion. The system also provides for the publication of media content as a file or stream of digital data, for the archiving of media content, and the caching of transcoded media content to improve system efficiency.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2)(b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC but insertion section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: A transmission code which packs six bits of data and four control vectors into an eight-hit format is presented. A direct current (DC)-balanced 6B/8B transmission code is produced from an input data stream that includes one or more six-bit source vectors. A given coded vector is created in accordance with an eight binary digit coded vector set. The given coded vector has eight binary digits and the given coded vector corresponds to a given six-bit source vector. Each coded vector in the eight binary digit coded vector set is balanced. The given coded vector is output.

Abstract: A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A method of determining a merging bit in an optical storage device. The method includes appending one bit to a fourteen-bit set of data output from an eight-to-fourteen modulator, dividing the fifteen-bit set of data into five local digital-sum-values of three bits, adding the five local digital-sum-values to an initial digital-sum-value to generate a sub-digital-sum-value, and generating the merging bit according to the sub-digital-sum-value.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: A method an apparatus for symmetric line coding is provided where a binary input signal d is received; a value for each of a pair of binary bits p and q are dynamically defined in response to the input stream; and a pair of output bitstreams v1 and v2 are dynamically generated in accordance with the following: if d=1, then v1=p and v2=p, and if d=0, then v1=(1?q) and v2=q. In illustrative embodiments of the invention, the generation may be performed by symmetric-line coding machines, including: a bitstream symmetric line coding machine, a regular bitstream symmetric line coding machine, a complementary regular bitstream symmetric line coding machine, a binary complementary regular symmetric line coding machine, a bitstream parallel symmetric line coding machine, a regular bitstream parallel symmetric line coding machine, a complementary regular bitstream parallel symmetric line coding machine, and a binary complementary regular parallel symmetric line coding machine.

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode of data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract: A method for converting a succession of data words into an output bit stream comprising a succession of code words uses a table of code words and associated next state values. For each data word the table provides a code word and associated next state value for each of a plurality of present state values. The code words are either of a first type that correspond to only one data word or of a second type that correspond to more than one data word. The next state value associated with each code word of the second type belongs to one of a first group of states. The next state values ensure that adjacent code words chosen in accordance with the next state values satisfy a run length constraint. Code words belonging to the first group of states can be identified by a unique bit structure.

Abstract: Disclosed herein is a method and system for providing a secondary communication channel overlaid on a primary communication channel using an enhanced encoding method to effectively expand the utilized information capacity of the primary communication channel. Aspects of the invention may include encoding a portion of at least a first word of one or more data packets in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive, i.e., RD(+), then the running disparity is reversed to RD negative, i.e., RD(−). Similarly, if an encoded running disparity is RD negative, i.e., RD(−), then the running disparity is reversed to RD positive, i.e., RD(+). The word may be a data word, control word, or an idle word corresponding to a data packet, a control packet, and an idle packet, respectively.

Abstract: A method and associated structures for coding a sequence of data bytes (BY1,BY2), in which two bits (B1, B2) of a data byte form a double bit (D1-D4). Each double bit is represented by a time slot frame (ZR1-ZR4) that has at least four time slots (ZS1-ZS4). The time slots can assume an on or off value (Z1, Z0). The coding is carried out in a time slot frame such that at least one time slot is preloaded with an off value (Z0) at a position (AF). The time slots that have not been preloaded have, at most, one time slot with an on-value in order to form a logic value (00, 01, 10, 11) of a double bit. The method can be used for identification systems (IS), for mobile data memories (DT) and for reader/writers (SLG). Therein, a higher data rate and/or a greater transmission distance between the reader/writer and the mobile data memory is achieved.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method divides a data word, which a sync signal is to be added in front or rear of when it is written in a recording medium, into two or more word segments, generates for each word segment a number of intermediate sequences by combining mutually different digital words with that word segment, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d, k) constrained sequence, checks how many undesired sub-sequences are contained in each (d, k) constrained sequence, and selects one (d, k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d, k) constrained sequences not having the undesired sub-sequence. Applying this method to a modulating device, DSV control can be conducted by much simpler hardware.

Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0≠q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word.

Abstract: 8b/10b encoding begins when an input running disparity is received. The processing then continues by receiving an 8-bit digital input that includes a 5-bit digital input portion and a 3-bit digital input portion. The processing then continues by determining, in parallel, a 6-bit running disparity and a 4-bit running disparity. The processing then continues by determining a 6-bit digital output based on the 6-bit running disparity and the 5-bit digital input portion. The processing then continues by determining a 4-bit digital output based on the 4-bit running disparity and the 3-bit digital input portion. The resulting 10-bit encoded digital output is the combination of the 6-bit digital output and the 4-bit digital output.

Abstract: A run length limited code recording/reproduction apparatus according to an aspect of this invention includes a generation unit for generating a plurality of different code sequences which have recording densities that gradually become higher, and a recording unit for recording the plurality of different code sequences generated by the generation unit on a plurality of successive subfields in a test data field of an information storage medium.

Abstract: A digital signal modulation method selects a modulation strategy to modulate current M sets of data by determining variations in a digital sum value (DSV) corresponding to the modulated data modulated according to a first modulation strategy from M sets of data ahead of the current M sets of data.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ⅔ which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal.

Abstract: The present invention relates to a coding apparatus for encoding data represented by 8 bit input symbols into 12 bit output codes for serially transmitting the codes along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width and sampled by a receiver at each receiver's clock period. The invention reduces artifacts introduced by sending data at a higher payload rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: The disclosure relates to providing a secondary communication channel overlaid on a primary communication channel, using an enhanced encoding method, to effectively expand the utilized information capacity of the primary communication channel. A portion of at least a first word of one or more packets may be encoded in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive RD(+), then the running disparity is reversed to RD negative RD(−). Similarly, if an encoded running disparity is RD negative RD(−), then the running disparity is reversed to RD positive RD(+). The word may be a data word, control word or an idle word corresponding to a data packet, a control packet and an idle packet, respectively.

Abstract: The present invention relates to a method for compensating asymmetry in a reproduction signal DRSO from an optical recording medium, and to an apparatus for reading from and/or writing to optical recording media using such method. It is an object of the invention to propose a method for compensating an offset in an asymmetric reproduction signal DRSO capable of compensating the offset even if the amplitude of the shortest run-length components is smaller than the asymmetry of the reproduction signal DRSO. This object is achieved by a method for compensating an offset in an asymmetric reproduction signal, whereby an offset compensation signal OFS is subtracted from the reproduction signal DRSO, the offset compensation signal OFS being generated by an offset compensator 11, comprising the steps of: detecting a binary data signal NRZ from the asymmetric reproduction signal DRSO; and using the binary data signal NRZ for obtaining the offset compensation signal OFS.

Abstract: An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b1, b2, b3 . . . bk to a coded sequence c0, c1, c2 . . . cq. The selection circuit selects c0 in the coded sequence c0, c1, c2 . . . cq such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b1, b2, b3 . . . bk to a sequence c1, c2 . . . cq, and a transition minimization circuit to add c0 to the sequence c1, c2 . . . cq. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c0, c1, c2 . . . cq.

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Abstract: A system and method are provided for encoding and decoding a bitstream according to the High level Data Link Control protocol (HDLC) without having to analyze the bitstream bit by bit. An optimized encoder and an optimized decoder are provided. Both encoder and decoder analyze their respective input streams by using a number of bits in parallel as an index into a table, the contents of which control an action by the encoder or decoder that emits in parallel a number of output bits.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data word, a number of intermediate sequences by combining mutually different digital words with that data word, scrambles the intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, measures for each (d,k) constrained sequence, not only an inclusion rate of undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV. smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: Clock information related to a reference clock is distributed from a master network node to a slave network node in an asynchronous packet-based network by embedding the clock information into an additional bit stream and multiplexing the additional bit stream with a primary data stream using an out-of-band channel. Multiplexing the additional bit stream with the primary bit stream using an out-of-band channel may involve selecting yB codes of an xB/yB encoded bit stream to represent bits of the additional bit stream or to balance the running disparity of the xB/yB encoded bit stream. The clock information that is embedded into the additional bit stream is used to generate a clock that is synchronized with a reference clock. In an embodiment, the clock information represents the time difference between a transmitted frame of the additional bit stream and a next edge of the reference clock.

Abstract: Codeword synchronization and scrambler synchronization in a block-coded serial communications link are accomplished by (i) substituting a specific comma control codeword for a selected codeword value occurring in the output of a scrambler receiving an input data stream, and (ii) using selected polarity-independent bits of the block-coded scrambled bit stream to convey samples of the scrambler state. Inversion of received control codewords indicates polarity inversion somewhere along the link, enabling automatic polarity correction to be applied.

Abstract: The present invention relates to method and apparatus of modulating a series of data words into (d,k) constrained sequence in order to record onto a recording medium. The present method generates, for each data word, a number of alternative sequences by combining mutually different digital words with the data word, calculates for each alternative sequence a digital sum value (DSV) and a penalty based on respective consecutive-zeros sections within the sequence and a joining consecutive “zeros” to a previously-selected sequence, and selects one alternative sequence for recording onto a recordable medium based on the calculated DSV and penalties. Owing to the present invention, DC component of sequences to be recorded onto a recording medium is suppressed and stabilization of a reproduction clock is improved through writing more edge information (i.e., “1”s).

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: Managing a primary bit stream involves converting a qB/rB encoded bit stream to an xB/yB encoded bit stream and multiplexing an additional bit stream with the xB/yB encoded bit stream at a transmission side of a link. The additional bit stream is then demultiplexed from the xB/yB encoded bit stream and the xB/yB encoded bit stream is converted back to the qB/rB encoded bit stream at the receiver side of the link. The qB/rB encoded bit stream is converted to and from the xB/yB encoded bit stream so that the additional bit stream can be multiplexed with the qB/rB encoded bit stream using multiplexing/demultiplexing systems that are compatible with the xB/yB multiplexing system. In an application, a 4B/5B encoded bit stream is converted to an 8B/10B encoded bit stream and an additional bit stream is multiplexed with the 10B code-words of the 8B/10B encoded bit stream using code-word manipulation.

Abstract: An ultra-wideband pulse modulation apparatus, system and method is provided. The pulse modulation method increases the available bandwidth in an ultra-wideband, or impulse radio communications system. One embodiment of the present invention comprises a pulsed modulation system and method that employs a set of different pulse transmission, or emission rates to represent different groups of binary digits. The modulation and pulse transmission method of the present invention enables the simultaneous coexistence of the ultra-wideband pulses with conventional carrier-wave signals. The present invention may be used in wireless and wired communication networks such as CATV networks.

Abstract: An ultra-wideband pulse modulation apparatus, system and method is provided. The pulse modulation method increases the available bandwidth in an ultra-wideband, or impulse radio communications system. One embodiment of the present invention comprises a pulsed modulation system and method that employs a set of different pulse transmission, or emission rates to represent different groups of binary digits. The modulation and pulse transmission method of the present invention enables the simultaneous coexistence of the ultra-wideband pulses with conventional carrier-wave signals. The present invention may be used in wireless and wired communication networks such as CATV networks.

Abstract: An input bit stream is encoded into a stream of output code words according to variable-length encoding rules using a variable constraint length. The output-code-word stream observes prescribed run length limiting rules RLL(d, k). Every m-bit piece of the input bit stream is encoded into an n-bit output code word by referring to predetermined M encoding tables following the variable-length encoding rules. CDS (code word digital sum) values are calculated which correspond to respective n-bit output code words. DSV (digital sum variation) control bits are generated in response to the calculated CDS values. The generated DSV control bits are periodically inserted into the input bit stream at intervals each corresponding to a prescribed number of successive bits. The input bit stream is subjected to variable-length encoding while DSV control is implemented in response to the inserted DSV control bits.

Abstract: Methods and apparatus for spreading and concentrating information are taught. The present invention relates to constant-weight encoding of data words on a parallel data line bus while allowing communication of information across sub-word paths.

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.