Abstract: Power consumption required for charging and discharging a source signal line is reduced in an active matrix EL display device. A bipolar transistor (Bi1) has a base terminal B connected to an output terminal c1 of an operational amplifier (OP1), a collector terminal C connected to a low power potential (GND), and an emitter terminal E connected to a resistor R2. A high power potential (VBH) is a potential in synchronization with a high power potential of a light emitting element. A potential of the output terminal c1 of the operational amplifier (OP1) is outputted as a buffer low power potential (VBL). The low power potential (VBL) corresponds to a potential difference between the high power potential (VBH) and a high power potential (V1). Accordingly, the low power potential (VBL) can follow the high power potential (VBH), that is a high power potential of the light emitting element.

Abstract: The present invention relates a display device and a method for driving the same which can improve a picture quality. The display device can include a histogram generation/analysis unit for analyzing image data, generating a histogram of the image data to each of the frames, and analyzing the histograms, a gamma reference voltage generating unit for generating gamma reference voltages and adjusting magnitude of the gamma reference voltages according to a result of analysis and forwarding the gamma reference voltages adjusted, a timing controller for re-arranging the image data, controlling output timings of the image data re-arranged and forwarding the image data re-arranged, and a data driver for generating gamma gradient voltages by using the gamma reference voltages, converting the image data into analog image signals by using the gamma gradient voltages and supplying the analog image signals to a display panel.

Abstract: There is provided an organic light emitting display. The organic light emitting display includes a display unit including pixels coupled to scan lines, control lines, and data lines; a control line driver for providing control signals to the pixels through the control lines; a scan driver for providing scan signals to the pixels through the scan lines; a data driver for providing data signals to the pixels through the data lines; a first power source driver for applying a first power to the pixels of the display unit; a second power source driver for applying a second power to the pixels of the display unit; and a timing controller for controlling the control line driver, the power source drivers, the scan driver, and the data driver. The timing controller is configured to determine a refresh rate of input data to control a length of an emission period in a frame.

Abstract: A driving apparatus of a liquid crystal display device for reducing or automatically restoring a driving current of a light source by being inversed or re-inversed a phase of a driving current with which a light source of a liquid crystal display device is supplied by the human body is disclosed. In the driving apparatus of the liquid crystal display device, a driving controller reduces or restores a duty ratio of a driving control signal which controls a generation of a driving current of a backlight assembly in accordance with whether a predetermined enable signal is applied or not. A master inverter reduces or restores a level of a driving current of the backlight assembly in accordance with a duty ratio of a driving control signal from the driving controller. A slave inverter reduces or restores a level of a driving current of the backlight assembly in accordance with a duty ratio of the driving control signal.

Abstract: For picture updating, an electrophoretic display erases the ghost image and then continuously turns on a plurality of frames, each for changing only one gray level, so as to gradually adjust each of the pixels to a respective desired gray level, which can simplify and accelerate the picture updating, and reduce the content size of a lookup table. By incorporating with adjusting the time length of the frames, the lightness adjustment of the electrophoretic display can be simplified.

Abstract: An electrophoretic display includes a row driver connected to an electrophoretic display panel via a plurality of gate scanlines, and the row driver has a decoder. When the electrophoretic display is to update a picture that includes only a block to be changed, the decoder decodes a start position and an end position of the block to determine a portion of gate scanlines that are occupied by the block, and the row driver drives only the portion of gate scanlines. Therefore, the update time is shorter and the power consumption is less than that for a full update case.

Abstract: A display, a pixel circuitry and an operating method of the pixel circuitry are provided. The display includes a source driver and a pixel circuitry. The source driver converts a first pixel data to a first polarity data voltage and a second polarity data voltage during a first frame period and converts a second pixel data to a third polarity data voltage and a fourth polarity data voltage during a second frame period. The pixel circuitry is coupled to the source driver. The pixel circuitry stores the first polarity data voltage and the second polarity data voltage during the first frame period, displays the first polarity data voltage and the second polarity data voltage during a first sub-period and a second sub-period of the second frame period respectively, and stores the third polarity data voltage and the fourth polarity data voltage during the second frame period.

Abstract: Disclosed here is a driving method for a pixel circuit which includes a light emitting element, a driving transistor for applying current in response to a signal value applied between a gate and a source thereof to the light emitting element when a driving voltage is applied between a drain and the source thereof, and a holding capacitor connected between the gate and the source of the driving transistor for holding the input signal value, the driving method comprising steps carried out within a light emitting period of one cycle which includes a no-light emitting period and the light emitting period, the steps including a first step to a sixth step.

Abstract: A pixel having an improved response time includes an organic light emitting diode connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the organic light emitting diode, the first transistor including a gate electrode connected to a first node; a second transistor connected between a first electrode of the first transistor connected to the first power supply and a data line, the second transistor including a gate electrode connected to a current scanning line; a third transistor connected between a second electrode of the first transistor connected to the organic light emitting diode and the first node, the third transistor including a gate electrode connected to the current scanning line; a fourth transistor connected between the second electrode of the first transistor and the organic light emitting diode, the fourth transistor including a gate electrode connected to a light emitting control line; a fifth transistor connected betwee

Abstract: A gate driving circuit is capable of improving yield by virtue of acquisition of a design margin and reduction of a fabricating cost. The gate driving circuit includes a shift resistor having N stages driven by a start signal and first to fourth clock signals output from the exterior, and an externally input reset signal is applied to reset terminals of the N?1th stage and the Nth stage of the shift resistor, respectively.

Abstract: The projector with at least two light sources for emission of light beams and a projection unit for controllable deflection of the light beams onto a projection surface has a control device to control light output of the light sources and a deflection of the projection unit, and also at least one digital delay element and at least one analog delay element for combined time delay of at least one of the light beams and/or deflection of the projection unit.

Abstract: Provided is image display apparatus, in which a surface to be scanned is two-dimensionally scanned with a light beam which is modulated based on image information and emitted from a light source means and an image formed on the surface to be scanned is observed through an optical system, wherein a synchronization light detection device to obtain synchronization signal related to a scanning start position on the surface to be scanned is disposed on the surface to be scanned, on the vicinity thereof, or on a surface optically conjugate therewith, so that a synchronization signal can be detected with high precision and a preferable quality image can be displayed for observation, and image taking apparatus including the image display apparatus.

Abstract: An electrophoretic display device includes M×N numbers (M, and N are integers more than two) of pixels. The M×N numbers of pixels include M numbers of pixel groups having N numbers of pixels. Further, an image on the electrophoretic display device is displayed by making some of the M×N numbers of pixels switched at least from a bright display to a dark display, and vice versa. A period for displaying one piece of an image on the electrophoretic display is defined as period for forming an image and a period for introducing an image signal to each of the M×N numbers of pixels with sequentially selecting each of the pixels is defined as a frame period. Then, the time for forming an image includes a plurality of frame periods (a numbers of L: L is integers more than two.

Abstract: A power supply circuit which outputs a common electrode voltage to a common electrode of an electro-optical device provided opposite to pixel electrodes through an electro-optical material includes a voltage booster circuit which generates a boost voltage boosted by a charge-pump operation in synchronization with a charge clock signal, and a common electrode voltage generation circuit which outputs a high-potential-side voltage or a low-potential-side voltage generated based on the boost voltage to the common electrode as the common electrode voltage. The charge clock signal has a rising edge and a falling edge in a period in which a sign of voltages between the pixel electrode and the common electrode are either positive or negative.

Abstract: An object of the present invention is to provide a display device consuming lower amounts of power. The display device determines whether or not video signals corresponding to all of pixels in one row of a plurality of pixels are equal to one another. In a case where the video signals corresponding to at least two pixels among the video signals corresponding to all of the pixels in one row of the plurality of pixels, are different from each other, video signals input to an image signal input line are sequentially output to a plurality of source signal lines in synchronization with a sampling pulse output from a shift register. On the other hand, when the video signals corresponding to all of the pixels in one row of the plurality of pixels are equal to one another, input of a start pulse to the source driver is stopped, and the video signals input to the image signal input line are simultaneously output to the plurality of source signal line.

Abstract: A system and method for displaying video images in response to each frame of field-sequential video signals. The system comprises a backlight comprising first, second and third primary color light sources. The backlight is operable to emit light for at most 5.67 milliseconds of each frame (on-time), and to emit no light during the remainder of each frame (off-time). During a portion of the on-time, at least two of the primary color light sources are on simultaneously. For another portion of the on-time, the primary color light sources are on sequentially.

Abstract: In an image display system, when a sequence of frames ?, ?+1, ?+2, ?+3, . . . , with a frame rate of m is given as an input video signal S1, a controller controls a frame memory to output a sequence of frames ?, ?+2, . . . , as an output video signal S2 at a frame rate of m/2 and a sequence of frames ?+1, ?+3, . . . , as an output video signal S3 at a frame rate of m/2 such that the timing of outputting each of frames ?+1, ?+3, . . . , of the output video signal S3 is delayed by 1/m with respect of the timing of outputting each of frames ?, ?+2, . . . , of the output video signal S2. By displaying the output video signals S3 and S2 in the above-described manner, a resultant motion image formed by a combination of the output video signals S3 and S2 is refreshed at an effective frame rate of m.

Abstract: A display device includes a display unit and a plurality of refreshing units. The display unit has a plurality of the display areas. Each of the display areas has a plurality of pixels. Each of the pixels has a memory. The refreshing units respectively control to refresh the pixels of the corresponding display areas at different time periods. Thus, the produced peak current during the pixel refreshing can be reduced, and the stored pixel data can be maintained.

Abstract: A system, apparatus, method and article to switch between video display modes are described. The apparatus may include a graphics device to switch between a progressive mode and an interlaced mode to display media information using a single pixel clock frequency for both modes. Other embodiments are described and claimed.

Abstract: Data enable learning is provided for a video display driver in which a data enable signal and pixel clock exclusive of their associated horizontal and vertical synchronization signals for a digital video signal are used to facilitate generating of signals corresponding to the associated horizontal and vertical synchronization signals.

Abstract: A display device includes a timing controller, a data driver and a gate driver. The timing controller receives a first clock and an image data signal and outputs a second clock having a lower frequency than that of the first clock and the image data signal. The data driver receives the image data signal in synchronization with the second clock and converts the image data signal into a pixel voltage in response to a data control signal. The gate driver outputs a gate voltage in response to a gate control signal generated based on the second clock.

Abstract: A device for driving an image display device that includes an image display panel, a plurality of drivers for driving the image display panel, a Low Voltage Differential Signaling (LVDS) transmission unit for converting external image data and a plurality of control signals including frame ratio setting signals into LVDS signals and transmitting the same, an LVDS reception unit for converting the image data and the plurality of control signals including frame ratio setting signals OP1, OP1 converted into the LVDS signals and transmitted thus into TTL signals and forwarding the same, and a timing controller for aligning the image data to fit to the display frame ratio according to the frame ratio setting signal and the plurality of control signals from the LVDS reception unit and supplying the same to the plurality of drivers, for displaying the image on the image display panel.

Abstract: An image recording apparatus includes an imaging section which images a subject to obtain imaging data. An image quality information acquiring section acquires a plurality of sets of information concerning image quality. An image quality information converting section converts the plurality of sets of information concerning the image quality acquired in the image quality information acquiring section into image processing parameters used in image processing of the imaging data. An image processing section performs image processing with respect to the imaging data based on the image processing parameters converted by the image quality information converting section. A recording section records in a recording medium the imaging data subjected to image processing in the image processing section, or records in the recording medium the imaging data which is not yet subjected to image processing in the image processing section and the plurality of sets of information concerning the image quality.

Abstract: A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a first clock signal from the I2C master to the external memory is synchronized with a second clock signal from the external memory to the I2C master. If the first clock signal is not synchronized with the second clock signal, the pre-scaler stops transmission of a third clock signal for an I2C interface with the external memory to the I2C master.

Abstract: Tonal data of one frame of a video signal is subject to time division into dark subframe tonal data at a low tone and bright subframe tonal data at a high tone to compensate for a lowered luminance in the dark subframe by the bright subframe so as not to change an integrated luminance per one ordinary frame. Subframe tonal data read from a memory is converted into output tonal data constituted of dark subframe tonal data at a low tone and bright subframe tonal data at a high tone, by four arithmetic calculation operations using calculation parameters supplied from a register.

Abstract: A two-terminal switching device provided on each of a plurality of pixel units and connected at a first terminal to a control electrode of a drive transistor, the two-terminal switching device being transferred to a conductive state according to magnitude of the voltage applied to a second terminal to supply the applied voltage to the control electrode; and a reverse bias voltage applying unit for adjusting the voltage applied to the second terminal and applying a reverse bias voltage to the drive transistor are provided.

Abstract: A liquid crystal display device includes a display section, an image signal drive circuit, a scan signal drive circuit, a common electrode potential control circuit, and a synchronous circuit. The display section has scan electrodes, image signal electrodes, a plurality of pixel electrodes arranged in a matrix, a plurality of switching elements for transmitting an image signal to the pixel electrodes, and a common electrode. The common electrode potential control circuit changes an electric potential of the common electrode into a pulse shape, after the scan signal drive circuit has scanned all the scan electrodes and the image signal has been transmitted to the pixel electrodes. Otherwise, the image signal is overdriven. Otherwise, torque for returning to a no-voltage-application state is increased.

Abstract: A scan driving apparatus, includes scan driving blocks, each including a first and a second input terminal where a frame start or a scan signal of an adjacent scan driving block is input during forward and backward direction driving, respectively, wherein each of the scan driving blocks transmits a first scan direction signal instructing forward scan driving to a first transistor adjusting a clock signal in accordance with a signal input to the first input terminal, transmits a second scan direction signal instructing backward scan driving to the first transistor in accordance with a signal input to the second input terminal, and outputs the clock signal as a corresponding scan signal, the even numbered ones of the scan driving blocks receive a first clock signal as the clock signal, the odd numbered ones of the scan driving blocks receive a second clock signal as the clock signal.

Abstract: In order that a boost converter of an LDI can reduce electromagnetic interference by generating a panel driving voltage through the use of a variable frequency, while achieving a stable boosting operation using the same frequency whenever each frame begins, an oscillator generates an oscillation signal having a frequency, which varies in a predetermined pattern or hops in a random pattern around a center frequency, and generates an oscillation signal having a preset fixed frequency whenever each frame begins.

Abstract: A device for driving a light source in an image display device includes input terminals to receive a horizontal synchronization signal and a control signal, an oscillator to generate a reference signal having a frequency, a controller to modulate the reference signal in response to the control signal and output a modulated signal, and a phase difference detecting unit to receive the horizontal synchronization signal and the modulated signal and detect a phase difference between the horizontal synchronization signal and the modulated signal to generate an output signal indicating the phase difference. The oscillator adjusts the frequency of the reference signal in response to the output signal of the phase difference detecting unit so that the horizontal synchronization signal and the reference signal are synchronized with each other.

Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.

Abstract: A transmitter includes a pair of output terminals which output an image data, and a transmitting unit. When the transmitting unit outputs the image data, a first output terminal of the pair is connected to a reference electric potential and a second output terminal of the pair is to a floating state, based on the image data. When the transmitting unit does not output an image data, the first and second output terminals of the pair become to a floating state.

Abstract: A driving method of an LCD device adapted to improve the quality of pictures is disclosed. The driving method includes: deriving a frame detection signal from a data enable signal and a data clock signal; simultaneously deriving a start signal and a first gate clock signal from the frame detection signal and the data clock signal; and deriving a second gate clock signal from the first gate clock signal and the data clock signal. The first gate clock signal is identical with the start signal in a start time point of enable interval.

Abstract: Disclosed is a liquid crystal driving device, which is without a gate PCB, having improved uniformity of screen, and a driving method thereof. The liquid crystal driving device comprises: a sequence recognition means for recognizing sequence of a pertinent gate driver IC by a pulse width of a vertical start signal inputted in synchronization with a vertical synchronous signal, and generating a Carry signal and location data of the pertinent gate driver IC; and gate-off voltage generation means for receiving a first gate-off voltage and the location data of the pertinent gate driver IC, and outputting a second gate-off voltage which is generated by subtracting a voltage attenuation quantity corresponding to the location data of the gate driver IC from the first gate-off voltage.

Abstract: A display apparatus including a display, a video processor to output an video signal to the display, a power supply to output a power signal to turn on/off the display, and a controller to control at least one of the power supply and the video processor to make a sequence difference between an enable/disable time of the video signal outputted form the video processor and an on/off time of the power signal outputted from the power supply be within a predetermined range. The display apparatus and a control method thereof, in which the sequence difference is adjusted to be within a predetermined range.

Abstract: A display driving apparatus includes: n level shift units shifting a voltage level of n pixel data; a step potential providing unit providing a step potential; a change judgment unit judging whether or not each of the n pixel data has changed from pixel data of an immediately previous cycle; a delay unit generating n timing signals changing with different timings; and a control unit performing control such that the display output terminal corresponding to the pixel data judged to have changed by the change judgment unit is provided with: the step potential provided by the step potential providing unit during a first time period included in each of the cycle; and a potential shifted by the corresponding level shift unit during a second time period that is different from each other and is based on a timing of change of the corresponding timing signal.

Abstract: A plasma display apparatus includes a plasma display panel having a plurality of sustain electrodes and a plurality of scan electrodes, a driver circuit to apply sustain pulses to the plurality of sustain electrodes and the plurality of scan electrodes to generate sustain discharges, and a control circuit to control the driver circuit such that a total light emitting pulse count defined as a total number of sustain pulses in one display frame is set equal to a predetermined pulse count defined as a function of a display load ratio, and such that the total light emitting pulse count is set lower than the predetermined pulse count upon detecting a predetermined condition, wherein the control circuit is configured to cause the driver circuit to selectively generate first sustain pulses with timing for clamping to a predetermined voltage being first timing and second sustain pulses with timing for clamping to the predetermined voltage being second timing, and configured to cause a ratio between a number of the fi

Abstract: A driver circuit usable for a display panel can generate an output signal in response to an input pulse signal supplied to only one input signal terminal thereof. The driver circuit includes a pulse generating circuit for generating an output signal at the output terminal. The pulse generating circuit has a first and second differential input stage for respectively driving a push-pull construction of output transistors in response to the input pulse signal supplied through the input signal terminal with respect to the push-pull output, whereby to simplify the circuitry, operate at a high slew rate, and decrease electric current consumption.

Abstract: A liquid crystal display device including a liquid crystal panel, a gate driver configured to drive a plurality of gate lines on the panel, a data driver configured to drive a plurality of data lines on the panel in response to the pixel data stream, a timing controller configured to control the gate driver and the data driver, and a single-chip drive voltage generating section configured to supply voltages used by the common electrode on the liquid crystal panel, the gate driver, the data driver, and the timing controller using an external input voltage.

Abstract: The present invention relates to a wearable electronic device, a viewing system comprising the wearable electronic device, a display device and methods for operating a wearable electronic device and a viewing system, respectively, wherein the wearable electronic device comprises a pair of glasses which can be controlled to change their optical state in a way to allow other and more flexible use of the equipment. The wearable electronic device for watching images comprises a left glass and a right glass which are adapted to change between a dark state and a transparent state of the glass and a controller operable to control the state of the glasses synchronous with a display of a plurality of images per second by a display device so that said left glass and said right glass are both in a dark state at the same time for a specific displayed image.

Abstract: A scan signal transmission system and a method thereof are provided, which are applicable to a display device. The system includes a display area circuit and a gate circuit, the display area circuit has a plurality of pixel scan lines, and the gate circuit is connected to each of the pixel scan lines. The gate circuit is used for obtaining a scan signal from a clock generator, so as to transmit the scan signal to each of the pixel scan lines sequentially. During each frame scan operation, the gate circuit transmits the scan signal to the pixel scan lines in a reverse signal transmission direction.

Abstract: A driving circuit includes a plurality of scanning lines, a plurality of data lines, a plurality of capacitor lines, pixels, a scanning line driving circuit, a capacitor line driving circuit, a first capacitive signal output circuit, and a data line driving circuit. Each of the pixels includes a pixel switching element, a pixel capacitor, and a storage capacitor. The capacitor line driving circuit supplies a first capacitive signal to the capacitor line when the one scanning line is selected, and changes a voltage value of the first capacitive signal when a scanning line, located a predetermined number of scanning lines away from the one scanning line, is selected. The first capacitive signal output circuit adjusts and outputs a voltage of the first capacitive signal when the one scanning line is selected. The data line driving circuit supplies the pixels with data signals of voltages corresponding to gray scale levels.

Abstract: An apparatus for driving a display device includes a timing controller and a data driver. The timing controller encodes first gray scale data of a present frame, decodes encoded second gray scale data of a previous frame, compares the first gray scale data with the second gray scale data, and generates compensated gray scale data based on a result of comparing the first gray scale data with the second gray scale data. The data driver generates data signal based on the compensated gray scale data to provide the data lines with the data signal. The gray scale data are encoded so that the toggle number between adjacent data pins into which the gray scale data are output may be reduce. The encoded gray scale data are stored in a memory. Thus, the power consumption is reduced, and the EMI may be reduced.

Abstract: A display driving apparatus according to an implementation of the present invention includes: a first delay circuit that generates latch control signals changing with different timings; a second delay circuit that generates falling delay signals and rising delay signals by delaying the latch control signals; a delay selection circuit that (i) selects the falling delay signals or the rising delay signals when pixel data for adjacent display output terminals have changed in different directions and (ii) selects the latch control signals when pixel data for adjacent display output terminals have changed in the same direction; and a step control circuit that drives the display output terminals with timings of the signals selected by the delay signal circuit.

Abstract: A plasma display apparatus and a method of driving the same are disclosed. The plasma display apparatus includes a plurality of scan electrodes, a plurality of data electrodes, a scan driver and a data driver. The scan driver scans the plurality of scan electrodes during an address period in one scanning type of a plurality of scanning types having different scanning orders. Further, the scan driver supplies a scan signal, of which the duration of a voltage rising period is different from the duration of a voltage falling period, to the scan electrodes when scanning the scan electrodes. The data driver supplies a data signal to the data electrodes depending on the scanning type selected from the plurality of scanning types.

Abstract: A pixel clock generating device includes a time interval detection unit detecting a time interval between a first signal and a second signal in each of cyclically repeating N (?2) time periods; a comparing unit cyclically selecting a target value from N target values corresponding to the N time periods and outputting an error indicating a difference between the detected time interval and the selected target value for each of the N time periods; a frequency calculation unit correcting a frequency of the pixel clock signal based on the error and cyclically generating a frequency specification signal indicating the corrected frequency for each of the N time periods; a high-frequency clock generating unit generating a high-frequency clock signal; and a pixel clock generating unit generating a pixel clock signal based on the frequency specification signal and the high-frequency clock signal.

Abstract: A display device includes a display unit in which pixels are arranged in a matrix state and a drive circuit selecting respective pixels in the display unit by each row and giving additional potential to pixel electrodes of the pixels by using coupling, in which the drive circuit has a function of allowing the reverse polarity of potential added to pixel electrodes to be a potential which can add suitable voltage to additional potential lines in a frame before adding the additional potential.

Abstract: A liquid crystal display (LCD) capable of enhancing display quality includes a voltage generation unit, a clock generation unit, a gate driving unit, and a display unit. The voltage generation unit outputs a gate-on voltage and first and second gate-off voltages that are different from each other. The clock generation unit outputs a first clock signal and a second clock signal whose phase is opposite to the phase of the first clock signal. The first clock signal swings between the gate-on voltage and the first gate-off voltage. The gate driving unit is provided with the first clock signal, the second clock signal, and the second gate-off voltage and outputs a gate signal. The display unit includes a plurality of pixels that are turned on or off in response to the gate signal and that display an image.

Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Abstract: A data driver connected to the display panel and applying an image data signal to the plurality of pixels; a scan driver connected to the display panel and applying an image scan signal to the plurality of pixels for the image data signal to be applied to the plurality of pixels, and a signal controller controlling the data driver and the scan driver. The data driver applies a data signal having a predetermined pattern to the display panel in a data porch period for adjusting synchronization between frames. The data signal applied during the data porch period may be determined in accordance with frames adjacent the data porch period.