Abstract: A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.

Abstract: An integrated circuit device includes: a data driver that drives a plurality of data lines of an electro optical device; and a data distribution circuit that supplies data to the data driver, wherein the data driver includes an odd numbered data line driver circuit for driving odd numbered data lines among the plurality of data lines, an even numbered data line driver circuit for driving even numbered data lines among the plurality of data lines, an odd numbered data line latch circuit provided for the odd numbered data line driver circuit, and an even numbered data line latch circuit provided for the even numbered data line driver circuit; and the data line distribution circuit, upon receiving time serially inputted image data, supplies odd numbered data line image data for the number of multiplexes to the odd numbered data line latch circuit, and supplies even numbered data line image data for the number of multiplexes to the even numbered data line latch circuit.

Abstract: Disclosed is an LCD driver IC including: a POR (Power On Reset) circuit; and a counter, which receives a signal from the POR circuit to delay time and releases a RESETB of the POR circuit after power of a gate driver IC is stabilized.

Abstract: A driving circuit that switches a light emitting element between an ON state and an OFF state in synchronization with an input signal is provided. The circuit includes a driving current supply unit that has a control terminal and supplies the light emitting element with a driving current whose value changes with dependency on the potential of the control terminal; a control unit that changes the potential of the control terminal in synchronization with the input signal; and a supplementary current supply unit that supplies the control terminal with a supplementary current that promotes change in the potential of the control terminal. The supplementary current supply unit has a capacitor, a voltage that is applied to the capacitor changes in synchronization with the input signal, and the supplementary current is generated by change in the voltage of the capacitor.

Abstract: A disclosed control device includes a first unit configured to generate image data of multiple images to be superposed one on the other to form a single image and transmit the image data. The second control unit transmits to the first control unit a horizontal sync reference signal for achieving synchronization of the images in a horizontal direction. Based on the horizontal sync reference signal, the first control unit transmits to the second control unit a transfer clock signal that indicates transmission timing of the image data and an effective area signal that indicates an effective area of the image data. The first control unit asserts the effective area signal for an effective-area-signal assertion period that occurs between two consecutive reference-signal assertion periods during which the horizontal sync reference signal is asserted.

Abstract: A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

Abstract: A scanned beam display device scans a beam to paint an image. The beam is scanned in two dimensions and includes at least one sinusoidal component. Phase offsets are introduced to provide different scan trajectories for successive traversals of the image field of view.

Abstract: The present invention relates to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter.

Abstract: An exemplary gate output control method includes the following steps: providing a gate control signal; using an angling control signal to angling modulate the gate control signal so as to generate a modulated gate control signal; and supplying the modulated gate control signal to a first integrated gate driver circuit and a second integrated gate driver circuit, to sequentially control the gate outputs of the first integrated gate driver circuit and the second integrated gate driver circuit. A duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the first integrated gate driver circuit is different from another duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the second integrated gate driver circuit.

Abstract: An image privacy protecting method is provided. Positions of a privacy protecting region and a normal display region are acknowledged first. When a frame of image is processed, a first image data will be displayed in the privacy protecting region is processed in a narrow viewing mode to obtain a narrow viewing driving data, and a second image data will be displayed in the normal display region is processed in a wide viewing mode to obtain a wide viewing driving data. Finally, display operations are performed in the privacy protecting region and the normal display region respectively according to the narrow viewing driving data and the wide viewing driving data.

Abstract: An image processing circuit turns off the writing unit of the controller of the DRAM when the previous frame is identical to the current frame. In this way, the writing unit of the controller of the DRAM does not write the current frame into the DRAM, thereby reducing power consumption.

Abstract: The method adjusts the phase of a quantization clock signal for a video signal automatically based on a received analogue video signal. The method includes a step of determining a horizontal start position and a horizontal end position of a pixel-level transition within the analogue video signal, a step of determining a stable-period start position and a stable-period end position at each transition by sequentially changing an adjustable phase of the quantization clock signal, a step of calculating an appropriate phase of the quantization clock signal based on the determined timings of the beginning and end of the stable periods within the analogue signal, and a step of setting the phase of the quantization clock signal to the calculated appropriate phase.

Abstract: A driving circuit includes digital/current converting (DCC) circuits one for each data line. The DCC circuit charges a capacitor with a reference current according to a supplied signal from a shift register. The DCC circuit stores a current value of the reference current and outputs the current value to a data line via a switching element turned on by a digital image data signal of a single line supplied from a line latch. The output value of each DCC circuit is reset one after another in every select scan period in which an OFF signal is sent to all the data lines. Thus, the reset of the output value and the output of the image data signal can be successively carried out within one frame period, so the data applied to the pixel circuit with the DCC circuits one for each data line.

Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Abstract: A liquid crystal display is provided. The liquid crystal display includes a liquid crystal display panel, a data driving circuit for converting digital video data into positive/negative data voltages to be supplied to the data lines and adjusting the horizontal polarity inversion cycle of the positive/negative data voltages, and a timing controller for generating the vertical polarity control signal and the horizontal polarity control signal, adding a FRC correction value to input digital video data to supply the input digital video data to the data driving circuit, detecting a predetermined weak pattern from the input digital video data and, when data having the weak pattern is detected, changing either the logic inversion cycle of the vertical polarity control signal or the logic of the horizontal polarity control signal and changing the position of the data to which the FRC correction value is added.

Abstract: A display driver generates a respective charge pumping signal and respective driving signals synchronized to a respective same clock signal for each of the CPU and video interface modes. Because such respective signals are synchronized to a respective same clock signal, the noise superimposed on the driving signals applied on a display panel is regular and uniform across the whole display panel, for each of the CPU and video interface modes. Accordingly, affects of such regular noise are advantageously not noticeable to the human eye, for both the video and CPU interface modes of operation.

Abstract: A contact detecting device includes: n driving electrodes that are arranged in a scanning direction; a detection drive scanning unit that selects continuous m (2?m<n) driving electrodes out of the n driving electrodes, simultaneously AC-drives the selected m driving electrodes, and repeats shift operation for changing selection targets of the m driving electrodes in the scanning direction such that one or more driving electrodes common before and after the shift operation performed each time are included in the selection targets; plural detection electrodes that form capacitors, between which and the respective n driving electrodes capacitors are formed; plural detection circuits that are connected to the plural detection electrodes and compare potentials of the detection electrodes corresponding thereto with a predetermined threshold every time the detection drive scanning unit performs the shift operation.

Abstract: A shift register of an LCD device operates based on two clock signals and maintains the gate voltage of an output transistor switch using two pull-down transistor switches. The gate voltages of the pull-down transistor switches are switched periodically between the high and low level of the clock signals. During the output period, the transistor switches have negative gate-source voltages so as to reduce leakage.

Abstract: A television display system including a display system controller, a transmitter, and an integrated timing controller. The display system controller receives pixel data and pixel timing and control data, and responsive to a pixel data format corresponding to a selected communication standard of a plurality of communication standards that includes LVDS and at least one of RSDS and mini-LVDS, provides formatted pixel data formatted according to the pixel data format of the selected communication standard. The transmitter receives the formatted pixel data, and transmits the formatted pixel data for receipt according to a pixel data rate corresponding to the selected communication standard.

Abstract: An object of the present invention is to provide a display device consuming lower amounts of power. The display device determines whether or not video signals corresponding to all of pixels in one row of a plurality of pixels are equal to one another. In a case where the video signals corresponding to at least two pixels among the video signals corresponding to all of the pixels in one row of the plurality of pixels, are different from each other, video signals input to an image signal input line are sequentially output to a plurality of source signal lines in synchronization with a sampling pulse output from a shift register. On the other hand, when the video signals corresponding to all of the pixels in one row of the plurality of pixels are equal to one another, input of a start pulse to the source driver is stopped, and the video signals input to the image signal input line are simultaneously output to the plurality of source signal line.

Abstract: A method for reducing temperature-caused degradation of the performance of a digital reader comprising pixels, the method including positioning at least one sheet of compressed particles of exfoliated graphite adjacent to a plurality of the pixels of the digital reader.

Abstract: A plasma display device is provided. The plasma display device can prevent the generation of complementary bright spots or the occurrence of voltage peaking by adjusting the time to apply a bias voltage during a reset period. Thus, it is possible to improve the discharge properties and picture quality of a PDP.

Abstract: A display includes a display panel, a pixel driving unit and a power supply for supplying power to the pixel driving unit. The display panel includes a plurality of pixels arranged in a matrix manner. The pixel driving unit is used for driving the pixels. The power supply includes an input power source, an output capacitor for providing an output voltage, and a control unit for controlling the input power source, such that in a frame period, the input power source charges the output capacitor during the non-refreshing duration of the pixels by the input power source and stops charging the output capacitor during the refreshing duration of the pixels.

Abstract: A level shifter for use in LCD display applications is provided which includes a group of separate channels each with a signal input and a signal output and with channel control circuitry supporting gate voltage shaping for improving image quality. The level shifter further has a number of flicker clock inputs. The channel control circuitry of each particular channel in the group comprises logic circuitry combining all of said flicker clock inputs with the signal input of the particular channel and signal inputs form other channels into a gate voltage shaping enable signal for the control circuitry of the particular channel. With this configuration it is possible to use the same level shifter IC with only one flicker clock signal for all phases, regardless of how many, without the need for an additional synchronization signal, or multiple flicker clock signals as is conventional.

Abstract: A source driver, an operation method thereof, and a flat panel display using the same are provided. The source driver includes a data channel, a switch and a switch controller. The data channel latches a pixel data according to timing of a line letch signal, and converts the latched pixel data to a driving signal for driving a display panel. The data channel decides a polarity of the driving signal according to a polarity signal. A first end of the switch is coupled to the data channel to receive the driving signal. The switch controller adjusts a pulse width of the line letch signal to obtain a control signal for controlling the switch according to the polarity signal. A pulse width of a first pulse is smaller than that of a second pulse in the control signal after the polarity signal is changed.

Abstract: Example embodiments include display driver systems having a host with an external image signal receiving unit configured to receive an external image signal and a graphic control unit configured to transmit input control signals. The systems further include a display driver integrated circuit configured to receive the input control signals, generate a screen display sync signal by using a main clock signal when the external image signal includes a moving image, and generate a screen display sync signal by using an internal clock signal when the external image signal includes a still image, the display driver integrated circuit including.

Abstract: The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.

Abstract: An image display system synchronizes the display of images on a plurality of display devices. The method entails generating at a first computer system a first signal representing first image data to be displayed on a first display device, generating at a second computer system a second signal representing second image data to be displayed on a second display device, and a method for synchronizing the first and second image data. The synchronizing method includes using a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.

Abstract: A digital-to-analog converter, in which a plurality of reference voltages that differ from one another are grouped into first to (S+1)th reference voltage groups, includes a decoder and an amplifying circuit. The decoder includes: first to (S+1)th subdecoders for selecting respective ones of reference voltages corresponding to a value of a first bit group on an upper bit side of an input digital signal from the reference voltages of the first to (S+1)th reference voltage groups; and an (S+1)-input and 2-output type subdecoder for selecting and outputting two reference voltages out of reference voltages selected by the first to (S+1)th subdecoders, in accordance with a value of a second bit group on a lower side of the input digital signal. The amplifying circuit receives the two reference voltages as inputs and outputs a voltage level obtained by interpolation at a prescribed ratio.

Abstract: A flat panel display is provided. In particular, a flat panel display including a driving circuit in which a timing controller and a data driver for driving a panel are mounted in a single IC, and a driving circuit thereof are provided. The flat panel display includes a display panel having a plurality of pixels, a gate driver controlling the plurality of pixels, and a plurality of driving circuits processing and converting an image signal and outputting the same to a display panel in a normal mode. The driving circuits generate a black image signal according to a synchronization signal.

Abstract: A method of operating an AC mercury lamp and DMD (Digital Micromirror Device) in a projection system, comprising receiving a periodic video frame pulse signal, switching the DMD between successive on and off states during each period of the frame pulse signal, wherein each off state results in a dark interval, and driving the lamp with a signal that is synchronized to the video frame pulse signal so as to alternate between a maintenance pulse level during at least a portion of the dark interval and a plateau level during the on state of the DMD.

Abstract: In order to facilitate printing of an image drawn on an electronic board while improving security, an MFP includes a portion to generate conference identification information in response to reception of a start instruction from an electronic board, a portion to associate the conference identification information with device identification information for the electronic board, a portion to associate image data received from the electronic board with conference identification information lastly associated with the device identification information for the electronic board, a portion to associate user identification information received from the electronic board with conference identification information lastly associated with the device identification information for the electronic board, a portion to authenticate a user, a portion to extract conference identification information associated with the user identification information for the authenticated user, a portion to extract image data associated with the c

Abstract: One aspect of the present invention relates to a display for displaying data. In one embodiment, the display includes a timing controller (TCON) configured to provide a plurality of data signals to be displayed, at least one clock signal and a data training code corresponding to at least one clock signal; a plurality of source drivers, each source driver configured to receive one or more corresponding data signals, the at least one clock signal and the data training code from the TCON, generate a plurality of data phase signals according to the one or more corresponding data signals, select one data signal from the plurality of data phase signals as an optimal data signal according to the data training code, and latch the one or more corresponding data signals according to the optimal data signal; and a display panel configured to display the plurality of latched data received from the plurality of source drivers.

Abstract: One aspect of the present invention relates to a display for displaying data. In one embodiment, the display includes a timing controller (TCON) configured to provide a plurality of data signals to be displayed, at least one clock signal and a clock training code corresponding to the plurality of data signals; a plurality of source drivers, each source driver configured to receive one or more corresponding data signals, the at least one clock signal and the clock training code from the TCON, generate a plurality of clock signal according to the at least one clock signal, select one clock signal from the plurality of clock signals as an optimal clock signal according to the clock training code, and latch the one or more corresponding data signals according to the optimal clock signal; and a display panel configured to display the plurality of latched data received from the plurality of source drivers.

Abstract: The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission.

Abstract: The wall charge is appropriately adjusted in the initializing period, and occurrence of an abnormal discharge and an unlit cell is suppressed in the address period. Therefore, a plasma display device has a plasma display panel having a plurality of discharge cells including a display electrode pair that is formed of a scan electrode and a sustain electrode, and a scan electrode driving circuit. The scan electrode driving circuit disposes a plurality of subfields having an initializing period, an address period, and a sustain period in one field, generates a decreasing down-ramp voltage in the initializing period, and generates a negative scan pulse voltage and applies it to the scan electrodes in the address period. In the initializing period, after the generation of the down-ramp voltage, the scan electrode driving circuit generates negative pulse voltage lower than the minimum voltage of the down-ramp voltage and applies it to the scan electrodes.

Abstract: A switching circuit and a DC-DC converter including the same are provided. The switching circuit includes an output terminal, a plurality of input terminals, and a plurality of switches configured to selectively connect the plurality of input terminals to the output terminal. The plurality of switches include a first switch directly connected to the output terminal and a plurality of second switches connecting the plurality of input terminals to the first switch. The first switch is implemented using a high-voltage transistor. Each of the second switches is implemented using a low-voltage transistor. A gate of the high-voltage transistor is at least two times longer than a gate of the low-voltage transistor. The DC-DC converter increases or decreases a signal selected from among a plurality of input signals input through the input terminals by a predetermined voltage level.

Abstract: A display device and a driving method of the same are provided. The display device includes a display panel having gate lines and data lines. A gate driver is included in each of stages and supplies each of the plurality of gate lines with gate signals using a clock signal and a clock bar signal. Each of the stages includes a gate output terminal through which the gate signal is outputted, a pull-down unit connected to the gate output terminal that pulls down a level of the gate signal using a first gate-off voltage. A holding unit is connected to the gate output terminal and holds the level of the pulled-down gate signal at a level of a second gate-off voltage using the second gate-off voltage, which is higher than the first gate-off voltage.

Abstract: A display device includes a skew compensating type data receiving unit for delaying clocks received in response to a program signal, comparing the clocks delayed thus to compensating clocks, setting an internal delay amount according to a result of the comparison, and delaying and forwarding a low voltage differential signals according to the delay amount set thus, a clock receiving unit for delaying the clock received thus by a fixed delay amount and forwarding the clock delayed thus as a compensating clock, a clock generating unit for generating a data restoring clock by using the clock delayed thus, and a data restoring logic for restoring the low voltage differential signal delayed at the data receiving unit in synchronization with the data restoring clock, thereby compensating for an internal skew taking place at the data channel which receives a low voltage differential signal.

Abstract: When there is a circuit that has to wait for one frame cycle to switch LCD resolution, a user feels uncomfortable because the resolution is switched while the screen is temporarily turned off and blackened or while the screen does keep display but causes flickers. When the user switches to an application that will display in QVGA mode on the LCD while the LCD is displaying in VGA mode, a synchronization signal, etc. are stopped from being output from an LCD controller within a vertical blank period (step S2). Then, a pseudo vertical synchronization signal whose cycle falls within the vertical blank period is generated by the LCD controller to trigger a circuit in a par/ser converting circuit triggered by a vertical synchronization signal (steps S3 to S5), and to realize resolution switching (steps S6 to S8). This prevents blackening/flickering of the screen when the resolution is switched.

Abstract: A liquid crystal display (LCD) device and a driving method thereof are provided. The LCD device includes a display panel including pixel units, a data driving circuit, and a gate driving circuit. The gate driving circuit provides a first gate off voltage to one pixel unit of the pixel units when the data driving circuit provides a data voltage having a positive polarity to the pixel unit, the gate driving circuit provides a second gate off voltage to one pixel unit of the pixel units when the data driving circuit provides a data voltage having a negative polarity to the pixel unit. The second gate off voltage is less than the first gate off voltage.

Abstract: A liquid crystal display comprising: a receiver for receiving power and differential signal; a backlight power supply which supplies the power to a backlight unit; a power-off sensor which senses power-off of the backlight power supply and distorts one of the differential signals; and a controller which senses the distortion of the differential signal and generates an after-image removing gray-scale signal.

Abstract: Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

Abstract: A method of driving an electro-optical device having scanning lines, data lines, a switching transistor and a pixel electrode. The device also has an electro-optical layer interposed between the pixel electrode and a counter electrode. The method includes: supplying a data signal alternate between a positive and a negative voltage to the pixel electrode. The positive voltage has a potential greater than a counter electrode potential applied to the counter electrode and the negative voltage is a potential lower than the counter electrode potential; setting the counter electrode potential to reduce a flicker; supplying a first voltage that is either the positive or negative voltage to the pixel electrode in a first period; the other voltage to the pixel electrode in a second period. A ratio of the first period to the second period is variable.

Abstract: A method and system are implemented to dynamically control a display refresh rate. Specifically, one embodiment of the present invention sets forth a method, which comprises the steps of driving a display device at a first refresh rate over a period of time, measuring a number of first content frames with changes in content out of a plurality of content frames that are generated over the period of time for the display device, and driving the display device at a second refresh rate if the number of the first content frames meets a first condition associated with a first threshold reference, and optionally driving the display device at a third refresh rate if the number of first content frames meets a second condition associated with a second threshold reference.

Abstract: A liquid crystal display device includes a liquid crystal panel, a driving circuit and a backlight unit supplying light to the liquid crystal panel. The liquid crystal display device further includes a power management unit. The driving circuit includes a plurality of sub-circuits. The power management unit may provide a common voltage to the driving circuit and the backlight unit. A driving method of the liquid crystal display device includes halting an image display operation of a liquid crystal panel in response to a change of an operation mode. The driving method further includes sequentially changing operations of the plurality of sub-circuits.

Abstract: Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

Abstract: A display control apparatus is capable of reducing image scaling times, maintaining image quality, and extending a turn-on time of a pair of 3D glasses. The display control apparatus includes a data processing unit and a timing generating unit. The data processing unit provides an image frame comprising a valid data region, which is larger than a visual region of a display panel. The timing generating unit generates an output timing signal according to a relative position of the visual region corresponding to the valid data region, so that a partial region of the valid data region corresponds to the visual region of the display panel. The partial region of the valid data region is displayed in the visual region of the display panel according to the output timing signal.

Abstract: An apparatus for driving a display includes a shift register, a first latch unit, a second latch unit, a data comparison unit and a level select unit. The shift register generates multiple latch signals according to a sync signal. The first latch unit latches a data signal in response to the latch signals to obtain multiple first data corresponding to multiple channels. The second latch unit is coupled to the first latch unit and latches the first data of the channels as multiple second data in response to a latch data signal. The data comparison unit responds to the latch data signal to respectively compare the first data and the second data corresponding to the same channel to output multiple third data corresponding to the channels. The level select unit selects multiple voltage levels corresponding to the channels according to the third data.

Abstract: A video graphics array (VGA) interface switch apparatus includes first to third VGA interfaces, a single-pole double-throw (SPDT) switch, a switch control chip, and first to sixth electronic switches. The first VGA interface is connected to the second and third VGA interfaces through the switch control chip and the electronic switches. The SPDT switch is used to control the first VGA interface to be selectively connected to the second or third VGA interface.