Abstract: A method of driving the electro-optical device includes selecting a plurality of scanning lines in a predetermined order in each of first and second fields of one frame; when one of the plurality of scanning lines is selected in the first field, for each pixel located on the selected scanning line, supplying one of a positive voltage and a negative voltage as the data signal to one of the plurality of data lines associated with the pixel, the positive voltage having a positive polarity corresponding to a voltage higher than a predetermined reference potential and the negative polarity corresponding to a voltage lower than the predetermined reference potential; and when the one of the plurality of scanning lines is selected in the second field, for each pixel located on the selected scanning line, supplying the other one of the positive voltage and the negative voltage as the data signal to one of the plurality of data lines associated with the pixel.

Abstract: A light emitting display for compensating for the threshold voltage of transistor or mobility and fully charging a data line. A transistor and first through third switches are formed on a pixel circuit of an organic EL display. The transistor supplies a driving current for emitting an organic EL element (OLED). The first switch diode-connects the transistor. A first storage unit stores a first voltage corresponding to a threshold voltage of the transistor. A second switch transmits a data current in response to a select signal. A second storage unit stores a second voltage corresponding to the data current. A third switch transmits the driving current to the OLED. A third voltage determined by coupling of the first and second storage units is applied to a transistor to supply the driving current to the OLED.

Abstract: A digital image display capable of controlling an image signal output to a display screen portion, particularly capable of precisely controlling the phase of the image signal, regardless of provision/nonprovision of a function of communicating with an image signal output device is obtained. This digital image display includes an analog-to-digital conversion portion converting a received analog image signal to a digital image signal, a display screen portion displaying the digital image signal converted by the analog-to-digital conversion portion and a control portion controlling a clock value, a phase value, a horizontal position and vertical position of the digital image signal, while the control portion is so formed as to decide the optimum phase value on the basis of pixel data on the boundary between an image region having no image and another image region having an image in the digital image signal when controlling the phase value of the digital image signal.

Abstract: A display device includes driving apparatus having first, second, third, and fourth gate drivers. The first and second gate drivers are connected to gate lines and are positioned on one side of the display device side by side. The third and fourth gate drivers are connected to gate lines and are positioned on the other side of the display device side by side. The first and third gate drivers apply the gate signal to the same gate line, and the second and fourth gate drivers apply the gate signal to the same gate line.

Abstract: The present invention provides a display device which is used in a miniaturized portable information device, wherein the display device requires a small mounting area for a driving circuit thus realizing free mounting of the driving circuit and also can perform driving thereof with a low-voltage power source such as a battery. In a display device which includes a display panel and a driving circuit on the same substrate, a booster circuit is formed on one side of a display panel together with the driving circuit and is formed by steps substantially equal to steps for pixel transistors. The booster circuit includes a circuit which compensates for the lowering of voltage of a switching element used in the booster circuit attributed to a threshold value of a switching element.

Abstract: A liquid crystal display and a method of driving the same are provided. The liquid crystal display includes a first source drive IC group outputting a first feedback lock signal in response to one of a power voltage input through a first lock signal input terminal and a lock signal from the timing controller, a second source drive IC group outputting a second feedback lock signal in response to one of the power voltage input through a second lock signal input terminal, the lock signal from the timing controller, and a lock signal transferred from the first source drive IC group, and a comparator that compares the first feedback lock signal with the second feedback lock signal and supplies a comparison result to the timing controller.

Abstract: A timing controller for an LCD panel includes a signal receiver, a data reader, a signal receiver, a logic control unit, and a data conversion unit. The signal receiver receives transmitted signals, and the data reader acquires data from the signal receiver. The logic control unit receives the data acquired by the data reader to generate pixel data, and the data conversion unit receives the pixel data and converts them into serial signals. The timing controller converts the pixel data and the control commands into serial signals, and then they are transmitted in serial to each of the source driver chips.

Abstract: A matrix array drive device according to the present invention includes: a horizontal scanning circuit controlling signal electrodes in a matrix array such that data signals corresponding to N rows of the matrix array are latched one row after another every horizontal scanning period of a predetermined length and a latch output for each row is continued to be produced for every horizontal scanning periods of N rows; and a vertical scanning circuit controlling scanning electrodes in the matrix array such that the matrix array is simultaneously driven N rows at a time and rows to be driven is shifted one row every horizontal scanning period.

Abstract: A display driver and display driving method process display data received from a central processing unit (CPU) and output display data voltages. The display driver includes a synchronization controller that sends a reference synchronization signal to the CPU, and controls the CPU to synchronize a write clock with the reference synchronization signal and to send the write clock. A write clock detector detects whether the write clock is received from the CPU and outputs a selection signal in response. A frame memory receives and stores display data of a current frame synchronized with the write clock. A gray-level compensator generates gray-level compensated display data based on the display data of a current frame and display data of a previous frame previously stored in the frame memory. A selector outputs one of the gray-level compensated display data or the display data previously stored in the frame memory as scan data in response to the selection signal.

Abstract: A source driving device, capable of reducing stand-by period and saving power consumption, includes a plurality of source drivers connected in series, which include one or more cascade source drivers. The one or more cascade source drivers include one or more first-type cascade source drivers, each of which, at different times to other first-type cascade source drivers, is respectively activated by a pulse signal generated by a previous source driver, and after the activation, is triggered by a frame signal to receive corresponding frame data in the frame signal. Each of the source drivers generates a pulse signal after receiving the corresponding frame data to activate the next source driver.

Abstract: A system, method, and computer program product are provided for adjusting at least one aspect of a programmable graphics and/or audio processor. In use, at least one input parameter and at least one output parameter of a programmable graphics and/or audio processor are identified. Thereafter, at least one aspect of the programmable graphics and/or audio processor may thus be dynamically adjusted. Such adjustment is performed as a function of both the at least one input parameter and the at least one output parameter.

Abstract: A plasma display panel driving method and a plasma display apparatus are disclosed in which a suitable address discharge can be performed at a next scanning timing by reducing voltage changes in a sustain electrode and a scan electrode caused by a change of an address pulse when the address pulse is applied to an address electrode at a scanning timing. The plasma display panel driving method drives a plasma display panel which includes plural scan electrodes extending in a first direction and plural address electrodes extending in a second direction orthogonal to the first direction. In the method, a negative polarity scan pulse is applied to a scan electrode, a positive polarity address pulse is applied to an address electrode from an address electrode driving circuit, and an address discharge is generated.

Abstract: Methods and apparatus for enhanced synchronization of a descrambler, such as used in a signal interface that carries scrambled data. In one embodiment, the descrambler self-synchronizes to a scrambled bit stream (rather than receiving an external “sync” trigger), thereby allowing for much more rapid synchronization. This is accomplished in one variant by identifying a scrambled symbol that has an expected value, predicting an internal scrambler seed based on the expected value, and verifying the predicted seed. For example, an invention-enabled device can synchronize to a DisplayPort stream during blanking intervals which are filled with known “dummy” bytes. Blanking intervals are much more frequent than explicit synchronization symbols, thus an invention enabled device can greatly improve synchronization times, and eliminate e.g., visual artifacts.

Abstract: The present invention provides a display apparatus, includes: a pixel array section; and a driving section; the pixel array section including a plurality of scanning lines extending along the direction of a row, a plurality of signal lines extending along the direction of a column, and a plurality of pixels disposed in rows and columns at places at which the scanning lines and the signal lines intersect with each other. The driving section including a write scanner and a signal selector.

Abstract: Disclosed herein is a display apparatus including: a pixel array section including pixel circuits laid out to form a matrix as pixel circuits each having an electro optical device, a signal writing transistor, a device driving transistor, and a storage capacitor; a power-supply scan circuit; a signal outputting circuit; and a write scan circuit.

Abstract: A timing controller and a Liquid Crystal Display (LCD) using the same are discussed. The timing controller according to an embodiment includes a reception unit which receives a video signal and a timing signal from a system; a control signal generation unit which generates a gate control signal and a data control signal with the timing signal, and outputs the gate control signal and the data control signal to a gate driver and a data driver, respectively; an image signal generation unit which realigns the video signal to output a realigned image signal; and a delay compensation unit which performs delay compensation for the realigned image signal with a circuit recombined according to a delay compensation value between each data drive Integrated Chip (IC) of the data driver and the image signal generation unit, and outputs the delay-compensated image signal to each data drive IC.

Abstract: A liquid crystal display and the driving method thereof. The LCD includes a timing controller, a plurality of driver chips and a display panel. The driver chips are cascaded together for driving the display panel to display frames. A driver chip includes a differential receiver, a single-ended receiver, a shift register, a differential transmitter, a single-ended transmitter and a pixel driver. The driver chip receives a pixel signal and drives the display panel according to the pixel signal, and outputs the pixel signal to the next driver chip.

Abstract: A system and method are provided for changing a display refresh rate. A first register is provided for storing at least one first refresh parameter in association with a first refresh rate. Additionally, a second register is provided for storing at least one second refresh parameter in association with a second refresh rate. Furthermore, logic is in communication with the first register and the second register. Such logic is adopted for selecting the first refresh parameter or the second refresh parameter, for the purpose of reducing artifacts resulting from a change from the first refresh rate and the second refresh rate.

Abstract: There is provided a pixel circuit, including: a signal line; a drive transistor; a light emitting element; and at least one power source line wired so as to intersect perpendicularly the signal line; wherein the drive transistor is connected between the wiring layer and a predetermined electrode of the light emitting element, and any one of wirings intersecting perpendicularly one another is wired in a region of overlapping a light emitting region of the light emitting element in a direction of lamination of layers.

Abstract: A multi-panel display device and a method of driving the same, which can simplify a driving circuit for driving multiple flat panel display devices, thereby decreasing the fabrication cost, are disclosed. In the device configured of an alignment of multiple flat panel display devices for representing a single image, the device comprises multiple flat panel display devices, wherein each flat panel display device includes a display panel configured of a plurality of pixel regions, a data driver driving a plurality of data lines provided in the display panel, and a timing controller receiving image data and synchronization signals from an external source so as to divide the received image data, converting a signal frequency of at least one of the synchronization signals, and converting a size of the divided image data in accordance with the frequency-converted synchronization signal, thereby providing the size-converted divided image data to the data driver.

Abstract: A driver for display provides a driving signal having a frequency synchronized with that of an image signal when the image signal is normal and provides a driving signal having a predetermined frequency when the image signal is abnormal, thereby performing a stable operation. The driver includes a frequency detection unit detecting a frequency difference between a frequency of an inputted image signal and a frequency of a frequency-divided driving signal, a driving signal generation unit generating the driving signal having a frequency synchronized with the frequency of the image signal according to a detection result of the frequency detection unit, and a control unit stopping a frequency detection operation of the frequency detection unit when the detection result of the frequency detection unit shows an abnormal operation.

Abstract: There is provided a liquid crystal display control device which can display pictures in a magnification mode by using only a memory having a low-speed access and a low storage capacity. When a video signal has intermediate resolution or less, the enlargement processing is performed by a frame memory, a line memory and an enlargement processing control circuit. If the input operation and the output operation to and from the frame memory are synchronized with each other, it is sufficient for the frame memory to have a storage capacity of two lines. When the video signal has the same high resolution as a liquid crystal display panel, the video signal is output through a gate circuit to a display timing generating circuit, and it is displayed in a through mode. In this case, no processing is performed by the frame memory or the like.

Abstract: A scanning backlight for a stereoscopic 3D liquid crystal display apparatus includes a light guide having a first side and a second side opposite the first side, and having a first surface extending between the first and second sides and a second surface opposite the first surface. The first surface substantially re-directs light and the second surface substantially transmits light. A plurality of first light sources are arranged along the first side of the light guide for transmitting light into the light guide from the first side and a plurality of second light sources are arranged along the second side of the light guide for transmitting light into the light guide from the second side.

Abstract: A liquid crystal panel includes a gate line, a data line, and a switching element connected to the gate line and the data line; a gate driver applying a gate signal; and a data driver selecting gray voltages and applying the selected gray voltages to the data line. The gate signal includes a gate-on voltage for turning on the switching element and a gate-off voltage for turning off the switching element. The gray voltages include voltages (V+, V?) and V + + V - 2 = Vconst for each gray. The gate-on voltage decreases from a first level to a second level, and the first level (Von1) and the second level (Von2) satisfy, Von ? ? 1 + Vconst 2 - Von ? ? 1 + Vconst 2 ? 10 ? % ? Von ? ? 2 ? Von ? ? 1 + Vconst 2 + Von ? ? 1 + Vconst 2 ? ? 10 ? % .

Abstract: In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

Abstract: In a plurality of source drivers, a unit start pulse inputted/outputted to/from the source drivers is cascaded between an ante-stage source driver and a post-stage source driver, a horizontal start pulse outputted from a timing controller is inputted to a first-stage source driver, and the duty ratio of a vertical clock is controlled by one of the plurality of cascaded unit start pulses. In a matrix display device, it is thereby possible to provide a timing controller having a simple circuit configuration which needs no counter circuit for generating a vertical clock to be outputted to a gate driver.

Abstract: A liquid crystal display (LCD) includes: a liquid crystal panel including a plurality of pixels; a data driver applying a data voltage to a plurality of data lines connected to the plurality of pixels; a scan driver applying a scan voltage to a plurality of scan lines connected to the plurality of pixels in synchronization with a scan clock signal controlling an output of the scan signal for the data voltage to be applied to the plurality of pixels; and a boost driver applying a primary boost voltage and a secondary boost voltage to a plurality of boost lines connected to the plurality of pixels in synchronization with a boost clock signal controlling the output of the boost voltage, wherein the boost clock signal has different synchronization from the scan clock signal controlling the output of the scan signal.

Abstract: A liquid crystal display is provided, which includes: a plurality of pixel row groups, each pixel row group including at least one pixel row that includes a plurality of pixels arranged in a matrix and including switching elements; a plurality of gate lines connected to the switching elements and transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements and transmitting data voltages, wherein the switching elements in adjacent pixel row groups are connected to the data lines at opposite sides.

Abstract: An apparatus and method of driving an LCD device is disclosed, which has a simplified structure by decreasing the number of signal transmission lines included in a shift register, the apparatus comprising a display panel to display images; a gate driver to drive gate lines of the display panel; a timing controller to control the gate driver by generating at least three clock pulses having the different phases from one another; and a start pulse generator to generate a start pulse using at least two clock pulses among at least three clock pulses, and to supply the generated start pulse to the gate driver.

Abstract: A method of using a customer pole display, point-of-sale pole display, point-of sale display, or pole display includes connecting a Universal Serial Bus, inputting a power signal from the Universal Serial Bus, translating the power signal to a display power signal, and connecting the display power signal to the display. A Universal Serial Bus-compatible interface adapted to provide power to a point-of-sale display includes a connector adapted to be coupled to a Universal Serial Bus and a converter operatively coupled to the connector and adapted to translate a power signal input from the Universal Serial Bus to a display power signal. A point-of-sale display assembly includes a display, a connector adapted to be coupled to a Universal Serial Bus, and a converter operatively coupled to the connector and adapted to translate a power signal input from the Universal Serial Bus to a display power signal.

Abstract: A method and apparatus for viewing and/or analyzing the operations and logical states of an integrated circuit. The logical state of various flip-flops within the ASIC may be determined at a specified time. The embodiment may store these flip-flop states in a computer-readable data structure, such as a file or database. By repeating this process and incrementing or decrementing the time with each repetition, a more complete picture of the ASIC's operation may be captured. Additionally, the embodiment may graphically display the flip-flop states, for example as a graph or waveform.

Abstract: A flat display and a method for modulating a clock signal for driving a flat display are provided. The flat display includes a clock generator and a clock modulator. The clock generator provides a clock signal that includes at least a first cycle waveform and a second cycle waveform following said first cycle waveform. The first cycle waveform is modulated by the clock modulator as a first modulated cycle waveform divided by a first positive modulated cycle waveform and a first negative modulated cycle waveform, and the second cycle waveform is modulated as a second modulated cycle waveform divided by a second positive modulated cycle waveform and a second negative modulated cycle waveform. The first positive modulated cycle waveform and the first negative modulated cycle waveform have a first duration difference, and the second positive modulated cycle waveform and the second negative modulated cycle waveform have a second duration difference different from the first duration difference.

Abstract: A system and method is provided for generating a video signal including a signal generator to generate the video signal, a user setting part to allow a user to set information for generating the video signal, and a controller to control the signal generator to generate the video signal on the basis of the information when the information is set through the user setting part. Thus, the system provides a controller for generating a video signal, a simulation system comprising the same, and a method of generating the video signal, in which a desired new video signal is generated or adjusted on the basis of information for generating the video signal input by a user.

Abstract: An integrated circuit device includes: a plurality of data line driving circuits that drive a plurality of data voltage supply lines; and a correction data calculation section that calculates correction data for correcting differences in data voltages outputted from the plurality of data line driving circuits, wherein the correction data calculation section executes, in one horizontal scanning period in a non-display period in a vertical scanning period, a first mode to obtain the correction data corresponding to a data line driving circuit to be corrected among the plurality of data line driving circuits.

Abstract: An apparatus for outputting an image by scaling an original image to a different size is disclosed. The apparatus includes an interpolator and at least one line buffer. The interpolator generates lines of the output image, at least one of which is derived by interpolation of lines of the original image, and the line buffer temporally stores pixels on a same one of the lines of the original image for the interpolation, in which the line buffer has single-port memories and each of the single-port memories is accessed for reading and writing values of the pixels which are non-adjacent to one another. A line buffer is also disclosed herein.

Abstract: A display image of a frame is input in time series. An inverse colored image to cancel the display image is generated. The display image is divided into a plurality of subfields, and the inverse colored image is also divided into a plurality of subfields. A time divisional image is generated by disposing a display time of a subfield of the inverse colored image before and after a display time of a corresponding subfield of the display image. While displaying the time divisional image on a screen, a light from the screen is transmitted in synchronization with display timing of the display image in a display time of the time divisional image, and the light is cut off in synchronization with display timing of the inverse colored image in the display time of the time divisional image.

Abstract: A display device according to the present invention includes a switching regulator control circuit formed of TFTs. A digital switching regulator control circuit is composed of an AD converter circuit, a CPU, a pulse generation circuit or the like. An analog switching regulator control circuit is composed of an error amplifier circuit, a triangle wave generation circuit, a PWM comparator or the like. By integrally forming the switching regulator control circuit on a display device, the problem of the conventional portable information equipment as to the reduction in size and weight can be solved.

Abstract: Techniques are described that can be used to adjust a refresh rate of a display device. For example, the refresh rate change can be triggered by a user application for a variety of circumstances such as a change in power source from AC to DC or display of 24 frames per second (fps) video. Contents of a primary buffer can be copied to a secondary buffer and a display engine can read video from the secondary buffer to provide video to a display. The clock rate of a clock used to read out pixels can be adjusted using software commands. Video is written to a third buffer and during a vertical blanking interval the display engine reads frames from the third buffer instead of the second buffer.

Abstract: A display device including a timing controller and a display panel is provided. The timing controller provides a clock signal and an inverted signal of the clock signal. The display panel includes a substrate, a pixel array and a plurality of shift registers. The pixel array is disposed on the substrate. The shift registers are disposed on the substrate and respectively coupled to the timing controller. The shift registers sequentially output a plurality of scanning signals to drive the pixel array according to the clock signal and the inverted signal. In a display period of a frame period, frequencies of the clock signal and the inverted signal are a first frequency. In a vertical blanking period of the frame period, frequencies of the clock signal and the inverted signal are a second frequency. The second frequency is smaller than the first frequency.

Abstract: A method for improving the EMI performance of an LCD device is disclosed, adapting for a point-to-point transistor transistor logic interface of the LCD device. The disclosed method comprises the following steps: receiving a plurality of image data based on a data CLK signal; providing a first CLK signal and a second CLK signal to a plurality of source drivers by a timing controller, wherein the frequencies of the first CLK signal and the second CLK signal are smaller than the frequency of the data CLK signal, the phase of the first CLK signal is different from the phase of the second CLK signal; and the timing controller transmitting a plurality of first image data to the plurality of source drivers based on the first CLK signal, and the timing controller transmitting a plurality of second image data to the plurality of source drivers based on the second CLK signal.

Abstract: A mobile terminal having a dual display unit and a method of changing a display screen using the same are disclosed. The mobile terminal includes a main body, a front display unit for providing a multimedia mode, a rear display unit for providing a normal mode, and a screen control module for controlling to turn off the rear display unit and turn on the front display unit, and to display a multimedia execution screen in the front display unit. The method of changing a display screen of the mobile terminal having additional multimedia functions provides an optimum multimedia environment and improves user convenience and effectiveness of the mobile terminal by flexibly supporting a multimedia function to be executed according to a screen state of the rear display unit.

Abstract: A digital driving system for a display includes a scan driver adapted to supply scan signals serially to scan lines of the display, a data driver adapted to supply a first data signal and a second data signal to data lines of the display, a timing controller adapted to control the scan driver and the data driver in accordance with a main clock, and to supply external data to the data driver, and a vertical synchronizing signal synchronizing circuit adapted to synchronize an internal vertical synchronizing signal and an external vertical synchronizing signal.

Abstract: The present invention provides a liquid crystal display controller device and method which provides for a full and/or partial display with good display quality and/or low power consumption based on the scanning period for an active scan line being dependent upon a number of reference clock pulses. Some embodiments of the present invention include one or more of the following features: keeping the frequency substantially constant for different numbers of active scan lines, allowing change of the frequency due to characteristics of the LCD, displaying gradation with near linear effective voltage characteristics, displaying graduation data with lower power, or displaying a partial or full screen in a mobile device, for example, a cell phone.

Abstract: A liquid crystal display device and a driving method thereof, which are capable of preventing generation of a residual image upon power-off, are disclosed. The liquid crystal display device includes a power supply unit for outputting a plurality of drive voltages after delaying the drive voltages, a voltage detector for monitoring one of the drive voltages, and outputting a power-off detect signal based on the result of the monitoring, a timing controller for increasing a frequency of a control signal in response to the power-off detect signal, and outputting the frequency-increased control signal, a gate driver for outputting a scan signal in response to the frequency-increased control signal, a data driver for outputting a constant voltage in response to another control signal from the timing controller, and a liquid crystal panel for applying the constant voltage to all sub-pixels of the liquid crystal panel in response to the scan signal.

Abstract: There is provided a method of driving an organic light emitting display capable of minimizing or reducing the amount of instantaneously current flowing in the display that is driven in a concurrent emission method. The method includes setting pixels included in j blocks of a panel in a non-emission state, charging the pixels with voltages corresponding to data signals, and emitting light by the pixels in units of horizontal lines respectively included in the j blocks to correspond to the charged voltages.

Abstract: A liquid crystal display device includes a timing controller, a liquid crystal display panel, multiple data drivers, and gate drivers. The timing controller supplies control data to specified drivers among the data drivers. The specified drivers generate gate driver control signals to control gate drivers in response to the control data, and supply gate driver control signals to the gate drivers.

Abstract: A level shifter includes at least one level shift unit for generating a corresponding clock-pulse output signal. The level shift unit receives a corresponding clock-pulse input signal. The clock-pulse output signal successively shares charges with respective auxiliary reference voltage sources to pull up a voltage level of the clock-pulse output signal from the second reference voltage to the first reference voltage. Alternatively, the clock-pulse output signal successively shares charges with respective auxiliary reference voltage sources to pull down the voltage level of the clock-pulse output signal from the first reference voltage to the second reference voltage.

Abstract: A mechanism for mitigating undesired color image breakup artifacts arising in display systems that exploit the principle of field sequential color generation. By suitably reducing the time interval during which image information strikes the moving retina, such that the differential position for the respective red, green, and blue components of the image falling upon the moving retina does not exceed the diameter of a retinal cone or rod, the cause of the breakup is negated and the image becomes unitary as expected: the eye sees the image as if all the components arrived at the same time. The truncation of light emission into shorter time frames necessitates a compensatory increase in imaging light intensity, such that the net amount of photonic flux striking the retina, averaged over time, remains unchanged. The mechanism can be applied to systems with discrete red, green, and blue sources as well as to color-wheel-based systems.

Abstract: A display structure of a slip-cover-hinge electronic device, which includes a housing, a display module, two track modules and a flexible-printed-circuit module, is disclosed. The housing has an accommodated cavity formed with a bottom wall, two parallel slots formed respectively at two opposite ends of the bottom wall, and a passageway formed between the two slots and on the bottom wall. The display module is connected within the cavity. Each track module has a track disposed on the opposite ends of the bottom wall and a skid slidably arranged onto the corresponding tracks for gliding in corresponding slots. The flexible-printed-circuit module has at least a flexible-printed-circuit member, which includes an electrical connection portion and a resilient portion flexibly extending from the electrical connection portion. The resilient portion extends out of the passageway of the housing, and the resilient portion is partially self-overlapped to be capable of stretching outwardly.

Abstract: A power-saving circuit for a digital video display device includes a TMDS driving unit converting a TMDS data signal and a TMDS clock signal, a display driving unit driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input from the TMDS driving unit, a clock signal detecting unit outputting a first or a second level of a clock detecting signal depending on the TMDS clock signal, a controller outputting a first-level of a power-saving signal when the first level clock detecting signal is input, and outputting a second level of power-saving signal when the second level clock detecting signal is input, and a power supply unit supplying a voltage to respective components, and cutting off the supply of the voltage to respective components depending on the level of the power-saving signal or the clock detecting signal.