Abstract: In a liquid crystal display (LCD) panel driver with a self-masking function using a power-on reset signal, and in a method of driving the same, the LCD panel driver includes a power-on reset signal generation unit that generates a power-on reset signal in response to a supply voltage applied to a LCD panel; a latch unit that receives a start pulse signal instructing that source lines of the LCD panel be driven and generates first and second set signals for setting an initial value of an output signal of a flip-flop to be in a predetermined default logic level, in response to the power-on reset signal; and a counter unit that generates a start pulse masking signal by masking at least one pulse of the start pulse signal in response to the first and second set signals and the start pulse signal.

Abstract: A gate signal adjustment circuit for a display is disclosed. The gate signal adjustment circuit can adjust a transition time of a gate signal used to drive data displaying. The adjustment can be to either speed up or slow down the transition time according to the requirements of the display. In an example, the gate signal adjustment circuit can include multiple transistors, where a first set of the transistors outputs the gate signal and a second set of the transistors outputs an adjustment to the gate signal. The second set of transistors can be the same or different sizes depending on the desirable number of adjustment options. The circuit can also include a control line coupled to the second set of transistors to control the adjustment output. Gate signal adjustment can reduce crosstalk in the display.

Abstract: A display panel drive apparatus includes a source driver that drives each unit dot in accordance with a time-divisional clock, and a booster circuit that generates a supply voltage to be supplied to the source driver based on a clock having a rising edge and a falling edge each coinciding with an off-period of the time-divisional clock. The display panel drive apparatus performs a time-divisional driving operation during one horizontal period.

Abstract: A pixel driving device for drive control of pixels, has a image data conversion circuit for generating an original gradation signal by converting an image data, based on a preset conversion property, a signal correction circuit for outputting a corrected gradation signal by adding a correction value acquired based on an electric property parameter of a pixel to the original gradation signal, and a drive signal impressing circuit for impressing a voltage signal corresponding to the corrected gradation signal on one end of a signal line. The original gradation signal has a value that corresponds to a gradation value of the image data and the maximum value of the original gradation signal is set to a value equal to or smaller than a value acquired by subtracting a value corresponding to the correction value from a maximum value in an input range of the drive signal impressing circuit.

Abstract: A display apparatus includes a first substrate, a second substrate, a liquid crystal layer, and a common electrode. The first substrate includes a gate line, a data line insulated from the gate line while crossing the gate line, and a pixel electrode connected to the gate line and the data line. The second substrate faces the first substrate. The liquid crystal layer is interposed between the first substrate and the second substrate. The common electrode is disposed on at least one of the first substrate or the second substrate to form an electric field in cooperation with the pixel electrode. A data voltage applied to the pixel electrode has a polarity inverted every at least one frame with reference to a predetermined reference voltage, and a common voltage applied to the common electrode has a polarity inverted every at least two frames with reference to the reference voltage.

Abstract: The backlight apparatus includes a light source module having a plurality of light sources connected in series, and a power supply module which generates a driving signal for driving the light source module according a synchronous control signal. A first switch is disposed between the light source module and power supply module, or between a last light source in the light source module and a reference voltage level. The first switch is turned on or off according to the synchronous control signal. In addition, a second switch determines whether or not to couple a function terminal of the power supply module to the reference voltage level to disable the driving signal without power off according to the synchronous control signal.

Abstract: A digital audio signal, a channel clock, and a bit clock are transmitted to the receiving apparatus via a pair of signal lines. The digital audio signal is input to a D/A converter via a first comparator. The channel clock and the bit clock are received, separated with first and second separation circuits, and input to the D/A converter via the second and third comparators. A reference electrical potential of the second comparator is corrected such that it becomes half or approximately half of an amplitude of the channel clock depending on an electrical potential change of the output of a second differential signal receiving circuit. A system clock is generated based on the bit clock. The digital audio signal is converted into the analog audio signal based on the channel clock, the bit clock, and the system clock, and then the converted analog audio signal is output.

Abstract: The display device may include a data aligning part that analyzes a gray level of input data and inserts black data into frame data having less than a designated reference gray level; and a driver that displays the data from the data aligning part in a display panel.

Abstract: In a liquid crystal display device performing alternating-current driving, at least one of a gate voltage amplitude Vgp?p(p) upon application of a positive polarity voltage and a gate voltage amplitude Vgp?p(n) upon application of a negative polarity voltage is changed in accordance with a liquid crystal driving frequency. Thus, an effective value of a liquid crystal application voltage in a positive polarity is set to be equal to an effective value of a liquid crystal application voltage in a negative polarity irrespective of the liquid crystal driving frequency, so that flicker is prevented from occurring when the liquid crystal driving frequency is switched. As the liquid crystal driving frequency is low, a gate low voltage Vgln after application of the negative polarity voltage is set to be low. Thus, a leak current from a TFT is reduced in the negative polarity, and a liquid crystal element is improved in voltage holding ratio.

Abstract: A light emitting display for compensating for the threshold voltage of transistor or mobility and fully charging a data line. A transistor and first through third switches are formed on a pixel circuit of an organic EL display. The transistor supplies a driving current for emitting an organic EL element (OLED). The first switch diode-connects the transistor. A first storage unit stores a first voltage corresponding to a threshold voltage of the transistor. A second switch transmits a data current in response to a select signal. A second storage unit stores a second voltage corresponding to the data current. A third switch transmits the driving current to the OLED. A third voltage determined by coupling of the first and second storage units is applied to a transistor to supply the driving current to the OLED.

Abstract: A disclosed display includes a display panel including a first group of data lines and second group of data lines, a plurality of gate lines crossing the first and a second groups of data lines, and a plurality of picture cells arranged in a matrix. The display also includes a first source PCB coupled to first data integrated circuits (ICs) to supply first data voltages to the first group of data lines and a second source PCB coupled to second data ICs to supply second data voltages to the second group of data lines. The display further includes a timing controller having a single output port with a plurality of output pins which are configured to output video data to both the first and second data ICs, and to output a timing control signal to control both the first and second data ICs.

Abstract: A display device includes a display portion; a signal driver; and a delay control circuit. The display portion is connected to a plurality of signal line groups. The signal driver is connected to the plurality of signal line groups and outputs a plurality of video data groups to the plurality of signal line groups at timings respectively in a single horizontal period. Each of the timings is shifted from an adjacent timing by a predetermined time. The delay control circuit varies the predetermined time every horizontal period and supplies the predetermined time to the signal driver.

Abstract: The invention provides a display device with reduced power consumption, comprising a host applied to generate a first image signal, a timing controller connected to the host, applied to generate a second image signal and comprised a memory for storing image data, and a panel connected to the timing controller and applied to receive the second image signal for displaying image frames. When the display device is in a power-saving mode, the host is powered down, and the timing controller generates the second image signal according to the image data stored in the memory and outputs the second image signal to the panel.

Abstract: An output buffering circuit of a driver device for a display includes a first amplifier circuit having a first input stage, coupled between an upper power supply and a lower power supply, and a first output stage, coupled between the upper power supply and a first intermediate power supply that is greater than the lower power supply, and a second amplifier circuit having a second input stage coupled between the upper power supply and the lower power supply, and a second output stage coupled between a second intermediate power supply that is lower than the upper power supply and the lower power supply.

Abstract: A display device includes a plurality of pixels arranged in matrix, a plurality of gate lines, a plurality of data lines, and a gate driver connected to the plurality of gate lines. The gate driver receives a first scan start signal, a second scan start signal and clock signals and outputs a gate-on voltage to each of the plurality of gate lines. The gate driver outputs the gate-on voltage to the plurality of gate lines such that the gate-on voltages do not overlap with each other when the gate driver receives the first scan start signal. The gate driver outputs the gate-on voltage to at least two of the gate lines at substantially the same time when the gate driver receives the second scan start signal.

Abstract: An apparatus and method for data interface of a flat panel display device, which is capable of transferring clocks in a state, in which the clocks are embedded in digital data, thereby reducing the number of transfer lines, is disclosed. The apparatus includes a transmitter unit built in a timing controller, to transmit transfer data with an embedding clock embedded between successive pieces of data, and a clock enable signal to indicate the embedding clock, and receiver units respectively built in a plurality of data integrated circuits connected to the timing controller, to separate and detect the embedding clock and the data from the transfer data, in response to the clock enable signal.

Abstract: A display apparatus includes a timing controller, a column driver, a row driver and a display unit. The timing controller outputs a first column clock embedded into image data during an active period, and outputs a second column clock embedded into blank data during a blank period. The column driver detects the first column clock and the image data and converts the image data into a first analog signal using the first column clock, and detects the second column clock and the blank data and converts the blank data into a second analog signal using the second column clock. The first column clock has a voltage level greater than a voltage level of the image data. The second column clock is embedded into the blank data and has a voltage level substantially the same as the voltage level of the image data.

Abstract: A light emitting device has a plurality of pixels, each of which includes a drive transistor, a light emitting element and signal lines, a property parameter acquisition circuit which acquires property parameter, a signal correction circuit that generates a corrected gradation signal by correcting the image data based on the property parameter, and a drive signal impressing circuit that impresses a drive signal, generated based on the corrected gradation signal, on the pixel to drive it. The property parameter is constituted of a threshold voltage, a current amplification factor and its irregularity of the drive transistor, and is acquired based on measured voltages of the signal lines after each of a plurality of predetermined settling times elapses from the time when the light emitting device cuts off a voltage subsequent to impressing the voltage on each pixel for a predetermined length of time.

Abstract: An electronic device comprises a central processing unit, a graphics processing unit, and a power control unit comprising logic to develop a predictive model of power states for a central processing unit in the electronic device, and use the predictive model to synchronize activity of a graphics processing unit in the electronic device with periods of activity in the central processing unit. Other embodiments may be described.

Abstract: A display panel drive device for applying a drive pulse to data lines of a display panel according to a video signal includes a latch portion and an output amplifier. The latch portion includes a first latch section, a delay circuit, and a second latch section. The first latch section is provided for capturing the pixel data pieces or retaining the pixel data pieces. The delay circuit is provided for generating a delayed load clock signal. The second latch section is provided for capturing the pixel data pieces or retaining the pixel data pieces. The delayed load clock signal is transited to the first level state after a first delay time, and the delayed load clock signal is transited to the second level state after a second delay time shorter than the first delay time.

Abstract: An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.

Abstract: A flat panel display includes first and second signal drivers which drive a first and second group signal lines of a display panel in accordance with an input first and second group video data respectively. A controller controls a timing of sending the first group video data to the first signal driver via the first data line, and a timing of sending the second group video data to the second signal driver via the second data line. A delay time generating section shifts a relative timing between a timing at which the first signal driver receives the first group video data and a timing at which the second signal driver receives the second video data by a determined time. The problem of the deterioration of the EMI caused by synchronization of the peak currents respectively generated in signal drivers for driving a flat panel display can be suppressed.

Abstract: A video switch for allowing at least two users to view video data from respective ones of at least two video sources. The video switch comprises a switch for selecting one of the at least two video sources and at least one sampler connected to the switch. The sampler is for sampling video data from the at least two video sources. The video switch further comprises a controller for controlling the switch and sampler to select one of the at least two video sources and sample a frame of video data. An output is provided for transmitting video data to one of the at least two users. The output supports a maximum number of simultaneous users which is at least two, and the number of samplers in the video switch is less than the maximum number of simultaneous users. A video switch according to the present invention allows a sampler for capturing video data to be shared between at least two simultaneous users. This reduces the cost, size and complexity of the hardware required to implement a video switch.

Abstract: A driving device of a light emitting unit is provided. The driving device includes a driving circuit, a switch, a capacitor, and a compensation circuit. The driving circuit has a control terminal and a driving terminal connected to the light emitting unit. The driving circuit determines a driving current according to the voltage on the control terminal. The switch has a first end for receiving a data voltage, a second end connected to the light emitting unit, and a control end for receiving a scan voltage. The capacitor has a first end connected to the control terminal of the driving circuit and a second end connected to the second end of the switch. The compensation circuit has an output terminal connected to the first end of the capacitor. The compensation circuit supplies a reset voltage to the first end of the capacitor when the switch is turned on.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.

Abstract: A pixel driving device has a voltage impressing circuit that outputs a reference voltage that exceeds a threshold voltage of a drive transistor, a voltage measurement circuit, and a property parameter acquisition circuit that acquires a property parameter related to an electronic property of a pixel. The pixel driving device impresses the reference voltage on the pixel that has a light emitting element and the drive transistor. The voltage measurement circuit acquires voltage of a signal line, as measured voltages, after each of a plurality of the settling times elapsing from the time when the reference voltage is cut. The property parameter acquisition circuit acquires, as property parameters, the threshold voltage and a current amplification factor of drive transistor based on values of a plurality of measured voltages acquired by the voltage measurement circuit.

Abstract: In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a shift register which performs discharge of a node and pull-down of an output signal and achieves a small area and low power consumption without using an output signal from a subsequent circuit.

Abstract: A liquid crystal display panel (LCD) including a plurality of pixels. A plurality of drivers are provided and switched between a driving state and a non-driving state in response to an ON/OFF signal that is fed. The plurality of drivers drive the plurality of pixels of the liquid crystal display panel on the basis of a display data signal and a synchronizing signal, including a vertical synchronizing signal VSYNC, so that an image responsive to the display data signal is shown on the liquid crystal display panel. A signal generating section is provided to generate, on the basis of the vertical synchronizing signal VSYNC and the ON/OFF signal that is fed, a new ON/OFF signal synchronized with the vertical synchronizing signal VSYNC, and feeds the new ON/OFF signal into the drivers.

Abstract: A display device includes a plurality of pixel each including a transistor, a pixel electrode connected to the transistor, and a reference electrode disposed so as to be opposite to the pixel electrode. The display device also includes data lines connected to the corresponding pixel circuits, a plurality of gate lines connected to the corresponding pixel circuits, gate circuits each of which sequentially outputs a gate signal, which is in a high voltage level during two or more horizontal periods in a first order or in a second order that is reverse to the first order, and a gate signal control circuit that controls each of the gate circuits and scans the gate lines. The gate signal control circuit controls each of the gate circuits to start to output the gate signals so as not to overlap periods when the gate signals are output to the adjacent gate lines.

Abstract: A drive circuit for rapidly interleaving image data displayed on an EL device is disclosed. The drive circuit includes a signal source that provides a image data signals. Each image data signal is provided for a specified load period. A multiplexer receives the image data signals, and in response to a selection signal selects one of the image data signals to provide a control signal that directs the EL device to emit light. Additionally, a controller causes interleaving of the image data during multiple display periods; each display period is shorter than the load period.

Abstract: An image recording apparatus includes an imaging section which images a subject to obtain imaging data. An image quality information acquiring section acquires a plurality of sets of information concerning image quality. An image quality information converting section converts the plurality of sets of information concerning the image quality acquired in the image quality information acquiring section into image processing parameters used in image processing of the imaging data. An image processing section performs image processing with respect to the imaging data based on the image processing parameters converted by the image quality information converting section. A recording section records in a recording medium the imaging data subjected to image processing in the image processing section, or records in the recording medium the imaging data which is not yet subjected to image processing in the image processing section and the plurality of sets of information concerning the image quality.

Abstract: Representative embodiments of the disclosure provide a system, apparatus, and method of controlling an intensity and spectrum of light emitted from a solid state lighting system. The solid state lighting system has a first emitted spectrum at full intensity and at a selected temperature, with a first electrical biasing for the solid state lighting system producing a first wavelength shift, and a second electrical biasing for the solid state lighting system producing a second, opposing wavelength shift. Representative embodiments provide for receiving information designating a selected intensity level or a selected temperature and providing a combined first electrical biasing and second electrical biasing to the solid state lighting system to generate emitted light having the selected intensity level and having a second emitted spectrum within a predetermined variance of the first emitted spectrum over a predetermined range of temperatures.

Abstract: One frame period of image data is divided into a plurality of subframes and driven. A first subframe included in one frame and a second subframe following the first subframe are output at opposite polarities. The image data is output while switching a phase mode between a first mode of driving the first subframe at positive polarity and the second subframe at negative polarity and a second mode of driving the first subframe at negative polarity and the second subframe at positive polarity.

Abstract: A system and method for determining high frequency content in an analog image source. A method comprises creating a histogram of the image, and selecting a portion of the image based on the histogram. The histogram comprises a first number of horizontal bins and a second number of vertical bins, with each bin having an associated counter for maintaining a count of pixel differences of pixels in a portion of the image corresponding to the bin that exceed a threshold. The portion of the image selected corresponds to a portion of the histogram having a high pixel difference count relative to other portions of the histogram.

Abstract: An active matrix emissive display (ED) is disclosed that also includes optical scanning capability. Each display pixel is independently addressable and independently internally driven for light generation. Each display pixel is also given the ability to be coupled to detection circuitry in order to sense currents or voltages that are optically generated or leaked by its internal LED when exposed to light (and thus acting in a photodiode capacity). Since the intensity of the light illuminating the diode determines the magnitude of generated currents and/or voltages or leakage current through the diode (when reverse biased), these sensed currents or voltages give an indication of the intensity of the light striking the pixel. In this manner, active matrix ED pixels are configured to serve the dual purpose of being able to generate and detect light.

Abstract: A display apparatus includes a substrate, gate lines disposed on the substrate, data lines extending across the gate lines, and pixels connected to the gate lines and the data lines. The pixels arranged in a matrix of rows and columns. The pixels disposed in the same columns are alternately connected to data lines disposed to the left or right sides of the column. The pixels may be disposed in different display areas of the substrate. Adjacent pixels in the same columns but in different display areas may be connected to the same data line.

Abstract: Detection voltages of self light emitting elements in a self-luminous display panel are detected by a detection circuit through a selection switch in a data line drive circuit via pixel detection switches and interactive signal lines. The detection operation is performed by making use of a power source supply time and a retracing period.

Abstract: An organic electroluminescent display and driving method thereof. The organic electroluminescent display includes a demultiplexer for outputting signals provided by a data driver to a plurality of data lines according to on/off operation of analog switches. The driving method divides a frame into two parts, and drives them. Data signals are applied to pixels which are not adjacent among the pixels of each row during the former ½ frame, and the data signals are applied to the pixels to which no data signal has been applied in the former ½ frame during the latter ½ frame.

Abstract: A signal transmission system includes a transmitting device and a receiving device. The transmitting device includes a superimposition portion that superimposes at least one synchronizing signal on at least one video signal among a plurality of video signals, and outputs the synchronizing signal and the video signal as a superimposition signal to a receiving device. The receiving device includes a separation portion that separates the superimposition signal into the synchronizing signal and the video signal, a first adjustment portion that adjusts an amount of delay of the separated video signal to another video signal, and a second adjustment portion that adjusts an amount of delay of the separated synchronizing signal.

Abstract: A gate driving circuit includes a plurality of stages connected to each other. An m-th stage (‘m’ is a natural number) of the stages includes a pull-up part, a pull-down part, a first holding part and a second holding part. The pull-up part outputs a high voltage of a clock signal as a high voltage of an m-th gate signal in response to a high voltage applied to a first output control part. The pull-down part pulls down the high voltage of the m-th gate signal to a first low voltage in response to a high voltage of an (m+1)-th gate signal. The first holding part holds a voltage applied to the first output control part as a second low voltage having a level lower than the first low voltage. The second holding part holds a low voltage of the m-th gate signal to the first low voltage.

Abstract: Write in of lower significant bits of a digital video signal to a memory is eliminated by a memory controller of a signal control circuit in a display device during a second display mode in which the number of gray scales is reduced, as compared to a first display mode. Further, read out of the lower significant bits of the digital video signal from the memory is also eliminated. The amount of information of digital image signals input to a source signal line driver circuit is reduced. Corresponding to this operation, a display controller functions to make start pulses and clock pulses input to each driver circuit have a lower frequency, and write in periods and display periods of sub-frame periods participating in display are set longer.

Abstract: In a first display period of a display device, a first count value is recorded at the rising edge of the data enable signal for controlling the length of a horizontal line. Next, a second count value is recorded at the falling edge of the data enable signal for identifying the time when the data enable signal switches from a high level to a low level. When entering a porch period following the first display period, the counter is cleared when the count value reaches the first count value. In a second display period following the porch period, the counter is cleared at the rising edge of the data enable signal, and the first count value is used for controlling the length of the horizontal line.

Abstract: A liquid crystal display includes a first gate line, a second gate line, a data line, a first pixel unit, a second pixel unit, a gate driver, and a source driver. The first and second gate lines respectively transmit a first and a second gate driving signals provided by the gate driver, while the data line transmits a first and a second data. The first pixel unit displays images according to the first gate driving signal and the first data, while the second pixel unit displays images according to the second gate driving signal and the second data. The source driver includes a logic circuit and a multiplexer circuit. The logic circuit generates an odd/even select signal according to a scan sequence signal and an enable signal. The multiplexer circuit outputs one of the first and second data according to the odd/even select signal.

Abstract: A pulse width modulation (PWM) signal generator generates multiple output PWM signals from an input PWM signal. The output PWM signals are synchronized to synchronization events. Each output PWM signal has a duty ratio substantially equal to the duty ratio of the input PWM signal, and each output PWM signal has a fixed phase-shift in relation to the other output PWM signals. The PWM signal generator samples an input PWM cycle to determine sample parameters representative of its duty ratio. The sample parameters are then used to generate a corresponding output PWM cycle for each of the output PWM signals. In response to a synchronization event, the PWM signal generator prematurely terminates the current PWM cycle and initiates the next PWM cycle while ensuring that the portion of the current output PWM cycle completed by the leading output PWM signal up to the point of the premature termination is replicated for the corresponding output PWM cycles of the other non-leading output PWM signals.

Abstract: The present invention provides a panel, including: a plurality of pixel circuits disposed in rows and columns and each including a light emitting element for emitting light in response to driving current, a sampling transistor for sampling an image signal, a driving transistor for supplying the driving current to the light emitting element, and a storage capacitor for storing a predetermined potential; a power supplying section configured to supply a predetermined power supply voltage to the pixel circuits disposed in rows and columns; and a power supply line for connecting all of the pixel circuits disposed in rows and columns and the power supply section to each other.

Abstract: An apparatus and method for data interface of a flat panel display device, which is capable of transferring clocks in a state, in which the clocks are embedded in digital data, thereby reducing the number of transfer lines, is disclosed. The apparatus includes a transmitter unit built in a timing controller, to transmit transfer data with an embedding clock embedded between successive pieces of data, and a clock enable signal to indicate the embedding clock, and receiver units respectively built in a plurality of data integrated circuits connected to the timing controller, to separate and detect the embedding clock and the data from the transfer data, in response to the clock enable signal.

Abstract: Disclosed herein are a light emitting display which can compensate for a threshold voltage of a driving switching element, and a method for driving the same. A light emitting display includes a pixel circuit that outputs a driving current corresponding to a data voltage from a data line using a scan signal, a first driving voltage and a second driving voltage; and a light emitting element that emits light by the driving current from the pixel circuit.

Abstract: There is provided a signal processing apparatus including a first image generating unit, a second image generating unit, a first selecting unit selects at least one of the first image generating unit and the second image generating unit and outputs an image, an image signal processing unit that performs signal processing on the image and outputs the processed image, a second selecting unit that selects one of the first selecting unit and the image signal processing unit and outputs an image, a storing unit that stores information on operations of the second image generating unit and the image signal processing unit, and a third selecting unit that selects at least one of the second image generating unit and the image signal processing unit and connects the selected one to the storing unit, whereby the storing unit is shared between the second image generating unit and the image signal processing unit.

Abstract: A display panel drive apparatus which can keep display brightness constant, thus preventing the occurrence of unevenness in brightness. The drive apparatus includes a current controlling voltage generating circuit to generate a current control voltage. The drive apparatus also includes a plurality of output drivers to supply brightness pulses whose amplitude is decided based on the current control voltage respectively onto data lines of a display panel in synchronization with a clock signal. The drive apparatus also includes a clock generating circuit to generate a pulse signal of a pulse period based on the current control voltage as the clock signal.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.