Plural Graphics Processors Patents (Class 345/502)
  • Patent number: 9377925
    Abstract: A computer is operated by displaying a window on a display device, where the window is an opaque window overlaid on the entirety of a system desktop that includes graphical representations of system controls and application controls. The window displays user interface elements of an application program executing on the computer, and also includes a portal region displaying an image of the system desktop including counterparts of the system controls and application controls. The computer provides user-controlled operation of the system controls and application controls based on simulated user interaction with the counterparts of the system controls and application controls in the portal region. The application program can effectively coordinate the use of the display by itself and by the system and other applications using the system desktop, relieving the user of this task.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: June 28, 2016
    Assignee: Citrix Systems, Inc.
    Inventors: Matthew Anderson, Brian Green, Albert Alexandrov
  • Patent number: 9348602
    Abstract: A method and apparatus for staged execution pipelining and allocating resource to staged execution pipelines are provided. One or more execution pipelines are established, where each of the one or more execution pipelines includes one or more execution stages. Data is provided to the one or more execution pipelines for processing and resources are allocated to the execution pipeline.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 24, 2016
    Assignee: Amazon Technologies, Inc.
    Inventors: Nishanth Alapati, Pradeep Vincent, David Carl Salyers
  • Patent number: 9327199
    Abstract: Some implementations may include one or more servers to host multiple game instances of game modules. The one or more servers may determine whether a difference between a total rendering time to render output data for the multiple game instances and a rendering capacity of the one or more processors is less than a predetermined rendering threshold. In response to determining that the difference between the total rendering time and the rendering capacity of the one or more processors is less than the predetermined rendering threshold, the one or more servers may adjust a rendering complexity associated with one or more of the plurality of game instances.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: May 3, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Chiyuan Chu, Alastair Wolman, Roger Wattenhofer, Sergey Grizan
  • Patent number: 9324174
    Abstract: Circuits, methods, and apparatus that provide multiple graphics processor systems where specific graphics processors can be instructed to not perform certain rendering operations while continuing to receive state updates, where the state updates are included in the rendering commands for these rendering operations. One embodiment provides commands instructing a graphics processor to start or stop rendering geometries. These commands can be directed to one or more specific processors by use of a set-subsystem device mask.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: April 26, 2016
    Assignee: NVIDIA Corporation
    Inventor: Franck R. Diard
  • Patent number: 9324294
    Abstract: The present invention sets forth an apparatus for supporting multiple digital display interface standards. In one embodiment, the apparatus includes a graphics processing unit (GPU) configured to determine a display device type of a display device that is in connection with a digital display interconnect, receive a display device information associated with the display device, and output a first data signal to the display device. The display device is of display port (DP) digital display interface standard and the digital display interconnect is of digital visual interface (DVI) digital display interface standard. The apparatus further includes a removable adaptor circuitry between the display device and the digital display interconnect.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: April 26, 2016
    Assignee: NVIDIA Corporation
    Inventors: Yao-Nan Lin, Hsin-Yu Cheng
  • Patent number: 9323653
    Abstract: An apparatus and method for processing data capable of providing an application with data converted based on various data types is provided. The data processing apparatus converts data, which is input from an input system, into various types of data. Various applications receive and use the data that is converted in the data processing apparatus.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 26, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Lee, Yoon-Soo Kim
  • Patent number: 9319719
    Abstract: A method for processing video and/or audio signals utilizing a processing component which is communicatively connected with a source component having a compression stage for compressing video and/or audio signals is suggested. The method comprises the steps of receiving uncompressed video and/or audio signals as source signals at the source component from one or a plurality of sources; compressing the video and/or audio signals with a selectable compression factor; transmitting the compressed video and/or audio signals to the processing component; processing the compressed video/audio signals in the processing component to produce at least one production output signal. In addition to that a system for processing video and/or audio signals is proposed. The system comprises a source component, a routing component and a processing component. The source component transmits all received source signals through the routing component to the processing component.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: April 19, 2016
    Inventor: Alfred Krug
  • Patent number: 9311152
    Abstract: Exemplary embodiments of methods and apparatuses to dynamically redistribute computational processes in a system that includes a plurality of processing units are described. The power consumption, the performance, and the power/performance value are determined for various computational processes between a plurality of subsystems where each of the subsystems is capable of performing the computational processes. The computational processes are exemplarily graphics rendering process, image processing process, signal processing process, Bayer decoding process, or video decoding process, which can be performed by a central processing unit, a graphics processing units or a digital signal processing unit. In one embodiment, the distribution of computational processes between capable subsystems is based on a power setting, a performance setting, a dynamic setting or a value setting.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 12, 2016
    Assignee: Apple Inc.
    Inventors: Howard Miller, Ralph Brunner
  • Patent number: 9305374
    Abstract: An electronic device with a display displays a user interface on the display. The device determines a first set of content-display values for one or more content-display properties of first content that corresponds to a respective region of the display. The device determines a first set of control-appearance values for one or more control-appearance parameters based on the first set of content-display values. The device displays a control in the respective region of the display, where an appearance of the control is determined based on the first content and the first set of control-appearance values, and displaying the control includes applying a blur operation to the first content to generate first blurred content and overlaying a translucent colored layer over the first blurred content.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: April 5, 2016
    Assignee: APPLE INC.
    Inventors: Kenneth L. Kocienda, Tiffany S. Jon, Chanaka G. Karunamuni
  • Patent number: 9269331
    Abstract: The present invention is directed to providing, in a plurality of information processing apparatuses which transmits and receives objects, a technique for causing the display contents in the apparatuses to be related by the apparatuses performing simple exchange of information. An information processing apparatus includes a display control unit configured to cause, based on the information on the azimuth direction in which an object displayed on a screen has been moved, from other apparatus that transmits the information and the information indicating the azimuth direction in which the screen of the information processing apparatus has been directed, an object which is the same as an object displayed on a screen of the other apparatus to appear from an azimuth direction opposite of the azimuth direction in which the object displayed on the screen of the other apparatus has been moved, in the screen of the information processing apparatus.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 23, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masayuki Ishizawa
  • Patent number: 9251552
    Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 2, 2016
    Assignee: INTEL CORPORATION
    Inventors: Seh Kwa, Nir Sucher, Vijay Sai Reddy Degalahal
  • Patent number: 9224358
    Abstract: A process is utilized to provide a multi-display configuration. The process detects, at a first proximity-based device within a first display device, a presence of a second proximity-based device within a second display device. The presence is within a proximity. Further, the process displays a first portion of a multi-display image at the first display device based upon a location of the first display device relative to the second display device.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 29, 2015
    Assignee: Disney Enterprises, Inc.
    Inventors: Edward Drake, Mark Arana, Evan Acosta
  • Patent number: 9218787
    Abstract: An image-displaying device includes a storage section, an image data generation section, a timing information acquisition section, and a display control section. The image data generation section is configured to generate image data indicative of an image of a subject and output to the storage section the image data including an Nth image data and an (N+i)th image data. The timing information acquisition section is configured to acquire timing information indicative of a timing related to generation of the image data and a timing at which output of each of the Nth image data and the (N+i)th image data to the storage section is completed. The display control section is configured to control a display section to commence reading and displaying the Nth image data in accordance with acquisition of the timing information indicating that the output of the (N+i)th image data to the storage section is completed.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: December 22, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Ryuichi Shiohara, Masahiro Kitano, Toshiyuki Yamamoto
  • Patent number: 9201579
    Abstract: According to various exemplary embodiments, user input of a single continuous gesture from a touch-sensitive surface of a first device to a touch-sensitive surface of a second device is detected. It is determined that the gesture corresponds to a drag-and-drop operation performed on an icon displayed on the touch-sensitive surface of the first device, the icon representing user profile information. Moreover, it is determined that the gesture terminates proximate to a job position user interface element in a job recruitment user interface window displayed on the touch-sensitive surface of the second device. Thereafter, the user profile information of the user is transferred from the first device to the second device.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: December 1, 2015
    Assignee: LinkedIn Corporation
    Inventors: Yevgeniy Jim Brikman, Bowei Gai, Matthew David Shoup
  • Patent number: 9202303
    Abstract: One embodiment of the present invention sets forth a technique for compositing a rendered path object into an image buffer. A shader program executing within a graphics processing unit (GPU) performs a stenciling operation for the path object and subsequently performs a texture barrier operation, which invalidates caches configured to store texture and frame buffer data within the GPU. The shader program then performs covering operation for the path object in which the shader renders color samples for the path object and composites the color samples into an image buffer. The shader program binds to the image buffer for access as both a texture map and a writeable image. Stencil values are reset when corresponding pixels are written once per path object, and texture caches are invalidated via the texture barrier operation, which is performed after each covering operation per path object.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 1, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • Patent number: 9189448
    Abstract: A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to a reference space, e.g., the physical space that is represented by the image data, to generate the data samples and each data sample may be tagged with a corresponding reference space coordinate value and routed through the network to one or more of the processors according to the tag.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: November 17, 2015
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventors: Andrew Wolfe, Tom Conte
  • Patent number: 9191221
    Abstract: The invention relates to a technique for protecting a point-to-multipoint primary tree in a connected mode communications network set up from a primary root node to leaf nodes in the event of a fault affecting the primary root node by means of a back-up tree between a back-up root node and at least one merge node, said at least one merge node belonging to a branch of the primary tree coming from the primary root node. A merge node executes the following steps: a step of receiving a request to set up the back-up tree sent by the back-up root node including an identifier of the protected primary root node; and a step of configuring a routing rule in a table, the aim of said rule being to route packets coming from the back-up tree to branches of the primary tree coming from said merge node, said routing rule being activated only in the event of a fault affecting the primary root node.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: November 17, 2015
    Assignee: Orange
    Inventors: Jean-Louis Le Roux, Mohamad Chaitou
  • Patent number: 9183610
    Abstract: The invention provides a method for driving a graphic processing unit (GPU), where a driver applies two threads to drive one ore more GPUs. The method includes the steps of: (a) activating a rendering thread and a displaying thread in response to invoking by an application thread of a graphics application; (b) sending according to the rendering thread a plurality of rendering instructions for enabling generation of at least a first rendered frame and a second rendered frame; and (c) sending according to the displaying thread one or more interpolating instructions and one or more displaying instructions, the one or more interpolating instructions enabling execution of interpolation according to the at least a first rendered frame and the second rendered frame to create one or more interpolated frames, and the one or more displaying instructions enabling display of the one or more interpolated frames.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: November 10, 2015
    Assignee: NVIDIA Corporation
    Inventor: Scott Saulters
  • Patent number: 9178747
    Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: November 3, 2015
    Assignee: NVIDIA Corporation
    Inventors: Rolf VandaVaart, Timothy James Murray, Peter Michael Buckingham
  • Patent number: 9172932
    Abstract: An image projection system includes a scaler IC, a micro-projector, a video connector, and a controller. The video connector is coupled to the scaler IC and the micro-projector. The controller controls the video connector and the scaler IC to form a first signal path mode and a second signal path mode. The video connector transmits a first image signal from the scaler IC for external displaying in the first signal path mode. The video connector receives a second image signal from a peripheral device and passes the second image signal to the micro-projector for projection in the second signal path mode.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: October 27, 2015
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventor: Chi-Hung Lin
  • Patent number: 9137050
    Abstract: A system and approach for utilizing a graphical processing unit in a demand response program. A demand response server may have numerous demand response resources connected to it. The server may have a main processor and an associated memory, and a graphic processing unit connected to the main processor and memory. The graphic processing unit may have numerous cores which incorporate processing units and associated memories. The cores may concurrently process demand response information and rules of the numerous resources, respectively, and provide signal values to the main processor. The main processor may the provide demand response signals based at least partially on the signal values, to each of the respective demand response resources.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 15, 2015
    Assignee: Honeywell International Inc.
    Inventor: Edward Koch
  • Patent number: 9135189
    Abstract: Described herein is providing GPU resources across machine boundaries. Data centers tend to have racks of servers that have limited access to GPUs. Accordingly, disclosed herein is providing GPU resources to computing devices that have limited access to GPUs across machine boundaries.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: September 15, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Parag Chakraborty, Bradley Stephen Post, Vladimir Pavlov, B. Anil Kumar
  • Patent number: 9117392
    Abstract: A method includes providing an Input/Output (I/O) interface at a periphery of a motherboard of a data processing device, and providing traces between a processor of the data processing device and the I/O interface across a surface of the motherboard. The traces provide conductive pathways between circuits of the processor and the I/O interface. The method also includes exposing the I/O interface through an external cosmetic surface of the data processing device in an assembled state thereof by way of a port complementary to that of a port of an external graphics card to enable direct coupling of the external graphics card to the data processing device through the exposed I/O interface by way of the complementary ports to provide boosting of processing through the data processing device.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: August 25, 2015
    Assignee: NVIDIA Corporation
    Inventors: Mahesh Sambhaji Jadhav, Rupesh Deorao Chirde
  • Patent number: 9105125
    Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 11, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd E. Martin, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
  • Patent number: 9105131
    Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. A block of geometry, containing a plurality of triangles, is split into sub-portions and sent to different geometry processing units. Each geometry processing unit generates a separate tiled geometry list that contains interleave markers that indicate an end to a sub-portion of a block of geometry overlapping a particular tile, processed by that geometry processing unit, and an end marker that identifies an end to all geometry processed for a particular tile by that geometry processing unit. The interleave markers are used to control an order of presentation of geometry to a hidden surface removal unit for a particular tile, and the end markers are used to control when the tile reference lists, for a particular tile, have been completely traversed.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 11, 2015
    Assignee: Imagination Technologies Limited
    Inventor: John W. Howson
  • Patent number: 9099050
    Abstract: A method and system for dynamically modifying the graphics capabilities of a mobile device is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of abstracting the handling of a first graphics subsystem and a second graphics subsystem associated with the mobile device, so that the first graphics subsystem and the second graphics subsystem appear as a third graphics subsystem to an operating system for the mobile device, detecting a configuration change event corresponding to the first graphics subsystem, masking the configuration change event to induce the generation of a reset event, and modifying the graphics capabilities of the mobile device to match the highest graphics capabilities between the first graphics subsystem and the second graphics subsystem that are accessible to the mobile device.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: August 4, 2015
    Assignee: NVIDIA Corporation
    Inventor: David Wyatt
  • Patent number: 9075559
    Abstract: Systems and methods for utilizing multiple graphics processing units for controlling presentations on a display are presented. In one embodiment, a dual graphics processing system includes a first graphics processing unit for processing graphics information; a second graphics processing unit for processing graphics information; and a component for controlling switching between said first graphics processing unit and said second graphics processing unit. In one embodiment, the component for controlling complies with appropriate panel power sequencing operations when coordinating the switching between the first graphics processing unit and the second graphics processing unit.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 7, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: David Wyatt, Manish Modi
  • Patent number: 9076361
    Abstract: An image processing apparatus and a method of controlling the same are provided. The image processing apparatus includes: one or more receiving units which receive a plurality of contents; a signal processing unit which outputs a first image frame by processing first content of the plurality of contents and outputs a second image frame by processing second content of the plurality of contents; an output unit which outputs a plurality of contents views by combining the first image frame and the second image frame; and a control unit which, if a sharing restriction command regarding a first contents view from among the plurality of contents views is obtained, restricts matching of a glasses apparatus with the first contents view.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-hwa Shin, Dae-ki Kim
  • Patent number: 9070201
    Abstract: An image processing apparatus includes a buffer unit which stores image data of one input image, an input control unit which causes the buffer unit to store the image data of the input image, a processing operation unit which outputs image data of a processed image generated by performing image processing based on one of a plurality of set processing conditions, a plurality of output control units corresponding to the processing conditions, wherein each output control unit causes the image data necessary when image processing is performed in a corresponding processing condition to be output from the buffer unit to the processing operation unit and causes the image data of the processed image to be output to a subsequent-stage processing circuit, and an output arbitrating unit which determines which processing condition is used to perform the image processing and permits the corresponding output control unit to perform output control.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: June 30, 2015
    Assignee: OLYMPUS CORPORATION
    Inventors: Ryusuke Tsuchida, Akira Ueno, Keisuke Nakazono
  • Patent number: 9053529
    Abstract: The present invention provides system for capturing displayed digital images. The system includes a selection tool utilisable by a user to select at least one portion of at least one displayed image; and, a capture routine arranged to reproduce the selected portion. If the selection tool selects only a portion of one image, then the captured image is sourced from a secondary storage source and if the selection tool selects more than one portion of one image, then the captured image is sourced from a primary storage source.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: June 9, 2015
    Assignee: Smart Internet CRC PTY LTD
    Inventor: Trent Apted
  • Patent number: 9041719
    Abstract: A method for transparently directing data in a multi-GPU system. A driver application receives a first plurality of graphics commands from a first graphics application and selects a first GPU from the multi-GPU system to exclusively process the first plurality of graphics commands. The first plurality of graphics commands is transmitted to the first GPU for processing and producing a first plurality of renderable data. The first plurality of renderable data is stored in a first frame buffer associated with the first GPU. A second plurality of graphics commands is received from a second graphics application and a second GPU is selected to exclusively process the second plurality of graphics commands. The second GPU processing the second plurality of graphics commands produces a second plurality of renderable data. The second plurality of renderable data is stored in a second frame buffer associated with the second GPU.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: May 26, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Andreas Wolf
  • Patent number: 9035968
    Abstract: A method for creating a distance dependent display that comprises providing an image separating mask having a plurality precision slits arranged in a pattern, generating an interlaced image from a plurality of images according to the pattern, and combining the interlaced image and the image separating mask to allow an observer to view substantially separately each the image from a respective of a plurality of different distances from the image separating mask.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: May 19, 2015
    Assignee: HumanEyes Technologies Ltd.
    Inventor: Assaf Zomet
  • Patent number: 9035956
    Abstract: In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: May 19, 2015
    Assignee: Apple Inc.
    Inventors: Richard W. Schreyer, Jason P. Jane, Michael J. E. Swift, Gokhan Avkarogullari, Luc R. Semeria
  • Publication number: 20150130820
    Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.
    Type: Application
    Filed: July 31, 2012
    Publication date: May 14, 2015
    Inventors: Kangyuan Shu, Junyong Ding, Yongnian Le, Weiliang Lion Lin, Xuefeng Deng, Yaojie Yan
  • Publication number: 20150123977
    Abstract: A method for synchronizing a plurality of pixel processing units is disclosed. The method includes sending a first trigger to a first pixel processing unit to execute a first operation on a portion of a frame of data. The method also includes sending a second trigger to a second pixel processing unit to execute a second operation on the portion of the frame of data when the first operation has completed. The first operation has completed when the first operation reaches a sub-frame boundary.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Nvidia Corporation
    Inventors: Mrudula KANURI, Kamal JEET
  • Publication number: 20150123978
    Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.
    Type: Application
    Filed: December 10, 2014
    Publication date: May 7, 2015
    Inventors: Hu Chen, Ying Gao, Xiaocheng Zhou, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
  • Patent number: 9019283
    Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 28, 2015
    Assignee: Transgaming Inc.
    Inventors: Gavriel State, Nicolas Capens, Luther Johnson
  • Patent number: 9013491
    Abstract: The disclosed embodiments provide a system that drives a display from a computer system. During operation, the system detects an idle state in a first graphics-processing unit (GPU) used to drive the display. During the idle state, the system switches from using the first GPU to using a second GPU to drive the display and places the first GPU into a low-power state, wherein the low-power state reduces a power consumption of the computer system.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 21, 2015
    Assignee: Apple Inc.
    Inventors: Ian C. Hendry, Rajabali M. Koduri
  • Patent number: 9013493
    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 21, 2015
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Colin Whitby-Strevens, Geertjan Joordens, Moon Jung Kim, Raman S Thiara
  • Patent number: 9007384
    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The sink processor may be operable to send a synchronization signal to the source processor through the interface. The source processor may be operable, dependent upon the synchronization signal, to send data to the sink processor.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Apple Inc.
    Inventor: Tripathi Brijesh
  • Patent number: 9009711
    Abstract: The present invention provides a particular efficient system of scheduling of tasks for parallel processing, and data communication between tasks running in parallel in a computer system. A particular field of application of the present invention is the platform-independent simulation of decomposition/partitioning of an application, in order to obtain an optimal implementation for parallel processing.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: April 14, 2015
    Inventors: Enno Wein, Vahagn Poghosyan
  • Patent number: 9001134
    Abstract: Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: April 7, 2015
    Assignee: NVIDIA Corporation
    Inventors: Franck R. Diard, Wayne Douglas Young, Philip Browning Johnson
  • Patent number: 9001141
    Abstract: An apparatus and method for providing display information generates, independently from an operating system, different screen subsections of a screen image using independent gamut remapping configurations to generate an output image in a target gamut space of a display. The method and apparatus also provides the generated output image for display or may display the generated output image.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: April 7, 2015
    Assignee: ATI Technologies ULC
    Inventors: David I. J. Glen, Jie Zhou
  • Patent number: 9001135
    Abstract: An improved approach for a remote graphics rendering system that can utilize both server-side processing and client-side processing for the same display frame. Some techniques for optimizing a set of graphics command data to be sent from the server to the client include: eliminating some or all data, that is not needed by a client GPU to render one or more images, from the set of graphics command data to be transmitted to the client; applying precision changes to the set of graphics command data to be transmitted to the client; and performing one or more data type compression algorithms on the set of graphics command data.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: April 7, 2015
    Assignee: Google Inc.
    Inventor: Makarand Dharmapurikar
  • Patent number: 8996078
    Abstract: A method for increasing data rate in wireless communications includes selectively activating a plurality of hardware accelerators, and performing, using the hardware accelerators, data processing for modem data based on parameters received from a processor.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: March 31, 2015
    Assignee: InterDigital Technology Corporation
    Inventors: Douglas R. Castor, Edward L. Hepler, Michael F. Starsinic, William C. Hackett, David S. Bass, Joseph W. Gredone, Paul L. Russell, Jr., Richard P. Gorman
  • Patent number: 8988452
    Abstract: Systems, apparatus, articles, and methods are described including operations for color enhancement via gamut expansion.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Ya-Ti Peng, Yi-Jen Chiu
  • Patent number: 8988442
    Abstract: A method and an apparatus for notifying a display driver to update a display with a graphics frame including multiple graphics data rendered separately by multiple graphics processing units (GPUs) substantially concurrently are described. Graphics commands may be received to dispatch to each GPU for rendering corresponding graphics data. The display driver may be notified when each graphics data has been completely rendered respectively by the corresponding GPU.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Michael James Elliot Swift, Kenneth Christian Dyke, Richard Warren Schreyer
  • Publication number: 20150077422
    Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Applicant: INTEL CORPORATION
    Inventors: Alon Gluska, Niraj Gupta, Mostafa Hagog, Dror Reif
  • Patent number: 8982138
    Abstract: A portable development and execution framework for processing media objects. The framework involves: accepting an instruction to perform a media processing function; accepting a media object to be associated with the media processing function; wrapping the media object with an attribute that specifies a type and format of the media object, and a hardware domain associated with the media object; and causing an execution domain to perform the media processing function on the media object. The instruction to perform the media processing function is expressed in a form that is independent of the hardware domain associated with the media object, and may also be independent of the type and format of the media object. The media object may be an image, and the media processing function may include an image processing function performed on a GPU.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: March 17, 2015
    Assignee: Avid Technology, Inc.
    Inventors: Shailendra Mathur, Daniel Beaudry, Michel Eid, Mathieu Lamarre, Raymond H. Tice
  • Patent number: 8982135
    Abstract: A server device 10 includes a frame buffer 13 that stores the image; an encoder 14e that compresses the image; a whole screen moving image conversion determination unit 14m that detects, from the image, a moving image area to be compressed by using the encoder 14e; a screen generator 14b that compresses the image such that image degradation is lower than that of the encoder 14e; a high frequency screen update area identifier 14n that detects, from an area compressed by the encoder 14e, a change area that has changed and calculates an accumulated change area by accumulating the change area; and a transmitter that transmits, to a client terminal 20, a moving image by compressing the moving image area detected by the moving image area and the detected change area and an image of the accumulated change area that is compressed by the screen generator 14b.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Kazuki Matsui, Kenichi Horio