Plural Graphics Processors Patents (Class 345/502)
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Patent number: 9495267Abstract: A system and method for providing assisted manual testing of computer related devices. Test commands are routed from a user system through a proxy module to a device under test. The responses of the device are routed through the proxy module to a user system. A user interface is run on the user system that allows the user to view the responses of the device in a log with the issued test commands. The user interface includes annotation dialog boxes and fields, highlighting elements and flagging elements through which a user can annotate and create notes for the test log as the test is being run on the device. Through the proxy module, a third party can act as a user and view the test log and user created annotations and notes as the test is being run on the device. The test log, annotation and notes can also be stored by the proxy module so that a third party can view them at a later time.Type: GrantFiled: July 12, 2013Date of Patent: November 15, 2016Assignee: Spirent Communications, Inc.Inventors: Brian Buege, Kevin Oelze, Amish Patel
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Patent number: 9489166Abstract: A data transmission method applied in a display, which includes a display panel, is provided. The data transmission method includes the following steps of: providing a host controller and n display drivers, n is a natural number greater than 1; providing a communication link under mobile industry processor interface (MIPI), connecting the host controller to the n display drivers; determining n virtual channel values Vc1-Vcn corresponding to the respective n display drivers; employing the host controller for providing a command with a virtual channel parameter through the communication link under MIPI; when the virtual channel parameter corresponds to an ith virtual channel values Vci, an ith display driver executing corresponding operations in response to the command, while the rest n?1 display drivers ignoring the command, wherein i is a natural number smaller than or equal to n.Type: GrantFiled: June 8, 2012Date of Patent: November 8, 2016Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Po-Chuan Chang-Chian, Chun-Yi Chou, Wing-Kai Tang, Ching-Chun Lin, Kai-I Dai, Shu-Wei Chang, Chih-Wei Tang
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Patent number: 9454397Abstract: A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialize one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.Type: GrantFiled: April 9, 2015Date of Patent: September 27, 2016Assignee: ARM LIMITEDInventors: Hakan Persson, Matt Evans, Jason Parker, Marc Zyngier
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Patent number: 9449360Abstract: Methods and apparatuses to reduce the number of sequential operations such as atomic operations in an application to be performed on a shared memory cell may be provided. A translation unit can detect in the application multiple atomic operations to be performed on the same memory and replaces the multiple atomic operations with an equivalent single atomic operation. In some implementations, the application includes shader code. In some implementations, each of the multiple atomic operations increment a value stored at the same memory by an update amount. The translation unit may calculate the partial prefix sum over all the atomic operations and replace the multiple atomic operations with a single atomic operation to increment the value stored at memory by the sum of the update amounts.Type: GrantFiled: December 28, 2011Date of Patent: September 20, 2016Assignee: Intel CorporationInventors: Tomasz Janczak, Marek Targowski
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Patent number: 9436289Abstract: An apparatus includes a transmitter configured to transmit content and a point of interest indicator to a second device. The content and the point of interest indicator are selected by a user of the first device using a single action. The point of interest indicator identifies a portion of the content to be highlighted by the second device.Type: GrantFiled: October 10, 2012Date of Patent: September 6, 2016Assignee: SONY CORPORATIONInventors: Akihiro Komori, Tomoaki Takemura, Shinya Masunaga, Nobuhiro Ozu
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Patent number: 9429755Abstract: A wearable device and a method for controlling display of the same are disclosed. Herein, the method for controlling the wearable device includes the steps of, when a contents or channel change in information currently being viewed through an external device occurs, determining whether or not the contents change corresponds to a change performed by a wearer of the wearable device, and, when it is determined that the contents change corresponds to a change performed by a viewer other than the wearer of the wearable device, displaying a content signal that was previously viewed prior to the contents change to the display means.Type: GrantFiled: January 15, 2014Date of Patent: August 30, 2016Assignee: LG ELECTRONICS INC.Inventors: Yongsin Kim, Doyoung Lee, Hyorim Park
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Patent number: 9424814Abstract: Buffer display techniques are described. In one or more implementations, at least part of an off-screen buffer is rasterized by an application to generate an item for display by the computing device. One or more communications are formed that describe the part of the off-screen buffer which contains the item that is to be copied to update an onscreen buffer.Type: GrantFiled: July 21, 2015Date of Patent: August 23, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Leonardo E. Blanco, Daniel N. Wood, Max McMullen, Allison W. Klein, Brian T. Klamik, Michael I. Borysenko, Keith D. Melmon, Michael P. Crider, Silvana Patricia Moncayo
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Patent number: 9413974Abstract: An information processing apparatus obtains a sensed image, and information representing imaging conditions used when the image was sensed. Based on the information representing the imaging conditions, the information processing apparatus generates conversion information corresponding to a conversion coefficient used in at least one of de-gamma processing and color balance correction processing for converting the sensed image into an image corresponding to a predetermined color response function. The information processing apparatus records the generated conversion information in association with the sensed image.Type: GrantFiled: July 14, 2014Date of Patent: August 9, 2016Assignee: CANON KABUSHIKI KAISHAInventor: Hironori Kaida
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Patent number: 9411659Abstract: Provided is a data processing method which can increase data processing speed without adding a new node to a distributed system. The data processing method may include: calculating a conversion number of cores corresponding to a number of processing blocks included in a graphics processing unit (GPU) of a node of a distributed system; calculating a adding up number of cores by adding up a number of cores included in a central processing unit (CPU) of the node of the distributed system and the conversion number of cores; splitting job data allocated to the node of the distributed system into a number of job units data equal to the adding up number of cores; and allocating a number of job units data equal to the number of cores included in the CPU to the CPU of the node of the distributed system and a number of job units data equal to the conversion number of cores to the GPU of the node of the distributed system.Type: GrantFiled: August 13, 2014Date of Patent: August 9, 2016Assignee: SAMSUNG SDS CO., LTD.Inventor: Sudhakar Sah
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Patent number: 9396577Abstract: Embodiments relate to selecting textures for a user-supplied photographic image in image-based three-dimensional modeling. In a first embodiment, a computer-implemented method includes a method positioning a geographic structure using user-supplied photographic images of a geographic structure. In the method, a user-supplied photographic images inputted by a user are received. Embedded camera parameters that specify a position of the cameras when each user-supplied photographic image was taken and are embedded in each user-supplied photographic image are read. An estimated location of the geographic structure is automatically determined based on the embedded camera parameters in each user-supplied photographic image. Each user-supplied photographic image to be texture mapped to the three-dimensional model is enabled.Type: GrantFiled: February 16, 2012Date of Patent: July 19, 2016Assignee: Google Inc.Inventors: Brian Brewington, David Hawkey, Bryce Stout
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Patent number: 9384583Abstract: An application executing on a rendering computer invokes a physics function request, e.g., to model the movement and interaction of objects to be rendered. The physics function request specifies a physics function to be performed on input data. Physics function request data is formatted for transmission over a network. The physics computer receives the physics function request data and performs an associated physics function using a physics GPU to generate physics computation result data. The physics computation result data is transmitted to the rendering computer over the network. A rendering GPU renders an image using the physics computation result data.Type: GrantFiled: October 27, 2006Date of Patent: July 5, 2016Assignee: NVIDIA CorporationInventor: Franck Diard
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Patent number: 9377925Abstract: A computer is operated by displaying a window on a display device, where the window is an opaque window overlaid on the entirety of a system desktop that includes graphical representations of system controls and application controls. The window displays user interface elements of an application program executing on the computer, and also includes a portal region displaying an image of the system desktop including counterparts of the system controls and application controls. The computer provides user-controlled operation of the system controls and application controls based on simulated user interaction with the counterparts of the system controls and application controls in the portal region. The application program can effectively coordinate the use of the display by itself and by the system and other applications using the system desktop, relieving the user of this task.Type: GrantFiled: August 30, 2013Date of Patent: June 28, 2016Assignee: Citrix Systems, Inc.Inventors: Matthew Anderson, Brian Green, Albert Alexandrov
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Patent number: 9348602Abstract: A method and apparatus for staged execution pipelining and allocating resource to staged execution pipelines are provided. One or more execution pipelines are established, where each of the one or more execution pipelines includes one or more execution stages. Data is provided to the one or more execution pipelines for processing and resources are allocated to the execution pipeline.Type: GrantFiled: September 3, 2013Date of Patent: May 24, 2016Assignee: Amazon Technologies, Inc.Inventors: Nishanth Alapati, Pradeep Vincent, David Carl Salyers
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Patent number: 9327199Abstract: Some implementations may include one or more servers to host multiple game instances of game modules. The one or more servers may determine whether a difference between a total rendering time to render output data for the multiple game instances and a rendering capacity of the one or more processors is less than a predetermined rendering threshold. In response to determining that the difference between the total rendering time and the rendering capacity of the one or more processors is less than the predetermined rendering threshold, the one or more servers may adjust a rendering complexity associated with one or more of the plurality of game instances.Type: GrantFiled: March 7, 2014Date of Patent: May 3, 2016Assignee: Microsoft Technology Licensing, LLCInventors: David Chiyuan Chu, Alastair Wolman, Roger Wattenhofer, Sergey Grizan
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Patent number: 9324294Abstract: The present invention sets forth an apparatus for supporting multiple digital display interface standards. In one embodiment, the apparatus includes a graphics processing unit (GPU) configured to determine a display device type of a display device that is in connection with a digital display interconnect, receive a display device information associated with the display device, and output a first data signal to the display device. The display device is of display port (DP) digital display interface standard and the digital display interconnect is of digital visual interface (DVI) digital display interface standard. The apparatus further includes a removable adaptor circuitry between the display device and the digital display interconnect.Type: GrantFiled: April 7, 2009Date of Patent: April 26, 2016Assignee: NVIDIA CorporationInventors: Yao-Nan Lin, Hsin-Yu Cheng
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Patent number: 9324174Abstract: Circuits, methods, and apparatus that provide multiple graphics processor systems where specific graphics processors can be instructed to not perform certain rendering operations while continuing to receive state updates, where the state updates are included in the rendering commands for these rendering operations. One embodiment provides commands instructing a graphics processor to start or stop rendering geometries. These commands can be directed to one or more specific processors by use of a set-subsystem device mask.Type: GrantFiled: November 24, 2009Date of Patent: April 26, 2016Assignee: NVIDIA CorporationInventor: Franck R. Diard
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Patent number: 9323653Abstract: An apparatus and method for processing data capable of providing an application with data converted based on various data types is provided. The data processing apparatus converts data, which is input from an input system, into various types of data. Various applications receive and use the data that is converted in the data processing apparatus.Type: GrantFiled: December 15, 2010Date of Patent: April 26, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Min Lee, Yoon-Soo Kim
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Patent number: 9319719Abstract: A method for processing video and/or audio signals utilizing a processing component which is communicatively connected with a source component having a compression stage for compressing video and/or audio signals is suggested. The method comprises the steps of receiving uncompressed video and/or audio signals as source signals at the source component from one or a plurality of sources; compressing the video and/or audio signals with a selectable compression factor; transmitting the compressed video and/or audio signals to the processing component; processing the compressed video/audio signals in the processing component to produce at least one production output signal. In addition to that a system for processing video and/or audio signals is proposed. The system comprises a source component, a routing component and a processing component. The source component transmits all received source signals through the routing component to the processing component.Type: GrantFiled: July 1, 2013Date of Patent: April 19, 2016Inventor: Alfred Krug
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Patent number: 9311152Abstract: Exemplary embodiments of methods and apparatuses to dynamically redistribute computational processes in a system that includes a plurality of processing units are described. The power consumption, the performance, and the power/performance value are determined for various computational processes between a plurality of subsystems where each of the subsystems is capable of performing the computational processes. The computational processes are exemplarily graphics rendering process, image processing process, signal processing process, Bayer decoding process, or video decoding process, which can be performed by a central processing unit, a graphics processing units or a digital signal processing unit. In one embodiment, the distribution of computational processes between capable subsystems is based on a power setting, a performance setting, a dynamic setting or a value setting.Type: GrantFiled: September 14, 2012Date of Patent: April 12, 2016Assignee: Apple Inc.Inventors: Howard Miller, Ralph Brunner
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Patent number: 9305374Abstract: An electronic device with a display displays a user interface on the display. The device determines a first set of content-display values for one or more content-display properties of first content that corresponds to a respective region of the display. The device determines a first set of control-appearance values for one or more control-appearance parameters based on the first set of content-display values. The device displays a control in the respective region of the display, where an appearance of the control is determined based on the first content and the first set of control-appearance values, and displaying the control includes applying a blur operation to the first content to generate first blurred content and overlaying a translucent colored layer over the first blurred content.Type: GrantFiled: February 18, 2014Date of Patent: April 5, 2016Assignee: APPLE INC.Inventors: Kenneth L. Kocienda, Tiffany S. Jon, Chanaka G. Karunamuni
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Patent number: 9269331Abstract: The present invention is directed to providing, in a plurality of information processing apparatuses which transmits and receives objects, a technique for causing the display contents in the apparatuses to be related by the apparatuses performing simple exchange of information. An information processing apparatus includes a display control unit configured to cause, based on the information on the azimuth direction in which an object displayed on a screen has been moved, from other apparatus that transmits the information and the information indicating the azimuth direction in which the screen of the information processing apparatus has been directed, an object which is the same as an object displayed on a screen of the other apparatus to appear from an azimuth direction opposite of the azimuth direction in which the object displayed on the screen of the other apparatus has been moved, in the screen of the information processing apparatus.Type: GrantFiled: November 25, 2013Date of Patent: February 23, 2016Assignee: Canon Kabushiki KaishaInventor: Masayuki Ishizawa
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Patent number: 9251552Abstract: An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.Type: GrantFiled: June 28, 2012Date of Patent: February 2, 2016Assignee: INTEL CORPORATIONInventors: Seh Kwa, Nir Sucher, Vijay Sai Reddy Degalahal
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Patent number: 9224358Abstract: A process is utilized to provide a multi-display configuration. The process detects, at a first proximity-based device within a first display device, a presence of a second proximity-based device within a second display device. The presence is within a proximity. Further, the process displays a first portion of a multi-display image at the first display device based upon a location of the first display device relative to the second display device.Type: GrantFiled: August 28, 2013Date of Patent: December 29, 2015Assignee: Disney Enterprises, Inc.Inventors: Edward Drake, Mark Arana, Evan Acosta
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Patent number: 9218787Abstract: An image-displaying device includes a storage section, an image data generation section, a timing information acquisition section, and a display control section. The image data generation section is configured to generate image data indicative of an image of a subject and output to the storage section the image data including an Nth image data and an (N+i)th image data. The timing information acquisition section is configured to acquire timing information indicative of a timing related to generation of the image data and a timing at which output of each of the Nth image data and the (N+i)th image data to the storage section is completed. The display control section is configured to control a display section to commence reading and displaying the Nth image data in accordance with acquisition of the timing information indicating that the output of the (N+i)th image data to the storage section is completed.Type: GrantFiled: October 27, 2014Date of Patent: December 22, 2015Assignee: Seiko Epson CorporationInventors: Ryuichi Shiohara, Masahiro Kitano, Toshiyuki Yamamoto
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Patent number: 9201579Abstract: According to various exemplary embodiments, user input of a single continuous gesture from a touch-sensitive surface of a first device to a touch-sensitive surface of a second device is detected. It is determined that the gesture corresponds to a drag-and-drop operation performed on an icon displayed on the touch-sensitive surface of the first device, the icon representing user profile information. Moreover, it is determined that the gesture terminates proximate to a job position user interface element in a job recruitment user interface window displayed on the touch-sensitive surface of the second device. Thereafter, the user profile information of the user is transferred from the first device to the second device.Type: GrantFiled: December 7, 2012Date of Patent: December 1, 2015Assignee: LinkedIn CorporationInventors: Yevgeniy Jim Brikman, Bowei Gai, Matthew David Shoup
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Patent number: 9202303Abstract: One embodiment of the present invention sets forth a technique for compositing a rendered path object into an image buffer. A shader program executing within a graphics processing unit (GPU) performs a stenciling operation for the path object and subsequently performs a texture barrier operation, which invalidates caches configured to store texture and frame buffer data within the GPU. The shader program then performs covering operation for the path object in which the shader renders color samples for the path object and composites the color samples into an image buffer. The shader program binds to the image buffer for access as both a texture map and a writeable image. Stencil values are reset when corresponding pixels are written once per path object, and texture caches are invalidated via the texture barrier operation, which is performed after each covering operation per path object.Type: GrantFiled: May 20, 2011Date of Patent: December 1, 2015Assignee: NVIDIA CorporationInventors: Jeffrey A. Bolz, Mark J. Kilgard
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Patent number: 9191221Abstract: The invention relates to a technique for protecting a point-to-multipoint primary tree in a connected mode communications network set up from a primary root node to leaf nodes in the event of a fault affecting the primary root node by means of a back-up tree between a back-up root node and at least one merge node, said at least one merge node belonging to a branch of the primary tree coming from the primary root node. A merge node executes the following steps: a step of receiving a request to set up the back-up tree sent by the back-up root node including an identifier of the protected primary root node; and a step of configuring a routing rule in a table, the aim of said rule being to route packets coming from the back-up tree to branches of the primary tree coming from said merge node, said routing rule being activated only in the event of a fault affecting the primary root node.Type: GrantFiled: May 12, 2009Date of Patent: November 17, 2015Assignee: OrangeInventors: Jean-Louis Le Roux, Mohamad Chaitou
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Patent number: 9189448Abstract: A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to a reference space, e.g., the physical space that is represented by the image data, to generate the data samples and each data sample may be tagged with a corresponding reference space coordinate value and routed through the network to one or more of the processors according to the tag.Type: GrantFiled: August 20, 2009Date of Patent: November 17, 2015Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventors: Andrew Wolfe, Tom Conte
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Patent number: 9183610Abstract: The invention provides a method for driving a graphic processing unit (GPU), where a driver applies two threads to drive one ore more GPUs. The method includes the steps of: (a) activating a rendering thread and a displaying thread in response to invoking by an application thread of a graphics application; (b) sending according to the rendering thread a plurality of rendering instructions for enabling generation of at least a first rendered frame and a second rendered frame; and (c) sending according to the displaying thread one or more interpolating instructions and one or more displaying instructions, the one or more interpolating instructions enabling execution of interpolation according to the at least a first rendered frame and the second rendered frame to create one or more interpolated frames, and the one or more displaying instructions enabling display of the one or more interpolated frames.Type: GrantFiled: January 18, 2013Date of Patent: November 10, 2015Assignee: NVIDIA CorporationInventor: Scott Saulters
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Patent number: 9178747Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.Type: GrantFiled: November 29, 2012Date of Patent: November 3, 2015Assignee: NVIDIA CorporationInventors: Rolf VandaVaart, Timothy James Murray, Peter Michael Buckingham
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Patent number: 9172932Abstract: An image projection system includes a scaler IC, a micro-projector, a video connector, and a controller. The video connector is coupled to the scaler IC and the micro-projector. The controller controls the video connector and the scaler IC to form a first signal path mode and a second signal path mode. The video connector transmits a first image signal from the scaler IC for external displaying in the first signal path mode. The video connector receives a second image signal from a peripheral device and passes the second image signal to the micro-projector for projection in the second signal path mode.Type: GrantFiled: July 9, 2012Date of Patent: October 27, 2015Assignee: LITE-ON TECHNOLOGY CORPORATIONInventor: Chi-Hung Lin
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Patent number: 9135189Abstract: Described herein is providing GPU resources across machine boundaries. Data centers tend to have racks of servers that have limited access to GPUs. Accordingly, disclosed herein is providing GPU resources to computing devices that have limited access to GPUs across machine boundaries.Type: GrantFiled: September 7, 2011Date of Patent: September 15, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Parag Chakraborty, Bradley Stephen Post, Vladimir Pavlov, B. Anil Kumar
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Patent number: 9137050Abstract: A system and approach for utilizing a graphical processing unit in a demand response program. A demand response server may have numerous demand response resources connected to it. The server may have a main processor and an associated memory, and a graphic processing unit connected to the main processor and memory. The graphic processing unit may have numerous cores which incorporate processing units and associated memories. The cores may concurrently process demand response information and rules of the numerous resources, respectively, and provide signal values to the main processor. The main processor may the provide demand response signals based at least partially on the signal values, to each of the respective demand response resources.Type: GrantFiled: November 18, 2011Date of Patent: September 15, 2015Assignee: Honeywell International Inc.Inventor: Edward Koch
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Patent number: 9117392Abstract: A method includes providing an Input/Output (I/O) interface at a periphery of a motherboard of a data processing device, and providing traces between a processor of the data processing device and the I/O interface across a surface of the motherboard. The traces provide conductive pathways between circuits of the processor and the I/O interface. The method also includes exposing the I/O interface through an external cosmetic surface of the data processing device in an assembled state thereof by way of a port complementary to that of a port of an external graphics card to enable direct coupling of the external graphics card to the data processing device through the exposed I/O interface by way of the complementary ports to provide boosting of processing through the data processing device.Type: GrantFiled: July 5, 2013Date of Patent: August 25, 2015Assignee: NVIDIA CorporationInventors: Mahesh Sambhaji Jadhav, Rupesh Deorao Chirde
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Patent number: 9105125Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.Type: GrantFiled: December 5, 2012Date of Patent: August 11, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Todd E. Martin, Mangesh Nijasure, Jason Carroll, Randy W. Ramsey, Brian A. Buchner
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Patent number: 9105131Abstract: A method and an apparatus are provided for combining multiple independent tile-based graphic cores. A block of geometry, containing a plurality of triangles, is split into sub-portions and sent to different geometry processing units. Each geometry processing unit generates a separate tiled geometry list that contains interleave markers that indicate an end to a sub-portion of a block of geometry overlapping a particular tile, processed by that geometry processing unit, and an end marker that identifies an end to all geometry processed for a particular tile by that geometry processing unit. The interleave markers are used to control an order of presentation of geometry to a hidden surface removal unit for a particular tile, and the end markers are used to control when the tile reference lists, for a particular tile, have been completely traversed.Type: GrantFiled: August 5, 2013Date of Patent: August 11, 2015Assignee: Imagination Technologies LimitedInventor: John W. Howson
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Patent number: 9099050Abstract: A method and system for dynamically modifying the graphics capabilities of a mobile device is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of abstracting the handling of a first graphics subsystem and a second graphics subsystem associated with the mobile device, so that the first graphics subsystem and the second graphics subsystem appear as a third graphics subsystem to an operating system for the mobile device, detecting a configuration change event corresponding to the first graphics subsystem, masking the configuration change event to induce the generation of a reset event, and modifying the graphics capabilities of the mobile device to match the highest graphics capabilities between the first graphics subsystem and the second graphics subsystem that are accessible to the mobile device.Type: GrantFiled: August 22, 2007Date of Patent: August 4, 2015Assignee: NVIDIA CorporationInventor: David Wyatt
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Patent number: 9076361Abstract: An image processing apparatus and a method of controlling the same are provided. The image processing apparatus includes: one or more receiving units which receive a plurality of contents; a signal processing unit which outputs a first image frame by processing first content of the plurality of contents and outputs a second image frame by processing second content of the plurality of contents; an output unit which outputs a plurality of contents views by combining the first image frame and the second image frame; and a control unit which, if a sharing restriction command regarding a first contents view from among the plurality of contents views is obtained, restricts matching of a glasses apparatus with the first contents view.Type: GrantFiled: December 19, 2012Date of Patent: July 7, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-hwa Shin, Dae-ki Kim
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Patent number: 9075559Abstract: Systems and methods for utilizing multiple graphics processing units for controlling presentations on a display are presented. In one embodiment, a dual graphics processing system includes a first graphics processing unit for processing graphics information; a second graphics processing unit for processing graphics information; and a component for controlling switching between said first graphics processing unit and said second graphics processing unit. In one embodiment, the component for controlling complies with appropriate panel power sequencing operations when coordinating the switching between the first graphics processing unit and the second graphics processing unit.Type: GrantFiled: February 27, 2009Date of Patent: July 7, 2015Assignee: NVIDIA CORPORATIONInventors: David Wyatt, Manish Modi
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Patent number: 9070201Abstract: An image processing apparatus includes a buffer unit which stores image data of one input image, an input control unit which causes the buffer unit to store the image data of the input image, a processing operation unit which outputs image data of a processed image generated by performing image processing based on one of a plurality of set processing conditions, a plurality of output control units corresponding to the processing conditions, wherein each output control unit causes the image data necessary when image processing is performed in a corresponding processing condition to be output from the buffer unit to the processing operation unit and causes the image data of the processed image to be output to a subsequent-stage processing circuit, and an output arbitrating unit which determines which processing condition is used to perform the image processing and permits the corresponding output control unit to perform output control.Type: GrantFiled: September 23, 2013Date of Patent: June 30, 2015Assignee: OLYMPUS CORPORATIONInventors: Ryusuke Tsuchida, Akira Ueno, Keisuke Nakazono
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Patent number: 9053529Abstract: The present invention provides system for capturing displayed digital images. The system includes a selection tool utilisable by a user to select at least one portion of at least one displayed image; and, a capture routine arranged to reproduce the selected portion. If the selection tool selects only a portion of one image, then the captured image is sourced from a secondary storage source and if the selection tool selects more than one portion of one image, then the captured image is sourced from a primary storage source.Type: GrantFiled: September 11, 2008Date of Patent: June 9, 2015Assignee: Smart Internet CRC PTY LTDInventor: Trent Apted
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Patent number: 9041719Abstract: A method for transparently directing data in a multi-GPU system. A driver application receives a first plurality of graphics commands from a first graphics application and selects a first GPU from the multi-GPU system to exclusively process the first plurality of graphics commands. The first plurality of graphics commands is transmitted to the first GPU for processing and producing a first plurality of renderable data. The first plurality of renderable data is stored in a first frame buffer associated with the first GPU. A second plurality of graphics commands is received from a second graphics application and a second GPU is selected to exclusively process the second plurality of graphics commands. The second GPU processing the second plurality of graphics commands produces a second plurality of renderable data. The second plurality of renderable data is stored in a second frame buffer associated with the second GPU.Type: GrantFiled: December 3, 2009Date of Patent: May 26, 2015Assignee: NVIDIA CORPORATIONInventor: Andreas Wolf
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Patent number: 9035968Abstract: A method for creating a distance dependent display that comprises providing an image separating mask having a plurality precision slits arranged in a pattern, generating an interlaced image from a plurality of images according to the pattern, and combining the interlaced image and the image separating mask to allow an observer to view substantially separately each the image from a respective of a plurality of different distances from the image separating mask.Type: GrantFiled: July 23, 2008Date of Patent: May 19, 2015Assignee: HumanEyes Technologies Ltd.Inventor: Assaf Zomet
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Patent number: 9035956Abstract: In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).Type: GrantFiled: May 8, 2012Date of Patent: May 19, 2015Assignee: Apple Inc.Inventors: Richard W. Schreyer, Jason P. Jane, Michael J. E. Swift, Gokhan Avkarogullari, Luc R. Semeria
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Publication number: 20150130820Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.Type: ApplicationFiled: July 31, 2012Publication date: May 14, 2015Inventors: Kangyuan Shu, Junyong Ding, Yongnian Le, Weiliang Lion Lin, Xuefeng Deng, Yaojie Yan
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Publication number: 20150123978Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.Type: ApplicationFiled: December 10, 2014Publication date: May 7, 2015Inventors: Hu Chen, Ying Gao, Xiaocheng Zhou, Shoumeng Yan, Peinan Zhang, Mohan Rajagopalan, Jesse Fang, Avi Mendelson, Bratin Saha
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Publication number: 20150123977Abstract: A method for synchronizing a plurality of pixel processing units is disclosed. The method includes sending a first trigger to a first pixel processing unit to execute a first operation on a portion of a frame of data. The method also includes sending a second trigger to a second pixel processing unit to execute a second operation on the portion of the frame of data when the first operation has completed. The first operation has completed when the first operation reaches a sub-frame boundary.Type: ApplicationFiled: November 6, 2013Publication date: May 7, 2015Applicant: Nvidia CorporationInventors: Mrudula KANURI, Kamal JEET
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Patent number: 9019283Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.Type: GrantFiled: August 29, 2012Date of Patent: April 28, 2015Assignee: Transgaming Inc.Inventors: Gavriel State, Nicolas Capens, Luther Johnson
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Patent number: 9013491Abstract: The disclosed embodiments provide a system that drives a display from a computer system. During operation, the system detects an idle state in a first graphics-processing unit (GPU) used to drive the display. During the idle state, the system switches from using the first GPU to using a second GPU to drive the display and places the first GPU into a low-power state, wherein the low-power state reduces a power consumption of the computer system.Type: GrantFiled: February 26, 2014Date of Patent: April 21, 2015Assignee: Apple Inc.Inventors: Ian C. Hendry, Rajabali M. Koduri
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Patent number: 9013493Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.Type: GrantFiled: December 18, 2012Date of Patent: April 21, 2015Assignee: Apple Inc.Inventors: Brijesh Tripathi, Colin Whitby-Strevens, Geertjan Joordens, Moon Jung Kim, Raman S Thiara