Abstract: A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.

Abstract: An organic light emitting display apparatus includes: a first pixel electrode and a second pixel electrode on a substrate and spaced apart from each other, each of the first pixel electrode and the second pixel electrode including a reflective layer; a pixel definition layer extending between and overlapping adjacent edges of the first pixel electrode and the second pixel electrode; a first intermediate layer and a second intermediate layer respectively on the first pixel electrode and the second pixel electrode; and an opposite electrode on the first intermediate layer, the second intermediate layer and the pixel definition layer and including a reflective layer.

Abstract: A processor determines a drive scheme from among candidates of a plurality of drive schemes having differing schemes for supplying a signal to a signal line of a display panel. A controller stores a scheme drive information in which a drive scheme information and a signal control information in a drive scheme are associated. A controller receives a scheme information from a processor, and controls a signal supplied to a signal line of a display panel, the control being made based on a scheme information and a scheme drive information.

Abstract: An organic light emitting diode (OLED) display device including a first transistor configured to supply a data voltage to a first node according to a scan signal; a first capacitor connected to the first node at one end of the first capacitor, and connected to a second node at the other end; a second transistor configured to supply a reference voltage to the second node according to a sensing signal; a driving transistor including a drain electrode receiving a high-level source voltage or an initial voltage, a gate electrode connected to the second node, and a source electrode connected to a third node; and an OLED including a cathode electrode receiving a low-level source voltage and an anode electrode connected to the third node.

Abstract: An array substrate, a manufacture method thereof, and a display device with the array substrate are provided. The array substrate includes a substrate; a first gate scanning line; a first gate insulating layer; an active layer; a date scanning line; a pixel electrode formed in a pixel unit defined by the first gate scanning line and the data scanning line and over the data scanning line; and a second gate scanning line formed over or below the first gate scanning line. The second gate scanning line is substantially overlapped with the first gate scanning line in a stacking direction of the array substrate, and is arranged to be insulated from the first gate scanning line, the active layer, the data scanning line, and the pixel electrode, respectively.

Abstract: A method and system for operating a pixel array having at least one pixel circuit is provided. The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period. The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.

Abstract: A pixel circuit is capable of maintaining a display quality even in cases where an input transistor has a low mobility, or where it is impossible to take a sufficient selection period for each scanning line. A pixel circuit includes an organic EL element (OLED), transistors, and a capacitor. A drive transistor has its drain terminal connected to a HIGH level power supply line, and has its source terminal connected to an anode terminal of the OLED. The first input transistor has its gate terminal connected to a scanning line Si, and is disposed between a data line Dj and the gate terminal of the drive transistor. The second input transistor has its gate terminal connected to a scanning line (Si?1) in the (i?1)th row, and is disposed between a data line and the gate terminal of the drive transistor. The capacitor is disposed between the gate terminal and the source terminal of the drive transistor.

Abstract: A display device is configured that the common electrode wiring layer is divided in a source wiring layer direction, the metal wiring layer is disposed above the source wiring layer at a position in contact with the upper part of the common electrode wiring layer, and the metal wiring layer is not disposed at a position where the common electrode wiring layer is divided. Alternatively, the metal wiring layer is not disposed at a position between the same colors as those at the division position of the common electrode wiring layer.

Abstract: The invention discloses a thin film transistor drive circuit and a drive method thereof and a liquid crystal display device. The thin film transistor drive circuit includes a plurality of scan lines, a scan signal output port configured to sequentially apply a scan signal to each of the scan lines, and a plurality of logic circuits. Each of the logic circuits is connected with one of the scan lines and a control signal line. The logic circuits are added to a drive circuit, and an input control signal corresponding to a truth table of the logic circuit is input for a preset duration by using a logic relationship of the logic circuit, so that an output control signal output to a scan line can be obtained to improve a scan signal on the scan line, to improve a delay distortion at the time of being turned off.

Abstract: A liquid crystal display device with an increased pixel aperture ratio is provided. A liquid crystal display device that displays an image with high contrast and high luminance is provided. The liquid crystal display device includes a first pixel electrode; a second pixel electrode; a transistor; a capacitor; a first insulating film; a second insulating film; and a third insulating film. The transistor includes a gate electrode; a gate insulating film; a first oxide semiconductor film; and a source electrode and a drain electrode. One of a pair of electrodes of the capacitor includes a second oxide semiconductor film. The first insulating film is provided over the first oxide semiconductor film. The second insulating film is provided over the second oxide semiconductor film such that the second oxide semiconductor film is sandwiched between the first insulating film and the second insulating film. The third insulating film overlaps with an end of the first pixel electrode.

Abstract: The present invention provides a source driving circuit and an LCD device. The source driving circuit includes output channels, and each output channel includes a first switch element, a second switch element, a first output end, and a second output end. The first switch element and the second switch element are respectively connected to the first output end and the second output end. When the first switch element is turned on, the output channel outputs a display signal, and when the second switch element is turned on, the output channel provides recycled charges which are generated when the display signal is changed from a positive voltage to a negative voltage. The source driving circuit can recycle charges to make the most of charges generated when the display signals change from positive voltages to negative voltages and reduce power consumption of the LCD device.

Abstract: The present invention discloses a display panel and a drive circuit thereof. The drive circuit comprises: a data signal providing module, generating a data signal; a first select signal generation module, providing a first select signal; a second select signal generation module, providing a second select signal; a select module, comprising a select switch combination receives a first, a second select signal, and outputs the data signal to the pixel array. The present invention can reduce the voltage level changing frequency of the select signal.

Abstract: The present invention discloses a liquid crystal display device and a driving method thereof, and the device comprises a plurality of data lines; a plurality of gate lines; a plurality of common lines; at least one dummy gate line; a plurality of gate line trigger circuits; and a plurality of common line trigger circuits; wherein, one end of the last gate line is connected with the last gate line trigger circuit; one end of each of remaining gate lines are connected with a gate line trigger circuit corresponding to said each of remaining gate lines, and the other end of said each of the remaining gate lines are connected with the succeeding gate line trigger circuit; the first common line trigger circuit is connected with one dummy gate line, and each of remaining common line trigger circuits is connected with one or more preceding gate line trigger circuits. Latency to the charging time is effectively reduced with the liquid crystal display device of this invention.

Abstract: The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.

Abstract: A display panel and an organic light-emitting diode (OLED) display including the display panel are disclosed. The display panel includes a first pixel configured to emit a first color of light, a second pixel configured to emit a second color of light, and a third pixel configured to emit a third color of light. Each of the first to third pixels includes a light emission current applying unit including a driving transistor and a storage capacitor, a gate electrode of the driving transistor configured to receive a data signal from a display driver of the OLED display. The panel includes a light emission unit configured to emit light based on a light emission current. The panel also includes an initialization voltage supply unit configured to provide an initialization voltage to the gate electrode of the driving transistor and the first electrode of the OLED.

Abstract: A panel driver integrated circuit (IC) and a cooling method of the panel driver IC are provided. The panel driver IC includes a data encoder, a level shifter, a Digital-to-Analog Converter (DAC), a rearrangement circuit and an output buffer. The data encoder receives and selectively changes an original data for outputting to the level shifter. An input terminal and an output terminal of the level shifter are coupled to an output terminal of the data encoder and a data input terminal of the DAC, respectively. The output terminals of the rearrangement circuit are respectively coupled to the reference voltage input terminals of the DAC for providing different reference voltages. The rearrangement circuit correspondingly rearranges the order of the reference voltages according to the operation of the data encoder. An input terminal of the output buffer is coupled to an output terminal of the DAC.

Abstract: A pixel circuit of an organic light emitting display device includes an emission unit, an emission control unit, a current supply unit, and a switch unit. The emission unit emits light based on an emission current. The emission control unit controls an emission operation of the emission unit based on a scan signal and a data signal. The current supply unit adjusts the emission current based on a current sinking operation performed based on an external constant current source, where the current supply unit is connected to the external constant current source. The switch unit controls an electrical connection operation between the emission control unit and the current supply unit.

Abstract: The present invention provides a liquid crystal display panel and a gate drive circuit thereof. The gate drive circuit comprises a plurality of shift register circuit, and the plurality of shift register circuit are series cascade connected, and each shift register circuit comprises: a first pull-up holding circuit, coupled to the first node, the first clock signal, a first reference voltage and a second reference voltage, and employed to keep a low voltage level of the first node; a compensating circuit, coupled to the first node or the first pull-up holding circuit, and employed to compensate the voltage level of the first node or the first pull-up holding circuit. Thereby, the stability of long-term operation of the gate drive circuit can be promoted to raise the quality of the display panel.

Abstract: A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.

Abstract: A display driving circuit includes first through (2*n)-th buffers, a buffer controller, first through n-th image processing units, and a source driver. The buffer controller circularly selects one of the first through (2*n)-th buffers in an order from the first buffer to the (2*n)-th buffer at each of a plurality of first time intervals, and stores pixel data received during the first time interval in the selected buffer. Each of the first through n-th image processing units is coupled to two corresponding buffers among the first through (2*n)-th buffers, and processes the pixel data, which are stored in at least one of their corresponding buffers, during n of the first time intervals to generate processed data when the pixel data are stored in the corresponding buffer during the first time interval. The source driver generates analog signals based on the processed data.

Abstract: A display device includes a display substrate, on which a display area and a non-display area are defined, a plurality of gate lines arranged in the display area to extend in a first direction, a gate driving unit including a plurality of stages which outputs gate signals to the plurality of gate lines, and a plurality of pixel rows disposed in the display area and connected to the plurality of gate lines, where a driving area and an electrode area are defined in the display area between two adjacent pixel rows in a second direction among the plurality of pixel rows, at least a part of the plurality of stages is disposed in the driving area, and a compensation electrode is disposed in the electrode area.

Abstract: The present invention provides a display panel and driving method thereof, and display device. The display panel includes an array substrate and a color filter substrate, disposed oppositely; the array substrate comprising a plurality of scan lines, disposed at intervals; a plurality of data line, disposed at intervals, and crossing over and isolated from the scan lines; and a plurality of pixel units, arranged in a matrix form, and driven by the scan lines and data lines; each of the pixel units further divided into at least two active areas; the color filter substrate includes at least two common electrodes, disposed correspondingly to the active areas, the at least two common electrodes applying common voltages independently. The present invention can eliminate the non-uniform luminance problem in display images and improve the display quality.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: A solid-state image pickup device including a pixel unit in which a plurality of photoelectric conversion elements having different sensitivities are arranged; and a pixel reading unit configured to read and add output signals from the plurality of photoelectric conversion elements in the pixel unit, and to obtain an output signal seemingly from one pixel. The pixel unit includes an absorbing unit configured to absorb overflowing electric charge from a photoelectric conversion element with a high sensitivity.

Abstract: Data signal lines, scanning signal lines, and pixels are formed in each of first and second regions of a liquid crystal panel, and the first half of a current frame and the second half of the current frame are written to the first and second regions, respectively. A data signal with polarity inverted for each vertical scanning period is supplied to each data signal line. A scanning direction of the first region is identical to a scanning direction of the second region and the first and second regions are arranged to line up in this order in the scanning direction. In the first and second regions, the potential of the data signal is corrected according to a distance from a scanning start end portion.

Abstract: A display device includes a pixel matrix having pixel rows and pixel columns and including pixels having switching elements positioned alternately at a corner near an upper and a lower side of each pixel row and positioned alternately at a corner near an upper and a lower side of and alternately at a corner near a left and a right side of each pixel column; multiple pairs of gate lines transmitting a gate-on voltage; and multiple data lines transmitting data voltages, wherein each pair of gate lines are disposed at the upper and lower sides of each pixel row with the pixels in each row connected to the gate line positioned nearest the respective switching element, and each data line is disposed between adjacent pairs of pixel columns and connected to pairs of pixels where one pixel of the pair has a switching element positioned nearest the respective data line.

Abstract: A circuit for driving a liquid crystal display includes a high selection unit turned on by a high selection signal, a low selection unit turned on by a low selection signal and transferring a low data signal to one side of the first storage capacitor, a high transfer unit connected to one side of the first storage capacitor, turned on by a high transfer signal and transferring voltage, a low transfer unit connected to one side of the first storage capacitor, turned on by a low transfer signal and transferring the voltage stored at one side of the first storage capacitor to one side of the liquid crystal capacitor, and a reset unit connected to one side of the liquid crystal capacitor, turned on by a reset signal and transferring a center voltage to one side of the liquid crystal capacitor.

Abstract: According to one embodiment, a display device includes a first signal line, a second signal line, a first switching element, a second switching element, an insulating film, a first contact hole, a second contact hole, a first pixel electrode and a second pixel electrode. The first contact hole is formed in the insulating film, and located between the first signal line and the second signal line. The second contact hole is formed in the insulating film, located opposite to the first contact hole with respect to the second signal line, and also located side by side with the first contact hole in the first direction.

Abstract: An array substrate, a liquid crystal display panel and a liquid crystal display device. The array substrate comprises data lines, gate lines and a pixel array provided on a base substrate. Each data line is connected with at least one type of sub-pixels in the pixel array, and sub-pixels of same type connected with a same data line have same polarity, and the sub-pixels connected with the same data line are connected with different gate lines, respectively.

Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N?1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.

Abstract: A method of reducing a time for switching a gate line driving signal of display device having plural gate lines from a level that is less than a full gate-on level to the gate-on level is disclosed. The method may include: during a gate line pre-charging period of a respective gate line, causing the gate line driving signal to be at the full gate-on level; during a corresponding gate line main-charging period that follows the pre-charging period, causing the gate line driving signal of to be at the full gate-on level; and during an interposed period that is interposed between the gate line pre-charging period and its corresponding gate line main-charging period, causing the gate line driving signal to be at an intermediate level that is between the full gate-on level and an opposed gate-off level.

Abstract: A display apparatus includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. Each pixel of the plurality of pixels comprises a switching device coupled to a corresponding gate line of the plurality of gate lines and to a corresponding data line of the plurality of data lines, a micro-electro-mechanical system coupled to an output electrode of the switching device, and a control device coupled to the output electrode of the switching device. The control device comprises a storage capacitor coupled to the output electrode of the switching device and a coupling capacitor coupled to the output electrode of the switching device, the storage capacitor connected in parallel with the coupling capacitor. The output electrode of the switching device, the storage capacitor, the coupling capacitor, and a first electrode of the micro-electro-mechanical system are all directly connected to each other.

Abstract: A pixel array and an organic light emitting display device including the same, can display an image with uniform luminance by compensating for a variation in threshold voltage/mobility of a driving transistor for each pixel and compensating for a change in efficiency due to degradation of an organic light emitting diode. A first pixel among the pixel array includes an organic light emitting diode; a pixel circuit positioned among an anode electrode of the organic light emitting diode, a first scan line and a first data line through which a data signal is supplied to the first pixel, and controlling current flowing in the organic light emitting diode; and a switching element controlling the coupling between a second data line through which a data signal is supplied to a second pixel of the plurality of pixels and the anode electrode of the organic light emitting diode.

Abstract: A shift register includes unit circuits connected in a cascade, and each of the unit circuits includes a logic circuit, a first output unit, and a second output unit. The first output unit is a buffer amplifier for outputting a driving signal and includes: a first transistor for outputting a first voltage; and a second transistor for outputting a second voltage lower than the first voltage. The second output unit is a buffer amplifier for outputting a signal to a next unit circuit in the cascade and includes: a third transistor for outputting a third voltage; and a fourth transistor for outputting a fourth voltage lower than the third voltage. The second voltage is set at a potential higher than the fourth voltage.

Abstract: The rate of reading from a memory for storing display irregularity correction data is lowered. At the time of display, calculation is carried out in a correction calculation section using an input signal and correction data in one or more memory units, and brightness inconsistency correction is carried out. The way in which correction calculation is carried out in the correction calculation section is changed for every frame.

Abstract: A semiconductor device capable of inhibiting incorrect data readout is provided. In a memory cell including a first transistor, a second transistor, and a third transistor, the potential of a fourth wiring is set to GND when data is written, and the potential is set to VDD when data is read out, for example. Note that the potential of a third wiring is set to GND when data is written and when data is read out, for example. When data is read out, the first transistor is off, so that a first capacitor and a fourth capacitor are connected in series. The potential of a second electrode of the second capacitor increases in this state, and thus part of charges accumulated in the second capacitor transfers to the first capacitor, so that the potential of a node increases.

Abstract: A display device has a plurality of arrayed display pixels. A drive transistor includes a first gate electrode and supplies the current corresponding to a level of a luminance signal to the luminescence element. A switching transistor includes a source electrode, a drain electrode, a second gate electrode and a semiconductor layer. The semiconductor layer is faced with the second gate electrode and has, in a channel width direction perpendicular to a channel length direction of the switching transistor, a channel region with a first width and a remainder region with a second width larger than the first width. The source electrode or the drain electrode is connected to the first gate electrode. The source electrode and the drain electrode are provided on the semiconductor layer at an interval. The second gate electrode overlaps, in a plan view, the channel region entirely and the remainder region at least partially.

Abstract: Provided is a light-emitting device which can emit monochromatic light with high purity due to a microcavity effect and which can emit white light in the case of a combination of monochromatic light. Provided is a high-definition light-emitting device. Provided is a light-emitting device with low power consumption. In a light-emitting device with a white-color filter top emission structure, one pixel is formed of four sub-pixels of RBGY, an EL layer includes a first light-emitting substance which emits blue light and a second light-emitting substance which emits light corresponding to a complementary color of blue, and a semi-transmissive and semi-reflective electrode (an upper electrode) is formed so as to cover an edge portion of the EL layer.

Abstract: A liquid crystal display (“LCD”) device includes a display panel, a data driving part, and at least one first light-blocking part and at least one second light-blocking part. The display panel includes a plurality of pixels and a plurality of data lines. The pixels are arranged in a column direction and a row direction. At least one of the data lines extends in a zigzag shape along the column direction to be discontinuously disposed between two adjacent columns of the pixels. The at least one data line is electrically connected to two of the pixels that are adjacent in the row direction. The second light-blocking part is thinner than the first light-blocking part. The first light-blocking part and the second light-blocking are repeatedly disposed on an area between two adjacent columns of the pixels. The data driving part applies a data signal to the data lines.

Abstract: A novel highly reliable display device is provided. Further, a novel display device capable of displaying images with less flicker is provided. Further, a display device capable of displaying eye-friendly still images is provided. The display device includes a feedthrough correction circuit which corrects a primary image signal. The feedthrough correction circuit corrects the primary image signal to compensate predicted feedthrough.

Abstract: An array substrate and a display device that comprises the array substrate are disclosed.

Abstract: The present disclosure provides a capacitive built-in touch screen, its touch positioning method, and a display device. In the capacitive built-in touch screen, at least one of the gate lines is set as a touch scanning line, and the capacitive built-in touch screen further includes at least one touch sensing line arranged on the array substrate. The touch scanning line intersects the touch sensing line in different planes. The touch sensing line is configured to, when a scanning signal is applied to the touch scanning line, couple the scanning signal through a touch sensing capacitor to obtain and output a touch sensing signal. The touch sensing capacitor is arranged at an intersection of the touch scanning line and the touch sensing lines on different planes.

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Abstract: An image sensor system has a first stitched image sensor part that has multiple image sensing pixels and pixel gates. The multiple pixel gates are connected together by a first line on the first stitched image sensor part, and said multiple pixel gates are controlled by a first control signal. A second stitched image sensor part also has multiple sensing pixels and pixel gates, and the multiple pixel gates are connected together by a second line on said second stitched image sensor part, and said multiple pixel gates on said second stitched image sensor part are controlled by the first control signal. A driver for the first control signal, wherein said driver includes a first part for controlling said multiple pixel gates of said first stitched image sensor part and said driver has a second part, also driven by the same first control signal, for controlling said multiple pixel gates of said second stitched image sensor part.

Abstract: A semiconductor device includes: a transistor including a gate electrode, a gate insulating film over the gate electrode, a semiconductor layer over the gate insulating film, and a source electrode and a drain electrode over the semiconductor layer; a first insulating film comprising an inorganic material over the transistor; a second insulating film comprising an organic material over the first insulating film; a first conductive film over the second insulating film and in a region overlapping with the semiconductor layer; a third insulating film comprising an inorganic material over the first conductive film; and a second conductive film over the third insulating film and in a region overlapping with the first conductive film. The absolute value of a first potential applied to the first conductive film is greater than the absolute value of a second potential applied to the second conductive film.

Abstract: A circuit, which includes a high voltage driver, is disclosed. The high voltage driver includes a P-type field effect transistor (PFET) and a source bias circuit. The source bias circuit receives a low voltage input signal and applies a direct current (DC) bias to the low voltage input signal to provide a DC biased signal. The PFET has a first source, a first gate, and a first drain. The first source receives the DC biased signal. The first gate receives a first low voltage DC supply signal. The first drain provides a high voltage output signal based on the DC biased signal and the first low voltage DC supply signal. In this regard, the high voltage driver receives and translates the low voltage input signal to provide the high voltage output signal.

Abstract: A liquid crystal display device is disclosed. The device includes data lines, gate lines, and common lines in parallel with the gate lines. The device also includes at least one dummy gate line in parallel with the gate lines, gate line trigger circuits, and common line trigger circuits. One end of the last gate line is connected with the last gate line trigger circuit, one end of each of remaining gate lines is connected with a gate line trigger circuit corresponding to said each of remaining gate lines, and the other end of said each of the remaining gate lines is connected with a next gate line trigger circuit. The first common line trigger circuit is connected with one dummy gate line, and each of remaining common line trigger circuits is connected with one or more preceding gate line trigger circuits.

Abstract: A pixel includes an organic light emitting diode (OLED), a first transistor having a gate electrode coupled to a first node, a first electrode coupled to a first power supply, and a second electrode coupled to the OLED, a first capacitor for storing a data signal, and a second capacitor coupled between the first node and the second electrode of the first transistor to charge a voltage corresponding to the data signal and a threshold voltage of the first transistor, wherein, in a period where a voltage stored in the first capacitor is supplied to the first node, the second capacitor is electrically blocked from the first node.

Abstract: A display device includes a pixel, a data line, a scan line, a data driver, and a scan driver. The pixel is configured to display an image. The data line is configured to transmit data voltages to the pixel. The scan line is configured to transmit a scan signal to the pixel. The data driver is configured to: float the data line during a first period of a frame, apply, after the first period, a first data voltage to the data line during a second period of the frame, and apply, after the second period, a voltage waveform to the data line that varies the applied voltage from the first data voltage to a target voltage during a third period of the frame. The scan driver is configured to selectively apply the scan signal to the scan line.

Abstract: A liquid crystal display includes: a liquid crystal capacitor; a first switching element which transmits a data voltage to the liquid crystal capacitor; a second switching element connected to the liquid crystal capacitor; and a transformation capacitor connected to the second switching element. A difference between a first time when the first switching element is turned on and a second time when the second switching element starts is turned on is greater than 1 horizontal period and less than 1 frame period.