Abstract: The display device includes a pixel circuit, wherein the pixel circuit includes: a light-emitting element configured to emit light based on a driving current; a driving transistor configured to control the driving current, and including a gate electrode, a source electrode, and a drain electrode, wherein a data voltage is applied to the source electrode; a storage capacitor connected to and disposed between the gate electrode of the driving transistor and a power voltage; and a reset transistor configured to apply an initialization voltage to an anode electrode of the light-emitting element in response to a scan signal, wherein when the display device operates in a Variable Refresh Rate mode for a refresh frame, an operating frequency of the scan signal varies for an anode reset frame of the refresh frame. Thus, response and image quality characteristics at a low gray level are simultaneously improved.

Abstract: Disclosed are a gate row driving circuit and a driving method thereof, and a display substrate. The gate row driving circuit includes: an input module; a driving module, configured to connect to a pixel driving voltage output by the input module and provide a pixel power supply voltage to power a current pixel row under drive of the pixel driving voltage; a thermoelectric module, configured to perform thermoelectric conversion on operating heat when the operating heat of the driving module matches preset charging heat to obtain compensation power; and a capacitor module. The driving module is also configured to superimpose a charging voltage continuously generated by the capacitor module onto the pixel driving voltage after the thermoelectric module charges the capacitor module according to the compensation power to obtain an updated pixel driving voltage.

Abstract: An electroluminescent display device includes a display panel including a plurality of pixels each having a light emitting element and a driving thin film transistor for controlling a driving current flowing through the light emitting element and connected to a data line and a gate line, a panel driver connected to the data line and the gate line, and a timing controller configured to control an operation of the panel driver such that the operation is divided into an emission period in which the light emitting element emits light and a non-emission period in which light emission is stopped and to perform control such that a data voltage is input through the data line during the non-emission period and light emitting elements to which the data voltage is applied simultaneously emit light during the emission period.

Abstract: A digital display includes a plurality of pixel rows. For each pixel row, the digital display includes an EM gate driver configured to supply the pixel row with a luminance-controlling signal during each of a plurality of image frames. A luminance controller is configured to instruct the EM gate drivers to supply a pulse-width modulated signal to the plurality of pixel rows. Some pixel rows are supplied with a pulse-width modulated signal starting with an on pulse, and some pixel rows are supplied with a pulse-width modulated signal starting with an off pulse, on the same or different image frames.

Abstract: A display device is disclosed that includes a display panel which includes a pixel, a driving controller which receives an input image signal and outputs an output image signal, and a data driving circuit which provides a data signal corresponding to the output image signal to the pixel. The pixel includes a light emitting device and a first transistor electrically connected to the light emitting device. The driving controller includes an initial threshold voltage map that stores an initial threshold voltage of the first transistor, a delta threshold voltage calculator that calculates a delta threshold voltage of the first transistor over an operating time based on the initial threshold voltage, a weight calculator that calculates a weight based on the initial threshold voltage and the delta threshold voltage, and a compensator that receives the input image signal and outputs an output image signal obtained by compensating for a threshold voltage of the first transistor based on the weight.

Abstract: A display apparatus includes a data generation circuit, a source driver circuit, and a pixel. The source driver circuit is electrically connected to the pixel through first and second wirings. The pixel includes a display device that is a liquid crystal device, a potential of one electrode of the display device can be a potential of the first wiring, and a potential of the other electrode of the display device can be a potential of the second wiring. The image data generation circuit has a function of generating digital image data including first and second data. One of the first and second wirings is made to have a potential corresponding to first data, and the other of the first and second wirings is made to have a potential corresponding to the second data. The potential of the first wiring and the potential of the second wiring are interchanged.

Abstract: Regarding a display device using a display element driven by a current, visibility in an environment where external light is strong is improved while suppressing deterioration in display quality and an increase in cost. An adjustment circuit (22) and an adjustment capacitor (Cp) for adjusting an amount of drive currents are provided for each one pixel circuit (20) or every plural pixel circuits (20). As for the adjustment capacitor (Cp), a first electrode is connected to a drive current control node (NG) connected to a control terminal of a drive transistor (T4), and a second electrode is connected to a light emission intensity adjustment node (NP) in the adjustment circuit (22).

Abstract: According to one embodiment, a stereoscopic image display device includes a three-dimensional pixel unit, a backlight, and an arithmetic/control circuit. The three-dimensional pixel unit includes a plurality of pixel cells that are formed of an optical material having electrically changeable optical characteristics, are arranged in a mutually separated manner and in a three-dimensional manner, and are electrically connected with transparent wiring patterns. The backlight is configured to emit illumination light to the three-dimensional pixel unit. The arithmetic/control circuit is configured to control the plurality of pixel cells individually via the wiring patterns on the basis of input three-dimensional image data to cause the three-dimensional pixel unit to function as a transmissive hologram.

Abstract: An electrical driver can be used to provide electrical drive signals to a first and second electrically controllable optical privacy glazing structures. A first electrical drive signal can be applied to the first privacy glazing structure and a second electrical drive signal can be applied to the second privacy glazing structure. Applying the first and second electrical drive signal can comprise temporally staggering delivery of the first and second electrical drive signals such that a peak power draw and/or a peak current draw from the first privacy glazing structure is temporally offset from a peak power draw and/or a peak current draw from the second privacy glazing structure. Staggering can include delaying the application of one electrical drive signal relative to the other, phase shifting one electrical drive signal relative to the other, or a combination thereof.

Abstract: The touch sensor includes a touch detection area with at least a part of a curved area having a curved edge. In the touch detection area, a plurality of first electrodes and second electrodes disposed side by side in a first direction and in a second direction are disposed. A plurality of first electrodes disposed side by side in the first direction are connected to each other. A plurality of second electrodes disposed side by side in the second direction are connected to each other. In the curved area, distances between the plurality of first electrodes and the second electrodes in the first direction gradually change in the second direction.

Abstract: Provided is a driving method of a display panel, which relates to a field of a display technology. The display panel includes a pixel array, the pixel array comprises a plurality of rows of sub-pixels, and the driving method includes: driving, in a same display frame, different sub-pixels in a row of the sub-pixels respectively by a forward driving signal and a negative driving signal, wherein a voltage conversion rate of the forward driving signal is greater than a voltage conversion rate of the negative driving signal under a same display gray scale. A driving circuit, a driving chip and a display device are further provided.

Abstract: A circuit for eliminating afterimage and a display device. The circuit includes a power supply unit, an afterimage elimination unit and a discharge unit. First and second output ends of the power supply unit are connected with the afterimage elimination unit, respectively. A control end of the discharge unit is configured in electric connection with the control unit, and an execution end of the discharge unit is connected with the first output end of the power supply unit. When the screen is turned off, the control unit outputs a first control signal to the discharge unit. The discharge unit discharges at the first output end of the power supply unit according to the first control signal, so as to expedite a falling of the first voltage output from the first output end of the power supply unit.

Abstract: A drive method for a display panel (100) includes: obtaining display data corresponding to a current display frame, and a current refresh rate (S10); determining a target rate level corresponding to the current refresh rate according to the current refresh rate and prestored rate levels corresponding one-to-one to different refresh rate intervals (S20); and controlling sub-pixels in the display panel (100) to be charged with a data voltage according to the target rate level and the display data (S30).

Abstract: In a liquid crystal display device, scanning lines, video signal lines and pixels are formed in respective regions enclosed by the scanning lines and the video signal lines. In the liquid crystal display device, a pixel electrode and a thin-film transistor (TFT) are formed in each of the pixels, a first insulating film is formed between a common electrode formed in common for a plurality of pixels and the pixel electrode, the pixel electrode is connected to one of the video signal lines via the TFT, the TFT has a gate connected to one of the scanning lines, a constant common voltage is supplied to the common electrode, the scanning lines are sequentially scanned from a first scanning line in one frame, and a predetermined voltage is applied for a predetermined period to all the scanning lines before a scanning signal is applied to the first scanning line.

Abstract: A display panel, a circuit board and a display device are provided. The display panel includes a first pad region including a first pad connected to a first integrated circuit, a second pad region including a second pad electrically connected to a second integrated circuit, a third pad region including third pads electrically connected to a circuit board and a common signal line electrically connected to the common electrode of the sub-pixel. The display panel further includes a first signal line and a second signal line, the first pad is electrically connected to the third pad through the first signal line, the second pad is electrically connected to the third pad through the second signal line; the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board.

Abstract: A display device includes a display panel including a pixel, and a panel driver driving the display panel. The pixel includes first to fifth transistors. The first transistor is connected between a power line and the light-emitting element. The second transistor is connected between a data line and the first transistor and receives a first scan signal. The third transistor is connected between the first transistor and a first node and receives a second scan signal. The fourth transistor is connected between the first node and an initialization line. The fifth transistor is connected between the first transistor and the first node and receives a fourth scan signal. The first and fourth scan signals are simultaneously activated, and a period of the second scan signal is smaller than or equal to a period of the fourth scan signal.

Abstract: A display apparatus includes a display panel including a pixel area in which a plurality of pixels is disposed and a peripheral area outside the pixel area; a transmissive light source disposed in a first area of the pixel area; and a timing controller which controls the transmissive light source not to emit light when pixels disposed corresponding to the first area of the pixel area among the plurality of pixels are present in at least one of an image data input period and a pixel light emission period.

Abstract: A display panel and a display device are disclosed in the present application. The display panel includes a plurality of data lines, a Demux circuit, a plurality of signal lines, and at least one signal adjusting trace. Wherein the signal adjusting trace and corresponding signal lines are disposed in different layers and intersect with each other, along a second direction, the signal adjusting trace is configured to output a voltage adjusting signal at least before a next controlling signal is output by controlling traces, to adjust a voltage value of a next data voltage output by the signal line within an output period of the voltage adjusting signal.

Abstract: An electronic device includes gate lines, maintained at a low level voltage during a blank period and sequentially scanned during an active period in a frame period, and data lines. Voltage polarities of the data lines for all the blank period are respectively identical with voltage polarities of the data lines during the active period. A first level voltage applied to one of the data lines during all the blank period is related to an average value or a maximum value of level voltages of a portion or all of the data lines during the active period. A time length of the blank period in the frame period with the average value or the maximum value applied to one of the data lines during all the blank period is longer than a first time length of a first blank period in a first frame period adjacent to the frame period.

Abstract: A scan driver includes stages including an input block to change a first node voltage to a gate on voltage based on an input signal, a second node control block to control second node voltage based on a first clock signal and the first node voltage, a scan output block to output a second clock signal as a scan signal based on the first node voltage, and to output a first gate off voltage as the scan signal based on the second node voltage, a carry output block to output the second clock signal as a carry signal based on the first node voltage, and to output a second gate off voltage different from the first gate off voltage as the carry signal based on the second node voltage, and a first node control block to transfer the carry signal to the first node based on a next carry signal.

Abstract: A data driving circuit is disclosed that includes an amplifier and an offset control circuit. The amplifier has an offset voltage and is configured to output a data voltage reflecting the offset voltage. The offset control circuit is configured to control, in response to an input control signal, the amplifier to output the data voltage reflecting the offset voltage in a positive direction or a negative direction. The data driving circuit may enhance the display quality of a low grayscale image.

Abstract: A display panel includes a plurality of data lines, a plurality of scan lines, a plurality of share bar groups, and a plurality of pixel units. Each of the share bar groups includes a first share bar and a second share bar. Each of the pixel units includes a first thin-film transistor, a second thin-film transistor, and a share thin-film transistor. The first thin-film transistor and the second thin-film transistor are electrically connected to a same one of the data lines. The first thin-film transistor, the second thin-film transistor, and the share thin-film transistor are electrically connected to a same one of the scan lines. The share thin-film transistor is electrically connected to the second thin-film transistor and one of the share bar groups.

Abstract: The present application discloses a display device and an electronic device. The display device includes a liquid crystal display panel and a driving integrated circuit. An output end of the driving integrated circuit is electrically connected to shared thin-film transistors of subpixels having a same color. By supplying different powers to the shared thin-film transistors of the subpixels having different colors through different output ends of the driving integrated circuit, a power of a load carried by a same power supply loop can be reduced, thereby increasing a uniformity of displayed brightness.

Abstract: A system that can intelligently help a user judge the resolution requirement of the image content. In an example, the display panel can show in different virtual resolutions or the system can automatically judge whether the image content requires high or low resolution using a similarity judgement. The system can then inform the display panel what virtual resolution should be shown or what the optimal resolution is using the similarity judgment and send the image content to the display panel with that resolution.

Abstract: An object of the present invention is to provide a light deflection device having a simple structure suitable for reducing the size and weight where a deflection angle can be increased. The object can be achieved with a light deflection device including: a light deflection element that deflects incident light in one direct to be emitted; a driving unit that drives the light deflection element; and a diffraction element that is disposed on a light emission side of the light deflection element in which a periodic structure pitch gradually changes from a center of deflection from the light deflection element toward an outside.

Abstract: A display apparatus includes a display panel, a driving controller, a gate driver and a data driver. The driving controller is configured to insert a compensation image to first image data including a normal image to generate second image data. The gate driver is configured to shift an output time of a gate signal and to output the gate signal having a shifted output time to the display panel. The data driver is configured to generate a data voltage based on the second image data and to output the data voltage to the display panel. A gate shift amount when the compensation image is applied is substantially the same as a gate shift amount immediately before the compensation image is applied.

Abstract: A display device includes: a display panel which receives a driving voltage and an initialization voltage; a power manager which provides the driving voltage to the display panel; and a voltage generator which receives a feedback driving voltage from the display panel and generates the initialization voltage based on the feedback driving voltage. The feedback driving voltage is a voltage that is fed back to the voltage generator after the driving voltage supplied from the power manager passes through the display panel.

Abstract: A scan driver includes a control unit, a first output unit, a second output unit, and a masking control unit. The control unit outputs a first control signal to a first control node and outputs a second control signal to a second control node. The first output unit is connected to the first control node, a first output terminal, and a first voltage terminal, and operates in response to the first control signal. The second output unit is connected to the second control node, the first output terminal, and a second voltage terminal, and operates in response to the second control signal. The masking control unit is connected between an input terminal, to which a clock signal is input, and the first control node and controls a voltage level of the first control signal in response to a masking enable signal.

Abstract: This display device includes: a grouping processing unit that groups a plurality of drive lines into a plurality of groups each having a set grouped number of adjacent drive lines; a setting processing unit that sets a display magnification of a display screen according to the grouped number; a display processing unit that causes a display panel to display the display screen in the display magnification; and a determination processing unit that determines, in a state where the display screen is displayed on the display panel in the display magnification, a position of a touch operation on the display screen that is displayed in the display magnification based on an output signal that is output from a plurality of sense lines in response to an input signal that is input to each of the grouped number of drive lines.

Abstract: The present disclosure is directed to display circuitry that can be formed on a flexible substrate. The circuitry includes a voltage divider formed from a first and second non-linear resistor device or a first and second transistor coupled in a diode configuration. The circuitry includes a driving thin film transistor coupled to the voltage divider. The non-linear resistor devices may include a lower electrode that is amorphous metal or a crystalline metal. The first and second transistor coupled in a diode configuration may have a lower electrode that is amorphous metal. Upper electrodes may be crystalline metal. The driving thin film transistors may have the lower electrode as amorphous or crystalline metal.

Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

Abstract: A digital display includes a plurality of pixel rows. For each pixel row, the digital display includes an EM gate driver configured to supply the pixel row with a luminance-controlling signal during each of a plurality of image frames. A luminance controller is configured to instruct the EM gate drivers to supply a pulse-width modulated signal to the plurality of pixel rows. Some pixel rows are supplied with a pulse-width modulated signal starting with an on pulse, and some pixel rows are supplied with a pulse-width modulated signal starting with an off pulse, on the same or different image frames.

Abstract: Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i?1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M?1, wherein a sum of all Xj voltages for j=1:(M?1) is greater than 0.25*VDD.

Abstract: A display device includes: a display panel including first and second wirings; a control circuit board spaced apart from the display panel and including a power management circuit which provides a driving voltage to the first and second wirings; a first cable coupled to the control circuit board and electrically connecting the power management circuit and the first wiring; a second cable coupled to the control circuit board and electrically connecting the power management circuit and the second wiring; an abnormal coupling detector connected between the first and second wirings and generating first and second protection signals based on a difference between a first voltage of the first wiring and a second voltage of the second wiring; and a voltage supply controller counting the first and second protection signals, and providing a shutdown signal to the power management circuit such that the power management circuit stops providing the driving voltage.

Abstract: A display apparatus includes a display panel, a gate driver, a data driver and a driving controller. The display panel including a gate line and a data line displays an image based on input image data. The gate driver outputs a gate signal to the gate line. The data driver outputs a data voltage to the data line. The driving controller includes an area divider dividing the input image data into first and second area data, a first variable frequency driver determining a first driving frequency of the first area data based on a flicker value according to a grayscale value and generating a first data signal of the first driving frequency and a second variable frequency driver determining a second driving frequency of the second area data based on a flicker value according to a grayscale value and generating a second data signal of the second driving frequency.

Abstract: A display device includes: a plurality of first pixels connected to a first scan line; a plurality of second pixels connected to a second scan line; and a plurality of third pixels connected to a third scan line, wherein, from a position in a first frame period, an image portion displayed by the first pixels, the second pixels, and the third pixels, which are connected to first data lines, is shifted in a first direction, in a second frame period next to the first frame period, wherein an image portion displayed by the first pixels and the second pixels, which are connected to second data lines, is shifted in the first direction, in the second frame period, wherein an image portion displayed by the third pixels connected to the second data lines is shifted in a direction different from the first direction, in the second frame period.

Abstract: An image display method includes generating luminance data, applying a special filter to the luminance data, generating luminance setting data, generating gradation setting data, and controlling a backlight based on the luminance setting data and a liquid crystal panel based on the gradation setting data. The luminance data indicates a luminance value for each of light-emitting regions of the backlight based on a maximum gradation value among gradation values of image pixels of an input image that correspond to the light-emitting region. The special filter is applied such that, with respect to each light-emitting region, a difference of the luminance value thereof from the luminance values of neighboring light-emitting regions decreases, and the luminance setting data is generated therefrom. The gradation setting data sets a gradation value of each pixel of the liquid crystal panel, and is generated based on the input image and the luminance setting data.

Abstract: The present disclosure provides a device and a method for detecting a screen freeze error of a display of a vehicle. The method comprises monitoring a drive pattern of at least one pixel in a porch area during a time period corresponding to a plurality of image frames, wherein the porch area including at least one of a front porch area and a back porch area of a display panel driven according to the plurality of image frames; and determining occurrence of a screen freeze error by comparing the drive pattern of the at least one pixel with a preset drive pattern.

Abstract: A display device that includes a plurality of scanning lines, a plurality of data lines, and a pixel unit in which a pixel is specified by the scanning line and the data line, in which image data of one line is simultaneously displayed for a plurality of adjacent scanning lines, image data to be simultaneously displayed is made different between an N frame and an (N+1) frame that are temporally consecutive, and the image data is shifted by one line, and the image data of a last scanning line of at least one of the N frame or the (N+1) frame is hidden.

Abstract: The present application discloses a cross voltage compensation method for a display panel, a display panel and a display device. The cross voltage compensation method includes steps of transmitting a preset voltage signal to in-plane data lines after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, keeping all the scanning lines at a close state while transmitting the preset voltage signal to in-plane data lines, and keeping all the scanning lines at a close state after scan of scanning lines of a last row of a current frame is completed and before scanning lines of a first row of a next frame are started, that is, V-blank time.

Abstract: A pair of eyeglasses may include one or more adjustable lenses that are each configured to align with a respective one of a user's eyes. The adjustable lenses may each include electrically modulated optical material such as one or more liquid crystal cells, each having a phase profile that is adjusted using patterned electrodes. Analog voltages may be provided to the patterned electrodes through variable-resistance conductive paths that are each coupled to a subset of the patterned electrodes. Digital voltage selection circuitry may be used to select which analog voltage to apply to each of the variable-resistance conductive paths from a predetermined set of analog voltages that are generated off of the lens. The digital voltage selection circuitry may include an array of multiplexers, each of which selects a desired voltage based on control signals received from digital control circuitry such a shift register and/or a decoder.

Abstract: Disclosed are a display panel, a driving method therefor, a display device. The display panel includes pixel circuits, data lines, write control lines, compensation control lines, a first driving circuit connected to compensation control lines, a second driving circuit connected to write control lines. Each column of pixel circuits corresponds to one data line, each row of pixel circuits corresponds to one write control line, one compensation control line. The first driving circuit outputs compensation control signals to pixel circuits by compensation control lines, second driving circuit outputs write control signals to pixel circuits by write control lines. The pulse width of compensation control signals is N times pulse width of write control signals, write control signals on two adjacent write control lines do not overlap, an overlap time of compensation control signals on two adjacent compensation control lines is (N?1)/N of pulse width of compensation control signals.

Abstract: In an electro-optical device, pixel circuits are provided corresponding to an intersection between a scanning line in an i-th row and a data line in a k-th column in a display region, and an intersection between a scanning line and data line. The pixel circuit is brought into an optical state in accordance with a voltage of a data line when a scanning line is selected. In an odd frame period, in the i-th row selection period and the (i+1)-th row, a data signal of a voltage corresponding to the i-th row and k-th column of data of the top image is output, and in an even frame period, in the i-th row selection period and the (i+1)-th row, a data signal of a voltage corresponding to the (i+1)-th row and the k-th column of data of the bottom image is output.

Abstract: A display device includes a display control circuit. The display control circuit includes: an arithmetic unit obtaining a video signal, and calculating, in accordance with the video signal, an average voltage value of a source signal in a display period; and a controller and a signal synthesizer supplying, in the display period, a source signal, based on the video signal, from a source drive circuit to a plurality of source lines, and supplying, in a suspension period, a source signal, having the average voltage value, from a source drive circuit to each of the source lines.

Abstract: A direct current-to-direct current (“DC-DC”) converter includes: a first converter which outputs a first power voltage in a normal mode or a power saving mode based on a inductor current generated therein, where the first converter operates in a first driving manner in the normal mode, and operates in a second driving manner in the power saving mode; a second converter which outputs a second power voltage based on a inductor current generated therein, where the second converter operates in a third driving manner in the power saving mode, and a magnitude of the second power voltage in the power saving to mode is different from that in the normal mode; and a mode selector which supplies a mode control signal to the first and second converters, where the first and second converters are driven in the normal mode or the power saving mode based on the mode control signal.

Abstract: A light emitting display device includes a display panel configured to display an image, a data driver configured to supply a data voltage to data lines of the display panel, and a sensing circuit configured to obtain a sensing voltage through sensing lines of the display panel after reflecting a negative impedance value canceling impedance differences of the sensing lines.

Abstract: The display apparatus includes a data generation circuit, a source driver circuit, and a pixel. The source driver circuit is electrically connected to the pixel through first and second wirings. The pixel includes a display device that is a liquid crystal device, a potential of one electrode of the display device can be a potential of the first wiring, and a potential of the other electrode of the display device can be a potential of the second wiring. The image data generation circuit has a function of generating digital image data including first and second data. One of the first and second wirings is made to have a potential corresponding to first data, and the other of the first and second wirings is made to have a potential corresponding to the second data. The potential of the first wiring and the potential of the second wiring are interchanged.

Abstract: An embodiment of the present disclosure is directed to a method of determining a charging time. The method includes: obtaining frame images corresponding to at least three grayscales; determining a luminance and a corresponding charging time of at least one test position in each of the frame images; obtaining a charging time luminance variance curve corresponding to the test position according to the luminance of the at least one test position in each of the frame images and the corresponding charging time; and determining the charging time corresponding to a highest luminance in the charging time brightness change curve as an optimal charging time.

Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

Abstract: A signal obtained through sampling a gate start pulse signal GSP by using one of a plurality of gate clock signals is supplied as a shift pulse for a forward shift action (a forward shift start pulse signal) to the first stage of a plurality of stages constituting a bidirectional shift register, and a signal obtained through sampling the gate start pulse signal GSP by using another one of the plurality of gate clock signals is supplied as a shift pulse for a backward shift action (a backward shift start pulse signal) to the last stage of the plurality of stages constituting the bidirectional shift register.