Abstract: An active level shift (ALS) driver circuit, a liquid crystal display device including the ALS driver circuit, and a method of driving the liquid crystal display device. A liquid crystal display device having a slim external black matrix may be provided by fabricating the ALS driver circuit using inverters and a transmission gate.

Abstract: A shift register driven by two complementary clock signals is integrated on an active-matrix substrate of a flat screen for controlling selection of rows of image points of the flat screen is disclosed. The shift register includes a control transistor driven by one of the clock signals, and connected between this clock signal and an output node connected to a corresponding row. The shift register also includes a capacitor connected between an internal node connected to the gate of the control transistor. The output node is discharged each time the flat screen starts.

Abstract: A display module includes a scan line, a data line, a driving circuit and a level converting circuit. The driving circuit has at least one first driving unit and at least one second driving unit electrically connected to the first driving unit. A non-DC signal is transmitted between the first driving unit and the second driving unit for controlling the first driving unit and/or the second driving unit. The first driving unit outputs a first driving signal to the scan line. The second driving unit outputs a second driving signal to the level converting circuit. The level converting circuit is electrically connected with the driving circuit and the data line, and outputs a display signal to the data line according to the second driving signal. A driving method of the display module is also disclosed.

Abstract: A display apparatus and a method for driving a display panel thereof are provided. The display panel includes an inducing signal readout line and N gate lines, in which N is a natural number. The inducing signal readout line is coupled to a plurality of inducing circuits. Each inducing circuit is coupled to one of the gate lines, and the Nth gate line is coupled to one of the inducing circuits. In the method, several gate pulses are provided to drive the gate lines sequentially to turn on the corresponding inducing circuits, wherein at least a portion of the driving duration of a gate pulse provided to the Nth gate line is in a blanking time between two frames.

Abstract: A gate driving method for a liquid crystal display (LCD) and a gate driver thereof are provided. The LCD has a plurality of scan lines. The method starts by generating a gate driving signal. A correction signal is superposed to the gate driving signal to generate a corrected gate driving signal and to reduce a high voltage level of the gate driving signal, wherein a polarity of the correction signal is opposite to a polarity of the gate driving signal. The corrected gate driving signal is then outputted to drive one of the corresponding scan lines.

Abstract: A method for driving a light modulation element includes: applying light to the light modulation element in accordance with an image to be displayed on the light modulation element while applying a DC voltage between a pair of electrode layers of the light modulation element; and applying a pulse voltage having an opposite polarity to the DC voltage applied so far between the pair of electrode layers with the light being applied, and terminating the applying of the light when the applying of the pulse voltage is terminated. The applying of the light, the applying of the pulse voltage and the terminating of the applying of the light are executed sequentially.

Abstract: A display device, including a substrate; an array of pixels arranged in rows and columns forming a light-emitting area over the substrate, each pixel including a first electrode, one or more layers of light-emitting material located over the first electrode, and a second electrode located over the one or more layers of light-emitting material; a first serial buss having a plurality of electrical conductors, each electrical conductor connecting one chiplet in a first set of chiplets to only one other chiplet in the first set in a serial connection, the chiplets being distributed over the substrate in the light-emitting area, each chiplet including one or more store-and-forward circuits for storing and transferring data connected to its corresponding electrical conductor; and a driver circuit in each chiplet for driving at least one pixel in response to data stored in the store-and-forward circuit.

Abstract: The present invention aims to reduce flickers of the liquid crystal display device and enable the use of liquid crystal material exhibiting a high response speed, and to enhance light usage efficiency of the field sequential type liquid crystal display device. After writing the video signal to all the pixels in each sub-frame period, a correction voltage signal or an alternating signal having a frequency of greater than or equal to a certain frequency is input to the data line, so that the magnitude of the leakage current of each pixel TFT caused by the difference in polarity of the video signal with respect to the opposing electrode written to the pixel electrode is equalized, and the flickers are greatly reduced.

Abstract: A liquid crystal display device is configured to improve display quality by minimizing flickers and residual images through inversion. The inversion may include changing the polarity of the data voltages. A first liquid crystal cell may be charged with a potential difference between a first data voltage supplied to a first pixel electrode and a second data voltage supplied to an adjacent second pixel.

Abstract: A buffer circuit drives a capacitive load based on a voltage Vin. In a setup period, switches are in an ON state, and in a drive period, a switch is in an ON state. A voltage comparison unit compares the voltage Vin in the setup period and a voltage Vout in a drive period to output a comparison result voltage. A push-pull output unit includes a TFT for charge and a TFT for discharge. A drive control unit controls the TFTs to be in an OFF state in the setup period, and in the drive period, selectively controls the TFTs to be in an ON state in accordance with the comparison result voltage. If Vout<Vin, the comparison result voltage rises, the TFT becomes in an ON state, a voltage at a node falls, the TFT becomes in the ON state, and the voltage Vout rises. Thus, there is a provided a small-sized capacitive load drive circuit with low power consumption and robust against process variation.

Abstract: An overflow suppression technique that is effective for avoiding degradation in image quality is provided. A fundamental waveform and detail is extracted out of an input RGB signal. A suppression gain generation unit 614 generates a suppression gain from the extracted fundamental waveform. Multipliers 612a and 612b multiply the detail and the fundamental waveform by the generated suppression gain, respectively. Then, an adder 626 combines them together for a mixed output. Alternatively, equalization processing is performed as follows. A low frequency component fundamental waveform is obtained as a result of the passing of an input RGB signal through a low pass filter 622. A suppression gain is generated from the low frequency component fundamental waveform. Then, the input itself is multiplied by the suppression gain to obtain an output.

Abstract: A system and method to drive display matrix, comprising: a voltage level generator to provide predetermined voltages, a row voltage selector to select a group of voltages from the voltage level generator depending on select vector to drive row drivers, a column voltage selector to select a group of voltages from the voltage level generator depending on data vector to drive column drivers, and a controller to generate control signals to scan the display as dictated by addressing technique.

Abstract: A method for addressing a bistable nematic matrix LCD having two stable textures without any applied electric field. Pixel addressing is of the passive multiplex type. The method includes selecting the value of the electrical voltage applied between the substrates so that an average value of the voltage, preferably the average quadratic value, since the initial command for image display up to the time immediately preceding switching, has a predetermined value independent of the information to be displayed, which is the same for all the pixels of the image.

Abstract: A display system includes a display device, a driving circuit, a flexible printed circuit (FPC), a charge pump circuit and a control circuit. The driving circuit is disposed on the display device, for driving the display device. The FPC is externally coupled to the display device. The charge pump circuit is disposed on the FPC, for generating at least an output voltage to the driving circuit. The control circuit is disposed on the display device and coupled to the driving circuit, for generating a plurality of control signals to control the charge pump circuit. The charge pump circuit has a plurality of control ports coupled to the control circuit for receiving the control signals generated from the control circuit, respectively.

Abstract: A liquid crystal display and a method of driving the same are disclosed. The liquid crystal display includes a liquid crystal display panel including data lines and gate lines crossing each other and liquid crystal cells, a timing control signal generating unit, a data drive circuit supplying a data voltage to the data lines, and a gate drive circuit. The timing control signal generating unit generates a first gate timing control signal for controlling a scan direction of the liquid crystal display panel in a sequential direction and a second gate timing control signal for controlling the scan direction in a reverse sequential direction. The gate drive circuit supplies a gate pulse to the gate lines while a shift direction of the gate pulse changes in response to the first and second gate timing control signals.

Abstract: A device for driving a liquid crystal display device includes a liquid crystal panel having a plurality pixel regions formed thereon, a data driver to drive data lines on the liquid crystal panel, a gate driver to drive gate lines on the liquid crystal panel, a driving voltage generating unit to generate a common voltage wherein a level of the common voltage swings every frame, and a timing controller to control the driving voltage generating unit and the gate driver to generate a gate driving voltage wherein a level of the gate driving voltage varies in accordance with the common voltage swinging level.

Abstract: A liquid crystal display device includes a display portion having a first substrate, a second substrate opposing to the first substrate, a liquid crystal layer held between the first and second substrates, and a plurality of pixels arranged in a delta shape. A plurality of pixel electrodes are respectively connected to signal lines extending in a first direction via a switch. The switch is controlled by scanning lines extending in a second direction which orthogonally crosses the first direction. The signal lines extend in a space between the pixel electrodes in a meandering shape in the second direction, and two kinds of color pixels are connected with a common signal line in turn via the pixel switch.

Abstract: To suppress deterioration of quality of a still image displayed with a reduced refresh rate. A liquid crystal display device includes a display portion that is controlled by a driver circuit and includes normally white mode (or normally black mode) liquid crystals, and a timing controller for controlling the driver circuit. The timing controller is supplied with an image signal for displaying a moving image and an image signal for displaying a still image. The absolute value of a voltage applied to the liquid crystals in order to express black (or white) in an image corresponding to the image signal for displaying the still image is larger than that of a voltage applied to the liquid crystals in order to express black (or white) in an image corresponding to the image signal for displaying the moving image.

Abstract: An exemplary driving method of a display panel with half-source-driving structure is provided. The display panel includes at least one pixel each using a capacitor to store a voltage. A terminal of the capacitor is adapted to receive a display data inputted from a data line, and another terminal of the capacitor is electrically coupled to a common electrode. The driving method includes: obtaining a direct current power signal; coupling an alternating current signal with the direct current power signal to generate a common electrode driving signal; and applying the common electrode driving signal to the common electrode. A rising time of a rising edge and a falling time of a falling edge of the common electrode driving signal are modified to improve a V-line mura phenomenon of the display panel.

Abstract: A field-sequential display is operated in one of a color mode or a grayscale mode. In the color mode, a video source provides image content in the form of multiple-color image data having a frame rate of X Hz and a display controller uses the multiple-color image data to drive the field-sequential display so as provide multiple-color image content at the field-sequential display. In the grayscale mode, the display controller generates grayscale image data from the multiple-color image data and the display controller then drives the field-sequential display with the grayscale image data at a lower frame rate of Y Hz. While in the grayscale mode, the display controller can take advantage of the enhanced contrast provided by the grayscale image content to reduce or disable backlighting at the field-sequential display. The reduced timing requirements afforded by the lower frame rate, as well as the reduction or elimination of backlighting, can reduce power consumption compared to the color mode.

Abstract: In one embodiment of the present invention, when a still image is displayed, applied voltages respectively corresponding to a total of n (n being an integer of not less than 4) types of gradation 0 to (n?1) are outputted to pixels. When a moving image is displayed, an applied voltage corresponding to a predetermined gradation m (1?m?(n?2)) is applied to the pixels instead of applied voltages respectively corresponding to gradations of less than the predetermined gradation m. Overdrive driving is performed with respect to a total of n types of gradation.

Abstract: A liquid crystal display device and driving method therefor are disclosed. The device includes a plurality of signal lines that apply different gray scale voltages to each of the pixels. A driving circuit is provided to generate the gray scale voltages to be applied to the pixels. In operation, the driving circuit applies the first gray scale voltage at intervals of the horizontal scanning time within a display period. The second gray scale voltage is output by a number of times that is not smaller than twice and not greater than (M-N) times at intervals of the horizontal scanning time from the beginning of the vertical retrace interval. The second gray scale voltage is then stopped until completion of the vertical retrace interval.

Abstract: An organic light emitting display device is disclosed. The device has a drive circuit which generates a reference clock to be used for synchronizing data signals supplied to the pixels. The reference clock is based on the frame frequency. As a result, the display will provide images of consistent quality which do not vary with input data frequency.

Abstract: In one embodiment of the present invention, a gate driver creates a dummy insertion period in which the driver does not apply a gate on pulse to a scanning signal line immediately after the time of the inversion of a data signal. When a period from the time of the application of the gate on pulse to an odd numbered or even numbered scanning signal line to which the gate on pulse is applied previously to the time of the application of the gate on pulse to an even numbered or odd numbered scanning signal line to which the gate on pulse is applied later is set as an adjacent line writing time lag period for two scanning signal lines adjacent to each other, a CS control circuit allows the polarity of every CS signal to be reversed on the same cycle at least in the adjacent line writing time lag period.

Abstract: A liquid crystal display is disclosed. The liquid crystal display includes a liquid crystal display panel on which a plurality of data lines and a plurality of gate lines are positioned to cross one another and a plurality of liquid crystal cells driven according to a voltage difference between a data voltage and a common voltage are positioned in a matrix format, a side printed circuit board (PCB) connected to the side of the liquid crystal display panel, and a DC to DC converter that is mounted on the side PCB to produce a driving voltage of the liquid crystal display panel.

Abstract: An exemplary liquid crystal display (200) includes a liquid crystal panel (201) having a plurality of pixel units (240), a scanning circuit (202) configured to activate the pixel units, a data circuit (203) configured to provide data voltage signals the pixel unit via a plurality of data lines (220), and a common voltage circuit (205) configured to generate a common voltage signal. Each pixel unit includes a pixel electrode (242), a common electrode (243), and a coupling member (245). The coupling member is connected between the pixel electrode and a corresponding one of the data lines, and is configured to transfer an electrical potential shift of the corresponding common electrode to the corresponding data line when one of the data voltage signals is applied to the pixel electrode. The common voltage circuit is configured to compensate the common voltage signal according to a feedback signal obtained from the data lines.

Abstract: A PLL as a clock generation circuit that generates a PWM clock based on a reference clock, which PWM clock is used for controlling, in a pulse width modulation method, a lamp on time and a lamp off time of a light source illuminating a liquid crystal panel by synchronizing with a video signal that performs display in a set period on the liquid crystal panel, includes a configuration that generates a PWM clock that can maintain a fixed ratio of the lamp on time to the lamp off time within one period even if the set period is changed, by changing a pulse interval of the reference clock in conjunction with the change in the set period.

Abstract: The present invention relates to a circuit for driving a liquid crystal display device in which no multi-flicker preventive signal FLK, but only single flicker preventive signal FLK, is used for reducing numbers of pins of a timing controller and a level shifter.

Abstract: A method of the present invention, for driving a liquid crystal display device includes the step of applying, when spray-bend transition of liquid crystal molecules is completed, a constant voltage to a storage capacitor electrode so that an electric potential difference between a pixel electrode and a common electrode becomes greater than an electric potential difference between the pixel electrode and another pixel electrode adjacent to said pixel electrode when application of a voltage for the spray-bend transition of the liquid crystal molecules is stopped.

Abstract: A method and system for determining the Vcom for a liquid crystal display by using a light diffusing unit.

Abstract: A liquid crystal light modulator 11 modulates a light according to an effective value of a supplied drive signal. A driving apparatus 21 changes the effective value of each frame of the drive signal supplied to the liquid crystal light modulator 11 according to modulation data. The driving apparatus 21 generates the drive signal containing plural pulses in each frame. The driving apparatus 21 supplies the generated drive signal to the liquid crystal light modulator 11, thereby enabling a high-frequency drive of the liquid crystal light modulator 11.

Abstract: A display panel and its gate driving circuit are provided. The gate driving circuit includes a plurality of shift registers. Each of the shift registers includes a first scan signal generator for generating a first scan signal, a second scan signal generator for generating a second scan signal, a first control unit for generating a first control signal, and a second control unit for generating a second control signal. Here, the first control signal and the second control signal are shared by the first scan signal generator and the second scan signal generator. Based on the above, the abatement of signal intensity of the first scan signal and the second scan signal caused by circuit sharing can be precluded, and a chip area occupied by each of the shift registers can be reduced.

Abstract: Disclosed are a display device and a method of driving the same that improve both moving image visibility and lateral visibility. A display panel including gate and data lines arranged in the form of a matrix for displaying an image, a gate driver for driving the gate line, and a data driver for supplying a low gray scale image signal, a high gray scale image signal, and a black impulsive signal to the data line within one frame period.

Abstract: In one embodiment of the present invention, a liquid crystal display device is disclosed in which a gate driver applies a gate-on pulse so that a second period is longer than a first period. The first period and the second period are defined as follows. Among gate-on pulses applied before the moment of polarity inversion of a data signal, the last end of the gate-on pulse nearest to the moment of the polarity inversion is earlier than the end time of the horizontal period during which the gate-on pulse is applied. The first period starts at the last end of the gate-on pulse and ends at the end time of the horizontal period during which the gate-on pulse is applied. The second period starts at the moment of the polarity inversion and ends at the moment of the application start of the gate-on pulse nearest to the moment of the polarity inversion among the gate-on pulses applied after the polarity inversion.

Abstract: In a stereoscopic display apparatus having optical directory elements (21) such as lenticular elements an overdrive voltage, e.g. obtained by introducing a resonant impedance (22) in one of the switching states, enhances switching speed between the 2D and the 3D state.

Abstract: A liquid crystal display device includes a display section, an image signal drive circuit, a scan signal drive circuit, a common electrode potential control circuit, and a synchronous circuit. The display section has scan electrodes, image signal electrodes, a plurality of pixel electrodes arranged in a matrix, a plurality of switching elements for transmitting an image signal to the pixel electrodes, and a common electrode. The common electrode potential control circuit changes an electric potential of the common electrode into a pulse shape, after the scan signal drive circuit has scanned all the scan electrodes and the image signal has been transmitted to the pixel electrodes. Otherwise, the image signal is overdriven. Otherwise, torque for returning to a no-voltage-application state is increased.

Abstract: During first period, TFTs: and are set in ON and OFF states, respectively. Potential Va is fed into a source line Sj so that potential of pixel electrode is Va. During second period, the TFTs: and are set in the OFF and ON states, respectively. The potential Va is continuously fed into the source line Sj. This sets potential of node to Va, thereby changing the potential of the pixel electrode. During third period, the TFTs: and are set in the OFF state. This realizes a display device where high cost factors and power consumption increase are suppressed, and the effective value of voltage expressed by difference between potential applied to a driving potential input terminal and reference potential can have variance larger than amplitude of signal voltage fed into a data signal line, the variance corresponding to variation in the signal voltage.

Abstract: A timing controller of an LCD panel is provided. The timing controller, for controlling a plurality of source drivers and a plurality of gate drivers of the LCD panel, includes a data processing module for generating a data signal carrying image data and black data, and a control signal generating module for generating a plurality of horizontal start signals, a first gate enable signal and a second gate enable signal. The horizontal start signals are for controlling the inputting of the data signals into the source drivers. The first and second gate enable signals correspond to different enable timings, and are selectively outputted to the gate drivers.

Abstract: A liquid crystal display having adaptive pulse shaping control mechanism includes a first gate driver for providing a first gate signal based on a first modulation voltage, a second gate driver for providing a second gate signal based on a second modulation voltage, a first pixel array unit for illustrating image according to the first gate signal, a second pixel array unit for illustrating image according to the second gate signal, a timing controller for performing a pulse compare operation over the first and second gate signals so as to generate a first shaping control signal and a second shaping control signal, a first gate pulse modulation unit for providing the first modulation voltage according to the first shaping control signal, and a second gate pulse modulation unit for providing the second modulation voltage according to the second shaping control signal.

Abstract: A method is arranged to process a frame for an LCD with a modified polarity pattern. The pattern employs a polarity reversal scheme that results in line inversion and/or dot inversion patterns that are observable by pixel locations within the frame. The drive polarity for the column drivers in the LCD is toggled according to the modified polarity pattern. The scanning sequence for each row on the display is modified for cooperation with the pattern. A first subframe is scanned during a first interval while applying a first set of drive polarities. A second subframe is scanned during a second interval that is non-overlapping with the first time interval. The application of the method enables the column drivers in the LCD to operate with reduced power while retaining the benefits of line and dot inversion techniques.

Abstract: An exemplary liquid crystal display (1) includes a first substrate assembly (11), a second substrate assembly (12) parallel to the first substrate assembly (11), a liquid crystal layer (13) sandwiched between the first substrate assembly and the second substrate assembly, and a discharging circuit (120). The first substrate assembly includes common electrodes (110) formed thereat. The common electrodes are parallel to each other. The second substrate assembly includes scanning lines (1211) that are parallel to each other and that each extends along a first direction, and signal lines (1212) that are parallel to each other and that each extends along a second direction orthogonal to the first direction. The discharging circuit is electrically connected with the common electrodes.

Abstract: A liquid crystal display having data driving apparatus comprising first and second output switches, a charge sharing line, and first and second charge sharing switches. The first output switch switches an electrical connection between a first amplifier providing a positive gradation voltage and a first data line in response to a control signal. The second output switch switches an electrical connection between a second amplifier providing a negative gradation voltage and a second data line in response to the control signal. The first charge sharing switch switches an electrical connection between the first data line and the charge sharing line in response to the control signal. The second charge sharing switch switches an electrical connection between the second data line and the charge sharing line in response to the control signal.

Abstract: A method for detecting line broken faults of common electrode lines of liquid crystal display comprising: loading detection picture to the liquid crystal display, wherein said detection picture comprises at least one detection picture for line broken of common electrode lines, wherein, in the detection picture of same frame, the voltage difference of storage capacitor corresponding to pixel electrode with one polarity is larger than voltage difference of a storage capacitor corresponding to pixel electrode with another polarity; when the detection picture for line broken of common electrode line is displayed on the liquid crystal display, detecting whether there is black line or white line gradually changed in horizontal direction in said detection picture for line broken of common electrode line, and determining line broken fault of common electrode line exists in the liquid crystal display when there is a black line or white line gradually changed in horizontal direction.

Abstract: Methods and devices employing circuitry for display turn-off that offsets the effect of kickback voltage are provided. In one example, a method may include determining an amount of kickback voltage that is expected to occur in pixels of the electronic display during shutdown of the display, supplying a common voltage output to a common electrode of a pixel of the electronic display, and supplying an activation signal to the pixel to activate the pixel. The method may also include supplying a data signal to a pixel electrode of the pixel. The data signal may be substantially equal to the sum of the common voltage output and the determined kickback voltage. The method may include removing the activation signal from the pixel to store the data signal in the pixel to reduce the effect of kickback voltage on the pixel electrode of the pixel during shutdown of the electronic display.

Abstract: Disclosed herein are a display, a source driver of the display and a method for driving the same. The source driver includes a determining unit. The determining unit is configured to temporarily store data in response to a latch enable signal, to output a plurality of digital data values continuous in time sequence, and to sequentially convert a first digital data value and a second digital data value of the digital data values to a first analog signal and a second analog signal, respectively, and to compare the first digital data value with the second digital data value. When the first digital data value and the second digital data value are the same, the determining unit continuously outputs the first analog signal and the second analog signal.

Abstract: A pixel in a liquid crystal display panel comprises a first sub-pixel area having a first sub-pixel electrode and a second sub-pixel area having a second sub-pixel electrode. Each sub-pixel electrode is associated with a capacitor. When a gate-line signal and a data voltage is provided to the pixel, the voltage level on the first sub-pixel electrode is substantially equal to or slightly higher than the voltage level on the second sub-pixel electrode and the capacitor associated with each sub-pixel electrode is charged. When the gate-line signal has entirely passed on partially passed, a circuit element causes the capacitor associated with the second sub-pixel electrode to transfer its charge to another capacitor, resulting in a reduction of the voltage level on the second sub-pixel electrode.

Abstract: In a display device having a plurality of scan signal line driving circuits, its display quality is improved. The display device comprises a plurality of scan signal lines, a plurality of image signal lines, and a plurality of scan signal line driving circuits for generating scan signals for driving the scan signal lines. Each of the scan signal line driving circuit internally generates a driving signal having the waveform of such potential variation that the potential decreases with a slope from a high potential to an intermediate potential between the high potential and a low potential. Each of the scan signal line driving circuits further includes a signal wiring for connecting the scan signal line driving circuits to one another and applying the driving signal.

Abstract: A driving apparatus, a system and a method thereof is provided by the present invention. The driving apparatus has at least an output terminal and includes a driving circuit and a control switch. The control switch is electrically coupled with the driving circuit. The driving circuit receives an input signal and converts the input signal into an analog driving signal. The control switch is controlled by a control signal. When the control switch is turned on, the analog driving signal is able to be sent to the output terminal of the driving apparatus. The control signal further controls the spike current generated as turning on the control switch so as to reduce the spike current. The driving apparatus can be applied to an LCD system, so that the panel and the chips of the LCD system have longer life time, lower electricity consumption and better heat dissipation performance.

Abstract: A display device comprises a display panel in which data lines and gate lines cross each other, a timing controller which outputs a single gate pulse modulation control signal (“FLK signal”) and I-phase (where I is an integer equal to or more than 2) gate shift clocks which are sequentially delayed, an FLK dividing circuit which divides the single FLK signal to output J (where J is an integer equal to or more than 2 and smaller than I) FLK signals, a data driving circuit which converts digital video data into data voltages to supply the data voltages for the data lines, and a gate driving circuit which generates gate pulses by level-shifting voltages of the gate shift clocks, to modulate falling edge voltages of the gate pulses in response to the divided FLK signals, and to sequentially supply the modulated gate pulses for the gate lines.

Abstract: A digital-to-analog converter circuit is configured to convert an m-bit digital signal into an analog signal. The circuit includes a bit voltage generator convert each bit of segmented n-bit units of the digital signal into a first voltage or a second voltage, first capacitors each configured to store the voltage for each bit output from the bit voltage generator, switches connected to the first capacitors, a second capacitor connected to the switches, an output unit configured to output the voltage stored in the second capacitor as an analog signal, and a control unit configured to control the switches, connect in parallel the first capacitors with the second capacitor, and adjust the voltage stored in the second capacitor.