Abstract: The present invention discloses a gate driver circuit. The gate driver circuit includes a plurality of driving units electrically connected in series, wherein the gate driver circuit receives a plurality of frequency signals and the driving units transmit a plurality of output signals sequentially. Furthermore, each driving unit includes a primary circuit, a first voltage regulator circuit and a second voltage regulator circuit.

Abstract: A device for reducing flickers of a liquid crystal display panel is disclosed. The liquid crystal display panel is divided into a plurality of blocks. The device includes a memory, a common voltage generation unit, and a controller. The memory is used for storing a plurality of initial codes. Each initial code corresponds to a block of the plurality of blocks and a common voltage. The controller is used for generating a control signal to the common voltage generation unit when the controller starts to count scan start signals corresponding to the block. The common voltage generation unit is used for reading the initial code from the memory according to the control signal, and generating the common voltage to the block according to the initial code.

Abstract: A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

Abstract: The present disclosure provides a display panel driving apparatus for driving a display panel including a plurality of display cells, in accordance with an inputted image signal, including, a first latch section that successively reads and holds a pixel data piece for each pixel based on the inputted image signal, a second latch section that successively reads and outputs pixel data pieces every Q pieces (Q is an integer equal to or larger than 2) with a predetermined time difference therebetween in accordance with a load signal, a drive potential generating section that generates a drive potential to drive each of the display cells based on the outputted pixel data pieces, and an output gate section that applies the drive potentials to the respective display cells of the display panel, simultaneously after an elapse of a predetermined time period from a timing of supplying the load signal.

Abstract: Disclosed are a display driving circuit and a display device. The display driving circuit includes an output buffer unit that outputs a pair of pixel signals, an output switch unit that directly transfers the pair of pixel signals to a pair of output lines or transfers the pair of pixel signals to the pair of output lines such that the pair of pixel signals cross each other in correspondence with repetitive panel charging/discharging periods, and a charge sharing switch unit that controls charge sharing of the pair of output lines in correspondence with a charge sharing period between the panel charging/discharging periods, and provides a variable connection resistance value for the charge sharing. Consequently, power consumption and heat generation of the display driving circuit are reduced.

Abstract: A display apparatus, an integrated circuit and method thereof are disclosed. The display apparatus includes a frame buffer, a controller circuit, and a display driver circuit. The frame buffer is configured to retain a plurality of image frames to be displayed. The controller circuit, coupled to the frame buffer, is configured to determine whether a change in the image frames has occurred and whether a refresh time is expired. The display driver circuit, operatively coupled to the frame buffer and adapted to couple to an active display device, is configured to receive the image frames to be displayed from the frame buffer and dynamically refreshing the active display device when the change is determined or when a refresh time is expired.

Abstract: A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage-capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage-capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction; and with the control unit, buffer transistors for outputting a pulse signal for sampling to an input video signal to each signal line are arrayed in a column in the longitudinal direction of the laser beam irradiation.

Abstract: In a liquid crystal display device, amplitude voltage of an image signal written into a signal line can be decreased. A liquid crystal display device in which frame inversion driving is performed includes pixels each including a liquid crystal element and a transistor that controls voltage applied to a first electrode of the liquid crystal element. A scan line is electrically connected to gates of transistors in pixels in a corresponding row. A common line is electrically connected to second electrodes of liquid crystal elements in pixels in the corresponding row. In a first frame period, a first potential is sequentially supplied to the common lines in synchronization with sequential selection of the scan lines. In a second frame period adjacent to the first frame period, a second potential different from the first potential is sequentially supplied to the common lines in synchronization with sequential selection of the scan lines.

Abstract: The embodiment of the present invention discloses a shift register for reducing the power consumption during driving. The shift register includes a protection circuit, a retaining circuit, an output circuit, a first driving circuit, a second driving circuit, a resetting circuit, a timing control terminal, a first power supply terminal, a second power supply terminal, a third power supply terminal and a fourth power supply terminal. The embodiment of the present invention further discloses a Gate driver On Array (GOA) panel and a method for gate driving.

Abstract: A driving method for a Liquid Crystal Display (LCD) device is used for reducing power consumption of the LCD device. The driving method includes determining a driving approach of the LCD device, and performing corresponding charge sharing on a plurality of data channels according to the driving approach. The driving approach of the LCD device is determined according to a latch data (LD) signal and a polarity signal.

Abstract: A driving device comprises: a first driver driven by a first input signal and generating a first interim output signal controlled by a first clock signal; a second driver driven by a second input signal and generating a second interim output signal controlled by a second clock signal; and a plurality of shift registers including a buffer driven by the first interim output signal and the second interim output signal and generating an output signal controllable by the first clock signal and the second clock signal. The buffer includes a second transistor connected to a gate electrode of a first transistor for transmitting a voltage with a first level with the output signal and transmitting a voltage with a second level for turning off the first transistor.

Abstract: A multi-primary color display device is capable of handling an increased number of primary colors for color image display with a reduced number of external parts, with reduced increase in the amount of drive circuit and reduced increase in operating speed. An active matrix liquid crystal panel includes a display section constituted by pixel formation portions, each made of four sub pixel-formation portions which handle four primary colors. These four sub pixel-formation portions are arranged in a 2×2 matrix pattern. With such a pixel configuration, a source driver drives as many as M source lines, which is two times the number M of pixels arranged in a horizontal direction. A gate driver is formed on the liquid crystal panel integrally with pixel circuit in the display section, and drives as many as N gate lines, which is two times the number N of the pixels arranged in a vertical direction.

Abstract: A display device includes: a transmission-type display member having a display area that is sequentially scanned; and an illumination member that is arranged on a rear face of the display member and includes a plurality of illumination units that are arranged so as to be aligned in a direction from one end portion side toward the other end portion side along a direction in which the display area is sequentially scanned. The illumination unit is in a light emitting state over a predetermined light emitting period after sequential scanning of display units formed from a portion of the display area, which corresponds to the illumination unit, is completed, and the illumination units are sequentially scanned from one end portion side to the other end portion side in accordance with the sequential scanning of the display area.

Abstract: A scan driving device including scan driving blocks including a first node receiving a second-voltage according to a signal input to a first-input terminal, a second node receiving a first-voltage according to a signal input to the first-input terminal, and receiving an input signal according to a clock signal input to a second-input terminal, a first transistor connected to the first node, the first power source, and an output terminal, and a second transistor connected to the second node and the output terminal and configured to receive a clock signal input to a third-input terminal, wherein, during the initial driving period, the input signal is applied with a gate-off-voltage, and clock signals input to the first-, second-, and third-input terminals are applied with a gate-on-voltage to reset a voltage at the first node with the gate-on-voltage and reset a voltage at the second node with the gate-off-voltage.

Abstract: A gate driver includes a gate integrated circuit (“IC”) chip which receives at least two scanning start signals and at least four clock control signals, and outputs a plurality of gate-on voltages, where at least two clock control signals of the at least four clock control signals are generated based on one scanning start signal of the at least two scanning start signals, timings of the at least two scanning start signals are independent of each other, and timings of the at least two clock control signals based on the one scanning start signal are independent of each other.

Abstract: A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

Abstract: According to one embodiment, a liquid crystal display apparatus includes a display panel on which a plurality of liquid crystal pixels are arrayed in a matrix, a lighting module arranged to be opposed to the display panel and configured to illuminate the display panel, and a control module configured to control image display on the display panel and luminance of a light source of the lighting module, the control module rewriting an image signal to the liquid crystal pixels by intermittent driving and controlling the luminance of the light source to be proportional to a reciprocal of transmittance of the display panel.

Abstract: A data driver includes a holding latch unit including a plurality of holding latches that store data, a signal generator including a plurality of digital-analog converters (DAC) for receiving the data to generate data signals, and a switching unit coupled between the signal generator and data lines to couple the plurality of DACs to the data lines or to commonly couple one of the plurality of DACs to the data lines.

Abstract: A display device includes a plurality of gate lines, a plurality of data lines, a gate circuit, a driver, and a data selector circuit that includes a plurality of switch groups each of which has a time division switch and a timing adjustment switch that are connected in parallel. The data selector circuit outputs output signals from the driver, which have different polarities every one or more data lines of the plurality of data lines, to the respective data lines. Each of the time division switches and the timing adjustment switches is an NMOS transistor. The driver turns on the timing adjustment switches connected to the data lines to which positive output signals are output from the driver, earlier than the time division switches connected to the data lines to which negative output signals are output from the driver, by a predetermined period.

Abstract: It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed.

Abstract: Aspects of the present invention relate to methods and systems for controlling power consumption with a power controlling display device. Some aspects relate to a power controlling display device that receives a notification of a power control event that may control internal display components as well as connected power consuming devices. Some aspects relate to methods and systems for automatically compensating a displayed image when display backlight levels are modified in response to a power control event.

Abstract: A pixel circuit includes a plurality of pixels. Each pixel includes a data storage capacitor to store a voltage for controlling a gray scale value based on an input data signal, a plurality of switch transistors connected in series between a data signal line and the data storage capacitor, and a plurality of connection transistors coupled to the pixels. The switch transistors have a gate electrode connected to a first gate control signal line. At least one connection transistor is connected between at least one node between the switch transistors of a first pixel and at least one node between the switch transistors of a second pixel adjacent to the first pixel. The at least one connection transistor includes a gate electrode connected to a second gate control signal line.

Abstract: The present disclosure generally relates to gamma bus wiring techniques that saves space in a display such as a liquid crystal display. In certain embodiments, a voltage offset associated with gamma bus amplifiers configured to provide analog voltage levels to a pixel may reduce at least some of the visual performance characteristics of the attached display when it transitions between different voltage values provided by different gamma bus amplifiers. The voltage offsets associated with the gamma bus amplifiers may be distributed between multiplexers that are coupled to gamma bus amplifiers by interlacing the wires routed from a resistor string to the multiplexers.

Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.

Abstract: A liquid crystal display (LCD) apparatus includes: multiple differential amplifier stages each of which is operable to generate, according to a bias current and an input voltage, an output voltage having a magnitude and a slew rate that correspond respectively to the input voltage and a magnitude of the bias current, and serving as a data voltage of a corresponding pixel unit of an LCD panel; multiple current sources controllable to generate and provide a plurality of the bias currents to the differential amplifier stages, respectively; and a bias voltage generating unit connected electrically to the current sources in a current mirror configuration for generating an input bias current and controlling the current sources to generate the bias currents according to a latch pulse signal. The slew rate of the output voltage corresponds to a logic state of the input bias current.

Abstract: A driving circuit for driving a display panel includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Abstract: A liquid crystal display device with low power consumption is provided by using a driver circuit and a pixel that have novel circuit structures. In a liquid crystal display device using n (n is a natural number and satisfies n?2) bit digital video signals to display an image, n×m (m is a natural number) memory circuits and n×k (k is a natural number) non-volatile memory circuits are provided in each pixel, thereby giving the device a function of storing m frames of digital video signals in the memory circuits and a function of storing k frames of digital video signals in the non-volatile memory circuits. Once stored in the memory circuits, the digital video signals are repeatedly read out for every new frame to display a still image, so that driving of a source signal line driver circuit can be stopped during still image display.

Abstract: The invention provides a backlight driving circuit, an LCD device, and a manufacturing method thereof. The backlight driving circuit includes at least two LED lightbars arranged in parallel connection, the output end of each of the LED lightbars is coupled with a variable current circuit, and the variable current circuit is provided with adjustable variable resistors used for balancing the voltage difference between the LED lightbars. In the invention, because the adjustable variable resistors are arranged in the variable current circuit which is connected in series with the LED lightbars, the resistance of the adjustable variable resistors can be adjusted according to the resistance of different LED lightbars before being used; thus, the total voltage of each LED lightbar and the variable resistor connected with ed LED lightbars in series can keep consistent.

Abstract: Provided are a display driving circuit, a display device and a driving method thereof, which are capable of avoiding an influence of a feed through effect on a voltage difference between a pixel electrode and a common electrode and thus improving the quality of a displayed picture. The display driving circuit comprises a gate driving unit for controlling a thin film transistor TFT to be turned on, a source driving unit for outputting a signal to a source of the TFT, and a circuit unit for supplying a power to a common electrode, the circuit unit outputs a first voltage to the common electrode when the TFT is in a turn-on state, and the circuit unit outputs a second voltage to the common electrode when the TFT is in a turn-off state, wherein the first voltage is a voltage different from the second voltage.

Abstract: A field-sequential display is operated in one of a color mode or a grayscale mode. In the color mode, a video source provides image content in the form of multiple-color image data having a frame rate of X Hz and a display controller uses the multiple-color image data to drive the field-sequential display so as provide multiple-color image content at the field-sequential display. In the grayscale mode, the display controller generates grayscale image data from the multiple-color image data and the display controller then drives the field-sequential display with the grayscale image data at a lower frame rate of Y Hz. While in the grayscale mode, the display controller can take advantage of the enhanced contrast provided by the grayscale image content to reduce or disable backlighting at the field-sequential display. The reduced timing requirements afforded by the lower frame rate, as well as the reduction or elimination of backlighting, can reduce power consumption compared to the color mode.

Abstract: A display driving system using single level data transmission with embedded clock signals. The display driving system is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words.

Abstract: A display device includes a display section displaying an image; and a barrier section including a plurality of liquid crystal barriers, the liquid crystal barriers each being configured to be switched between an open state and a closed state. The barrier section includes a barrier electrode being arranged in a region corresponding to the liquid crystal barrier, the barrier electrode including a plurality of sub-electrodes each of which includes a projection portion, a common electrode being commonly formed on an entire surface of a region corresponding to the plurality of liquid crystal barriers, and a liquid crystal layer being provided between the barrier electrode and the common electrode.

Abstract: An imaging device includes a pixel section and an amplification unit which amplifies the signal of the pixel section. The amplification unit includes an input capacitor having first and second nodes, an amplification circuit, a first feedback capacitor connected between the input capacitor and an output portion of the amplification circuit, a first MOS transistor switch connected in series with the first feedback capacitor, a second MOS transistor switch which is connected in series with the first feedback capacitor, and has a drain and a source connected to each other, a second feedback capacitor connected between the input capacitor and the output portion, a third MOS transistor switch connected in series with the second feedback capacitor, and a fourth MOS transistor switch which is connected in series with the second feedback capacitor, and has a drain and a source connected to each other.

Abstract: A buffer circuit includes a first transistor circuit having a first conductivity type transistor, a second transistor circuit having a second conductivity type transistors, in which the first and second transistor circuits are serially connected between a first fixed power supply and a second fixed power supply, and input terminals and output terminals of each of the first and second transistor circuits are connected in common respectively, in which at least one transistor circuit of the first transistor circuit and the second transistor circuit is a double gate transistor, and in which wherein a switch element, when any one transistor circuit of the first and the second transistor circuits is in an operating state, is included to supply a voltage of a third fixed power supply to a common connection node of the double gate transistor of the other transistor circuit.

Abstract: A display apparatus disclosed herein includes a plurality of pixel circuits, each having a plurality of switches configured to receive a driving signal of a predetermined period and to be controlled for opening and closing operation by the driving signal, a drive circuit configured to control the open/closed state of the switches, being operable to scan the pixel circuits and open and close the switches in periods independent of each other.

Abstract: A display apparatus includes a display panel including pixels, a gate driver to sequentially apply a gate signal to gate lines in response to a gate control signal, a first source driver to apply a first data voltage to data lines in response to a data control signal, and a second source driver disposed at an opposite side of the display panel from the first source driver with respect to the display panel. The second source driver is configured to apply a second data voltage to the data lines at every time period, at which the gate signal is applied to the gate lines, in response to the clock signal. The pixels display a gray scale in response to the first and second data voltages, and a time period of a rising edge of the clock signal is the same as a time period of a rising edge of the gate signal. In addition, the high level period of the clock signal is shorter than the high level period of the gate signal.

Abstract: A level shifter for a source driver of a liquid crystal display is provided. The level shifter includes: an input stage for generating a signal with a voltage of between a positive input source voltage and a negative input source voltage according to an input logic; a middle stage for generating a first logic signal and a second logic signal according to the signal; and an output stage, for generating a first output signal with a voltage of between a first positive output source voltage and a first negative output source voltage at a first output terminal or a second output signal with a voltage of between a second positive output source voltage and a second negative output source voltage at a second output terminal according to the first logic signal and the second logic signal.

Abstract: A bidirectional switch includes a pair of transistors, with each transistor including a source connected via a degeneration resistance to a common source control node, a gate connected to a common gate control node, a drain connected to a respective channel or gate line and to a charge storage node, respectively, and a clamp diode connected between the source and the gate. This forms a single charge transfer path between gate lines sequentially activated by a scan driver of an LCD panel, and implements a charge sharing technique for reducing power dissipation.

Abstract: A gate shift register and a display device using the same are disclosed. The gate shift register includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output a scan pulse. A k-th stage of the plurality of stages includes a scan direction controller for converting a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller for controlling charging and discharge operations of each of Q1, Q2, QB1, and QB2 nodes, a floating prevention unit for applying a low potential voltage to a gate electrode of a discharge TFT based on a voltage of the QB1 node or the QB2 node, and an output unit for outputting first and second scan pulses.

Abstract: A liquid crystal display device and a driving method thereof capable of simplifying of a hardware construction of the liquid crystal display device driven by the impulsive driving method and minimizing capacitance of memory for storing data are provided.

Abstract: To control the state of an input signal and output signal of a sequential circuit in order to prevent a malfunction of an electronic circuit. An electronic circuit includes a sequential circuit and a control circuit. A first signal, a second signal, and a third signal are input to the sequential circuit as a start signal, a clock signal, and a reset signal, respectively. The sequential circuit outputs, as an output signal, a fourth signal whose state is set in accordance with the state of the inputted first signal, second signal, and third signal. The control circuit controls the state of the third signal input to the sequential circuit.

Abstract: A display apparatus includes a first display panel with a plurality of first pixels, a second display panel facing the first display panel and having a plurality of second pixels, a light reflective polarizer, and a backlight unit. The light reflective polarizer is interposed between the first and second display panels to transmit light polarized in a first direction, and reflect light polarized in a second direction substantially perpendicular to the first direction. The backlight unit is arranged proximate to the second display panel to supply light to the first and second display panels. The first display panel displays an image by using reflected ambient light, and the second display panel displays an image by using light from the backlight unit.

Abstract: A liquid crystal display (LCD) panel is provided. The LCD panel includes a plurality of pixel units each having a storage capacitor, a plurality of scan lines coupled to the pixel units, and a plurality of storage capacitor charge transistors each respectively coupled to the storage capacitors of the corresponding pixel units and further coupled to two of the scan lines. The storage capacitor charge transistors are used for charging the storage capacitors of the pixel units.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: In a bi-directional shift register and a liquid crystal display device having the bi-directional shift register, the shift register further includes a dummy stage for resetting a last stage. The dummy stage is reset by a control signal of the last stage or by the output signal of the dummy stage. Therefore, power consumption and layout area may be reduced. The shift register includes a plurality of stages and two dummy stages, and two selection signals for selecting shift direction is applied to each of the stages.

Abstract: A stacked display (20b) comprises superposed regions for changing between a reflective color state (R, G, B) and a transparent state, which regions form part of a˜bended substrate (20). The substrate (20) may comprise a sequence of portions (1-6) which forms regions having pre-defined color. Each portion (1-6) is electrically connected to a further portion in the sequence by interconnect regions (b?, c?, d?) which form an oversized loop between the regions (1-2, 3-4, 5-6) when the substrate (20) is bent. The regions (1-2, 3-4, 5-6) are filled with a suitable optoelectronic color material (R, G, B).

Abstract: A display device having a pixel section including a plurality of pixel circuits arrayed in a matrix, a plurality of scan lines, a plurality of capacity lines, a plurality of signal lines, a drive circuit, and a generation circuit generating a small amplitude common voltage signal switching in level at a predetermined cycle, wherein each pixel circuit arranged at the pixel section contains a display element having a first pixel electrode and a second pixel electrode and a storage capacitor having a first electrode and a second electrode, the first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected, the second electrode of the storage capacitor is connected to the capacity lines arrayed in a corresponding row, and the common voltage signal is applied in a second pixel electrode of the display element.

Abstract: A driving apparatus applied in a liquid crystal display are disclosed. Its first channel includes a first latching module, a first level-shifting module, a P-type digital/analog converting module, a first R2R module, and a P-type amplifying module, the second channel includes a second latching module, a second level-shifting module, a N-type digital/analog converting module, a second R2R module, and a N-type amplifying module. The P-type digital/analog converting module and N-type digital/analog converting module are selectively coupled to the first R2R module or the second R2R module. The first latching module receives a first digital signal and the first latching module outputs a first analog signal corresponding to the first digital signal. The second latching module receives a second digital signal and the second latching module outputs a second analog signal corresponding to the second digital signal.

Abstract: A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.

Abstract: A liquid crystal display device and a driving method thereof capable of reducing flicker are provided. During a predetermined time period, two continuous inversion operations to pixel voltages and common voltages are repeatedly performed with a timing interval in which the liquid crystal component does not react to changes. After the predetermined time period, the pixel voltages and common voltages are performed by a single inversion operation such that they are phase inverted. Then, the pixel voltages and common voltages are repeatedly performed during the predetermined period by two continuous inversion operations with the timing interval in which the liquid crystal component does not react to changes.