Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain.

Abstract: A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding resistors. Each clock signal line extends from the circuit board to a non-display area of the display panel. The plurality of grounding resistors are disposed on the circuit board. Each grounding resistor is connected to a corresponding clock signal line, and is configured to reduce a voltage value of high level of the clock signal.

Abstract: A display apparatus includes a display panel including data lines, first to nth data driver integrated circuits (ICs) (n being a natural number greater than 1) supplying data voltages to the data lines, a controller controlling the first to nth data driver ICs, and a power supply supplying power to the first to nth data driver ICs, the first data driver IC includes a lock signal switching unit receiving or blocking a lock signal from the power supply, a pull-up resistor is provided between the second data driver IC and a lock signal line to which the lock signal is supplied from the power supply, and the lock signal supplied to the first data driver IC or the second data driver IC is transferred to the controller through the first to nth data driver ICs.

Abstract: The present application provides a display device driving control circuit assembly and a display device. In the present application, a frequency of the first timing control clock of the first timing controller and a frequency of the second timing control clock of the second timing controller are different, as a result, a radiation intensity generated by the first timing controller and the second timing controller during operation is greatly reduced, thereby greatly reducing an intensity of electromagnetic compatibility.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: An electronic device includes an array substrate. The array substrate includes first to third gate lines, a first to third pixel units, and a gate driving circuit. The third gate line is disposed between the first and second gate lines. The first pixel unit is electrically connected to the first gate line and the data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driving circuit is electrically connected to the first to third gate lines. The gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.

Abstract: An electronic display device has a panel that operates in conjunction with a light-emitting diode (LED) backlight. The device “slopes” or gradually ramps a change in brightness of an LED based on a target brightness value of the LED, a current brightness value of the LED, and temperature at the LED. The device also may limit power to the backlight based on an estimated power consumption of a current row of LEDs of the backlight and power consumption of the other rows of LEDs. The device also may determine a reduced voltage to supply to an LED based on a current to supply to the LED to cause the LED to operate. The device also may send an interrupt to the backlight to block updates to the backlight while image content is written to pixels of the panel. The device further compensates for aging of and temperature at an LED.

Abstract: A liquid crystal display (LCD) and a method for compensating current leakage of the LCD are provided. The LCD includes a thin film transistor (TFT) array having a plurality of TFTs, a gate driver configured to provide a scan signal, a source driver configured to provide a data signal, and a timing controller electrically connected to the gate driver and the source driver. The timing controller is configured to adjust a current refresh frequency according to a current frame rate and to transfer a control signal to the gate driver when the current refresh frequency is lower than a threshold frequency such that the gate driver increase a charging time of the plurality of TFTs according to the control signal.

Abstract: Disclosed are a display apparatus, a drive chip, and an electronic device. When determining that a disconnected signal line (DL) exists, a drive chip sends a control signal to a signal line repair module, so that shift output ends (OUT) of a plurality of shift units sequentially output enable signals, and the shift unit corresponding to a connection switch electrically connected to the disconnected signal line (DL) continuously outputs enable signals, so that the connection switch electrically connected to the disconnected signal line (DL) is continuously turned on. The display apparatus may repair a disconnected signal line without being returned to a factory and a manual operation.

Abstract: A variation in a signal line voltage is suppressed. A signal line drive circuit drives a plurality of signal lines, and the signal line drive circuit includes: a reference voltage generation unit that generates a reference voltage whose voltage level changes with time in a first period before the plurality of signal lines is driven; a current holding unit that is provided to correspond to the signal line and holds a current corresponding to a load of the signal line and a temporal change of the reference voltage; and a current control unit that causes the current held by the current holding unit to flow through the corresponding signal line in a second period after a lapse of the first period to generate a drive voltage of the signal line.

Abstract: A gamma voltage generator, a source driver and a display apparatus are provided. The gamma voltage generator is connected with a plurality of channel circuits and is used for outputting the predetermined number of gamma voltages, and each channel circuit selects at least one gamma voltage according to input display data to generate a corresponding data voltage. The gamma voltage generator includes a plurality of basic buffers and a plurality of dynamic buffers. Each dynamic buffer is configured to operate in a first mode of not outputting a buffer voltage or in a second mode of outputting a buffer voltage, wherein, the plurality of dynamic buffers switch from the first mode to the second mode based on update or change of the display data. The buffer voltages from the two types of buffers are used to generate the gamma voltages.

Abstract: A display device including: a display area including pixels connected to data lines and scan lines, the display area including a plurality of signal output lines connected to each of the scan lines through a contact; a data driver including a first data driving circuit at a side of the display area; a scan driver disposed at the side of the display area; and a timing controller, wherein the first data driving circuit includes: output buffers which respectively output data signals to first to k-th data lines (k is an integer greater than 2) of the data lines; and an output delay controller which transmits the data signals to the output buffers through first to k-th transmission lines, and controls delay times of the data signals output to the first to k-th transmission lines based on position information of a pixel row to which the data signals are supplied.

Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, including a pixel array region and a peripheral region; and a first scan driving circuit, a plurality of power lines, a first signal line group, and a second signal line group, which are in the peripheral region and located on a first side of the base substrate. The first scan driving circuit includes a plurality of cascaded first shift registers; the plurality of power lines are configured to provide a plurality of power voltages to the plurality of cascaded first shift registers in the first scan driving circuit; the first signal line group includes at least one timing signal line; and the second signal line group is on a side of the plurality of power lines and the first signal line group away from the pixel array region.

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: The present disclosure provides a chip-on-film, a display substrate, a display device and a driving method. The display substrate includes a plurality of scanning lines and a plurality of cascaded shift register units coupled to the scanning lines. The display substrate further includes an output control signal line electrically coupled to each shift register unit for providing an enable signal for the shift register unit. The output control signal lines include at least two output control signal lines for providing different enable signals, and two adjacent cascaded shift register units are coupled to different output control signal lines.

Abstract: Provided are a mura compensation circuit which prevents a change in color of a pixel upon mura compensations for the pixel and a driving apparatus for a display applying the same. The mura compensation circuit includes a mura memory configured to store mura information including location information of a pixel having mura and compensation values for colors thereof, a gain adjustment unit configured to provide adjustment compensation values generated by applying an adjustment gain having an identical ratio to the compensation values for the colors of the pixel, and a mura compensation unit configured to receive display data of the colors of the pixel and to perform mura compensations on the display data of the colors of the pixel using the adjustment compensation values corresponding to the location information.

Abstract: The present disclosure discloses a display apparatus having a lock function and a display driving circuit thereof. The display driving circuit of the present disclosure is configured to transfer a lock signal in a cascade way, receive a lock signal by pull-up and transfer the lock signal in an open drain form.

Abstract: A display device includes a display panel, a plurality of switch circuits and a charge sharing controller. The display panel includes a plurality of pixels which are connected to a plurality of gate lines and a plurality of source lines. The plurality of source lines are divided into a plurality of source line groups. The plurality of switch circuit electrically connect source lines included in each of the plurality of source line groups based on each of a plurality of group switch control signals to perform charge sharing. The charge sharing controller generates each of the plurality of group switch control signals based on first most significant bits (MSBs) of each of a plurality of (K?1)th digital data groups and second MSBs of each of a plurality of Kth digital data group.

Abstract: A display device and a terminal are provided. The display device includes first pixel units and second pixel units arranged alternately along a first direction. In an energy saving mode, a control module is used for controlling one of the first pixel units and the second pixel units to emit light in a current display frame, for controlling another one to detect a threshold voltage of driving units of pixel driving circuits, and for controlling pixel units emitting light and pixel units for detecting to swap with each other. Energy consumption can be lowered, and detection time is sufficient.

Abstract: The present disclosure relates to a data drive circuit capable of increasing clock and data recovery stability by generating a clock synchronized with input data, a clock recovery method thereof, and a display drive device having the same, and the data drive circuit according to an aspect includes a receiver including a clock and data recovery part configured to recover a test data pattern from input data using an internal clock, and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal according to a degree of asynchronicity between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery part recovers a clock synchronized with the input data according to the control signal, and recovers control information and image data from the input data using the recovered clock.

Abstract: The embodiments relate to a display device that includes an input terminal through which a feedback voltage of a high-potential driving voltage is received from a display panel. An output terminal is included through which a high reference voltage and a low reference voltage generated on the basis of the feedback voltage are output. A flexible printed circuit board (FPCB) includes at least one capacitor connected between the input terminal and the output terminal.

Abstract: An amplifier circuit includes a differential input terminal, a first power supplier, an amplifier, and a current redistributor. A differential input terminal includes a first differential pair of a p-type and a second differential pair of an n-type, and receives an input voltage. A first power supplier supplies a bias current to the differential input terminal. An amplifier receives an output current of the first differential pair and an output current of the second differential pair, and applies an amplified current to an output node. A current redistributor receives the output current of the first differential pair and the output current of the second differential pair, and provides a redistribution current to the differential input terminal.

Abstract: Provided is a display system, including one or more display screens (11, 12), a plurality of source drivers (13, 14), a timing controller (15) and a graphics processing unit (16). Each display screen (11, 12) is connected to one or more source drivers (13, 14). The graphic processing unit (16) is connected to the timing controller (15). The timing controller (15) is connected to the plurality of source drivers (13, 14). The graphic processing unit (16) is configured to determine each image of the one or more display screens (11, 12) and transmit the image to the timing controller (15). The timing controller (15) is configured to divide each image of the one or more display screens (11, 12) into a plurality of sub-images in a P2P transmission manner, and output in parallel the corresponding sub-images to the plurality of source drivers (13, 14).

Abstract: The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.

Abstract: A gate driving circuit and a display panel are provided. The gate driving circuit includes a plurality of shift register units as cascaded, and the plurality of shift register units as cascaded includes a first shift register unit including a first clock signal terminal, an (n+1)-th shift register unit including an (n+1)-th clock signal terminal, a second shift register unit including a second clock signal terminal, and an (n+2)-th shift register unit including an (n+2)-th clock signal terminal. The gate driving circuit further includes a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal.

Abstract: The invention relates to a source driver and a composite level shifter. The source driver comprises a data buffer circuit, a plurality of level shifters and a plurality of driving circuits. The data buffer circuit receives and registers a plurality of pixel data during a driving period. The level shifters convert the voltage levels of the pixel data registered in the data buffer circuit during the driving period. The driving circuits generate a plurality of source signals according to the converted pixel data during driving period. The data buffer circuit may comprise a plurality of composite level shifters for converting the voltage levels of the pixel data, and latching the converted pixel data.

Abstract: A demultiplexer gate driver circuit and a display panel are provided. The demultiplexer gate driver circuit aims at the problem that the output amplitude of the m sub-gate drive signals divided from the gate drive signal by the demultiplexer module is low, which results in a poorer All Gate On function, when the GOA circuit of the demultiplexer module is used to achieve the All Gate On function. The full-on control module is improved by connecting the full-on control module to the m sub-gate drive signals divided from the gate drive signal. The m sub-gate drive signals are directly controlled by the full-on control module to output the high potential at the same time, and there is only one threshold voltage consumption from the full-on control signal to the sub-gate drive signals. The effect of the All Gate On function is effectively improved.

Abstract: A pixel circuit includes an input circuit and a time control circuit. The input circuit is configured to output a driving signal to an element to be driven. The time control circuit is configured to control a light-emitting duration of the element in a light-emitting phase to be a first duration by controlling the input circuit coupled thereto in response to a first control signal from a first control signal terminal, and control the light-emitting duration in another light-emitting phase to be a second duration by controlling the input circuit in response to a second control signal from a second control signal terminal and a third control signal from a third control signal terminal. The second duration is less than the first duration. The second duration includes interval time periods. The third control signal has a frequency multiple times that of the first control signal or the second control signal.

Abstract: Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge of the start signal within the vertical blanking cycle of the (N?1)th frame cycle. Alternatively, the timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the Nth frame cycle.

Abstract: A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to xth input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to xth input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to xth input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

Abstract: Embodiments disclosed herein provide systems and methods for testing and repairing various aspects of an electronic display. The electronic display includes a reference array and an active array. The electronic display also includes test circuitry used to test individual or any combination of pixels of the electronic display. Switches may be disposed between the pixels and the test circuitry to be to repair the various components of the electronic display.

Abstract: A method for controlling a display panel includes: controlling polarities of data signals transmitted to pixel circuits in partial columns in a target display region to be inverted when a (KN?1)th frame is displayed; and controlling polarities of data signals transmitted to pixel circuits in other columns than the partial columns in the target display region to be inverted when a KNth frame is displayed.

Abstract: A display device including a flexible display panel and a roller disposed on a side portion of the flexible display panel to wind the flexible display panel, in which the flexible display panel includes a first substrate including a first base substrate having a display region and a non-display region adjacent to each other, and a light emitting element layer including light emitting elements disposed on the display region, a second substrate including a second base substrate opposing the first base substrate, and a color conversion layer disposed on the second base substrate and corresponding to each light emitting element, and an adhesive filling layer disposed in the display region to form a cell gap between the first and second substrate, and disposed in the non-display region to be in contact with the first and second base substrates to couple and seal the first and second base substrates.

Abstract: The present disclosure relates to the field of display technologies, and provides a gamma circuit. The gamma circuit includes: a plurality of positive gamma voltage output terminals, a plurality of negative gamma voltage output terminals in one-to-one correspondence with the plurality of positive gamma voltage output terminals, and a plurality of voltage conversion circuits. Each of the voltage conversion circuits is configured to output a negative gamma reference voltage to the negative gamma voltage output terminal based on a positive gamma reference voltage output by the positive gamma voltage output terminal corresponding to the negative gamma voltage output terminal.

Abstract: A display device includes a display panel including a first partial panel region and a second partial panel region, and a panel driver which drives the display panel. The panel driver determines a first driving frequency for the first partial panel region and a second driving frequency for the second partial panel region. In a case where the first driving frequency and the second driving frequency are different from each other, the panel driver sets a boundary portion including a boundary between the first partial panel region and the second partial panel region, and determines a third driving frequency for the boundary portion to be between the first driving frequency and the second driving frequency.

Abstract: The display device includes a first data line group including data lines connected to pixels arranged at a first resolution; a second data line group including data lines connected to pixels arranged at the first resolution and pixels arranged at a second resolution; a first gamma compensation voltage generation unit that divides a first reference voltage and outputs a gamma compensation voltage; a second gamma compensation voltage generation unit that divides a second reference voltage and outputs gamma compensation voltages; a first data drive unit that converts pixel data into the gamma compensation voltage output from the first gamma compensation voltage generation unit and outputs a data voltage to the first data line group; and a second data drive unit that converts pixel data into the gamma compensation voltage output from the second gamma compensation voltage generation unit and outputs a data voltage to the second data line group.

Abstract: A display apparatus includes: a display; a display driver that drives the display such that the display displays in accordance with display data; and a host controller that transfers update display data of one screen to the display driver. The display driver includes a light-emission controller that causes a self-luminous elements to emit light, and a memory that stores the update display data of the one screen. The display driver reads the update display data on the memory after an elapse of a predetermined period of time from a drive end time at which the display controller finishes driving in accordance with the update display data and drives the screen by using the read update display data. The display driver drives the self-luminous elements once or more at a timing when the update display data from the host controller to the display driver is not updated.

Abstract: A display apparatus includes a luminance controller that controls a luminance of a displayed video, a gamma controller that applies a gamma curve to a video signal, and a display that displays a video represented by the video signal that the gamma controller has applied the gamma curve to. If the luminance controller causes the display to display the video at a luminance value lower than a predetermined luminance value, the gamma controller applies to the video signal a gamma curve with a lower gradation region raised more than a gamma curve represented by a predetermined constant gamma coefficient.

Abstract: A shift register unit includes an input circuit, a first control circuit, a second control circuit and an output circuit. The input circuit is configured to provide signals of the signal input terminal to the first control node, and provide signals of the first power supply terminal or the first clock signal terminal to the second control node. The first control circuit is configured to provide signals of the second power supply terminal or the second clock signal terminal to the first output terminal. The second control circuit is configured to provide signals of the first power supply terminal to the second output terminal. The output circuit is configured to provide signals of the second power supply terminal to the second output terminal.

Abstract: A device for increasing a slew rate of a driving amplifier includes a driving amplifier, a slew rate improvement circuit, and a controller. The driving amplifier is configured to amplify an input voltage and output an output voltage. The slew rate improvement circuit is configured to provide or receive a current to increase the slew rate of the driving amplifier. The controller is configured to control an operation of the slew rate improvement circuit based on a difference between a first code corresponding to the input voltage of the driving amplifier during a current horizontal line time and a second code corresponding to the input voltage during a next horizontal line time.

Abstract: A display device includes a display panel having pixels. A timing controller generates a first control signal and data control signals. Data driving circuits each recover a data signal from a corresponding data control signal of the data control signals in response to the first control signal, generate a data voltage corresponding to the data signal, and provide the data voltage to the display panel. Each of the data driving circuits includes: a setting unit configured to acquire a setting value from the data control signal; an equalizer configured to compensate for distortion of the corresponding data control signal according to the setting value to output compensated data control signal; and a recoverer configured to recover a clock signal from the compensated data control signal and recover the data signal from the compensated data control signal based on the clock signal.

Abstract: A display device includes a plurality of pixels, a serial-to-parallel converter (SPC), a plurality of digital-to-analog converters (DACs), a plurality of switches, and a controller. The pixels are arranged in rows and columns. The columns include a first column and an adjacent second column. The SPC generates parallelized pixel data based on serial pixel data sent by a graphics controller. The DACs are coupled to the SPC and include a first DAC corresponding to the first column and a second DAC corresponding to the second column. The switches include a first switch that includes a first input coupled directly to an output of the SPC, a second input coupled to an input of the first column, and an output coupled to an input of the second column. The controller selects pixel data on one of the first input and the second input for output by the first switch.

Abstract: Embodiments of the present disclosure relate to a touch display device, a driving method, and a driving circuit. More particularly, embodiments of the present disclosure relate to a touch display device, a driving method, and a driving circuit capable of preventing touch sensitivity from being affected by display driving even though simultaneously performing the display driving and touch driving by supplying a data voltage to a plurality of data lines disposed in a display panel, supplying a common voltage to a plurality of common electrodes disposed in the display panel, displaying an image through the display panel, and supplying a common voltage to the common electrodes.

Abstract: A display device and a method of driving the same are provided. The display device according to an embodiment includes a plurality of pixel rows, a data driver configured to provide first data voltages which correspond to first line grayscale data to pixels disposed in an (N?1)-th pixel row, provide second data voltages which correspond to second line grayscale data to pixels disposed in an N-th pixel row, and provide third data voltages which correspond to third line grayscale data to pixels disposed in an (N+1)-th pixel row, and a data compensator configured to compensate for the second line grayscale data by using one of a first compensation and a second compensation based on the first line grayscale data, the second line grayscale data, and the third line grayscale data.

Abstract: An array substrate, a display panel and a display device are provided in the present disclosure. The array substrate includes a plurality of pixel circuits arranged in an array and a first signal line electrically connected to a pixel circuit of the plurality of pixel circuits. The first signal line includes a branch portion; the pixel circuit includes a storage capacitor, a drive transistor, and a first connection portion electrically connected to a gate electrode portion of the drive transistor; one plate of the storage capacitor at least partially overlaps the gate electrode portion of the drive transistor; and the branch portion at least partially overlaps the first connection portion.

Abstract: The present embodiment relates to a data processing device and a display device and, more specifically, to data processing device and a display device for selectively applying an image quality improvement function in consideration of the characteristics depending on the positions on a display panel.

Abstract: The display device includes a first pixel connected to a first scan line and a first data line, a second pixel connected to a second scan line and the first data line, a scan driver configured to supply a scan signal to the first scan line and the second scan line, and a data driver connected to the first data line. The data driver provides a first data signal to the first pixel when the scan signal is applied to the first scan line, the data driver provides a second data signal to the second pixel when the scan signal is applied to the second scan line, and a length of a first period in which the first data signal is provided is different from a length of a second period in which the second data signal is provided.

Abstract: Device for displaying images comprising: a line selector, the line selector and/or the column controller comprising a selection circuit comprising a succession of output channels corresponding to various rows of the matrix, said selection circuit further comprising a succession of shift registers and a succession of switches controlled by at least one configuration word for controlling the respective configurations of the succession of switches of said selection circuit and for placing the switches of said succession of switches respectively in one of said first configuration or second configuration according to the respective states of configuration bits of this configuration word, the first configuration allowing to propagate a signal in the succession of registers, the second configuration allowing to duplicate a signal emitted on the preceding output channel on the given output channel in order to consequently duplicate on a row corresponding to the given output channel a piece of data intended for a row

Abstract: A processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between the processing system and a controller. The source driver circuitry is configured to update a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. The timing controller may be further configured to resume the scanning of the plurality of gate lines in response to the expiration of the time limit.

Abstract: An operational amplifier includes an input stage with a first main input unit, a first auxiliary input unit, a second main input unit and a second auxiliary input unit, an amplification stage with a first current mirror receiving currents from the first main input unit and the first auxiliary input unit, and a second current mirror receiving currents from the second main input unit and the second auxiliary input unit, an output stage receiving voltages from the first current mirror and the second current mirror, a voltage storage unit storing an intermediate voltage based on an output signal generated by the output stage during at least one of a first operation period and a second operation period, and a switching unit that differently controls a first feedback path between the output stage and the input stage and a second feedback path between the output stage to the voltage storage unit in accordance with the first operation period and the second operation period.