Abstract: An automatic digital frequency control circuit is used for processing a digital video signal. The control circuit includes a phase difference calculator, which samples an analog horizontal sync signal and generates a phase difference value between the corrected phase values with respect to a present scanning line and a phase value of a previous scanning line of which the error values are corrected when a digital horizontal sync signal is obtained, and a phase difference accumulator, which accumulates the phase difference value from the phase difference calculator to a phase difference accumulated value which has been already stored therein.

Abstract: A synchronizing signal separator receives synchronizing signals from a remote source. A window generator opens a window for a period and a counter regenerates synchronizing signals detected when the window is open. Detection of an incoming synchronizing signal when the window is open causes a window counter to be stopped to reduce the window duration to approach a set minimum width. The window generator and the counter are controlled by a voltage controlled oscillator whose oscillation frequency varies according to a feedback signal derived from the sense of the phase error between an external counter of the window generator and the regeneration counter.

Abstract: A free running frequency alignment method in a video display having a sync generator comprising a first oscillator having a first frequency and a second oscillator having a second frequency. The first oscillator is phase modulated by the second oscillator which has a free running frequency different from a standard frequency. The free running frequency of the first oscillator is to be controllably aligned to the standard frequency by a method comprising the steps of applying a frequency determining initial control value to the first oscillator and measuring an average free running frequency responsive to the initial control value. An absolute difference frequency is calculated between the average frequency and the standard frequency. The absolute difference frequency is tested for a frequency value less than a predetermined value which signifies an aligned condition. If the difference frequency is less than the predetermined value the alignment is complete.

Abstract: Digital data having a symbol rate that is a multiple of horizontal scan rate are buried in broadcast television signals. In a digital signal receiver the data are separated from composite video signal by quadrature video detection followed by comb filtering. The comb filtering is most economically realized by digital sampling at symbol rates. The regeneration of clocking signals at symbol rate, and at multiples of symbol rate where oversampling analog-to-digital conversion (ADC) techniques are employed, is done using a controlled oscillator with automatic frequency and phase control (AFPC) responding to the horizontal synchronizing pulses transmitted in the broadcast television signals. The horizontal synchronizing pulses are usually much larger than noise, so the controlled oscillator frequency and phase is rapidly adjusted following energization or channel change of the digital signal receiver.

Abstract: A digital time base corrector which can perfectly eliminate residual errors. A sync clock signal whose phase is synchronized with a time base fluctuation included in a reproduction video signal is formed in accordance with at least one of the horizontal sync signal and the color burst signal which are separated from a reproduction video signal. The sync clock signal is phase-modulated in accordance with a burst error signal indicative of the time base fluctuation of the color burst signal in a period of time other than the generating period of time of at least the color burst signal in the reproduction video signal, thereby obtaining a write clock signal of the image memory.

Abstract: In a system which encodes video data in response to an encoding clock, transmits the encoded video data with an encoder clock signal representing the encoding clock frequency, and decodes the video data in response to a decoding clock, system clock accuracy is maintained by adjusting the decoding clock frequency. In order to reduce buffer requirements and to prevent deterioration of video program presentation, the decoding clock frequency is adjusted by slewing only during composite video synchronization periods when composite video decoded from the encoded video stream is not being presented. The preferred video synchronization periods are the vertical blanking interval and the front porch period. Restriction of decoding clock rate adjustment to these periods ensures that decoding clock slew rate limits may be unrestricted, thereby avoiding noticeable effects in the video program presentations.

Abstract: In a system for identifying specific horizontal lines of video that are included in a video signal, a horizontal line counter (100) is cleared to indicate the beginning of a vertical interval by a reset signal (VERDEL) derived from a vertical sync signal (VER). The line counter is clocked by a signal (HOR) at the horizontal sync rate that is derived from a harmonic (N.sub.-- FH) of the horizontal sync signal. The relative phase shift between the reset and clock signals for the horizontal line counter is measured (105,120). The measured phase shift is used as an input to a variable phase shifter (110) to adjust the phasing between the horizontal line counter control signals and the original sync signals. The phase adjustment permits significantly decreasing the sensitivity of the horizontal line counter to jitter of vertical sync.

Abstract: An apparatus, such as an adaptive flywheel, and method for producing periodic time references, forming a periodic time reference signal, from uncertain time references. A counter counts from a first count value to a second count value and provides a periodic time reference each time its count reaches the second count value. An error processing device, coupled to the counter, determines (a) whether an uncertain time reference is received within a predetermined range of count values (corresponding to a window of expectation), or (b) whether the absolute value of the average of an error, corresponding to the number of increment values before or after the second count value, whichever is lower, the count is at when an uncertain synchronization reference is received, and at least one previously determined error for at least one previously received uncertain synchronization reference is greater than WC/2 increment values.

Abstract: A frequency controlled clock circuit for use in a television receiver utilizes a detected sound intermediate frequency (IF) signal for use in controlling a voltage controlled oscillator and thereby provide immunity from ghost signals in the transmitted video signal. A phase locked loop responds to phase errors detected from the voltage controlled oscillator and a reference signal from the sound IF signal to control the frequency of the voltage controlled oscillator.

Abstract: A sync signal generator of a television receiver for use in a vehicle has a phase reset detector for gradually absorbing a phase fluctuation of an input sync signal which occurs due to a ghost phenomenon or a fading phenomenon and reducing a phase fluctuation. The sync signal generator provides a sync signal synchronized with an output signal of the phase reset signal detector. Thus, a stable sync signal without a sudden change in phase can be obtained although it is synchronized with the input sync signal.

Abstract: A secondary signal is processed and injected into a primary color video signal. The timing of the subsequent transmission of the secondary signal is controlled by timing signals. The timing signals also control the transmission of a carrier burst prior to the transmission of the secondary data signal. This carrier burst is used by a receiver to synchronize with the transmitter, reduce transmission errors and to indicate that a data transmission is to follow.

Abstract: A color signal reproducing circuit comprising a phase correction device receiving a gain-controlled composite color signal, detecting color burst signal in a composite color signal and correcting phase of the color burst signal by using a 3.58 MHz signal, first gate for receiving the gain-controlled composite color signal and passing only a color signal when a color burst pulse in the delayed horizontal synchronizing signal applied from the delay device is at a low level, and mixer for mixing the phase-corrected color burst signal and the color signal from the first gate to produce a phase-corrected composite color signal.

Abstract: A synchronizing signal regenerating circuit for standard video signals in a digital video signal processing system includes a circuit for regenerating stable horizontal synchronizing signals, a circuit for generating double horizontal synchronizing signals, a circuit for generating horizontal synchronizing signals, a circuit for generating vertical synchronizing signals and an output circuit. The circuit for regenerating stable horizontal synchronizing signals regenerates the horizontal synchronizing signals in response to quadruple burst signals, and the circuit for generating double horizontal synchronizing signals is connected to the output terminal of the circuit for regenerating stable horizontal synchronizing signals. The circuit for generating horizontal synchronizing signals is connected to an output terminal of the circuit for regenerating stable horizontal synchronizing signals.

Abstract: A video detector has a PLL, a bias circuit, a synchronous detector for detecting a video IF signal by using the output of a VCO, and a lock detector for detecting whether the PLL is locked. The PLL has the VCO, a phase comparator, and a low-pass filter. In the video detector the supply of the direct current from the bias circuit is halted while said lock detector detects that the PLL is locked.

Abstract: When processing a digital video signal, the problem often arises of converting the signal from a first sampling raster which is asynchronous with respect to the line interval to a second sampling raster which synchronous with the line interval. Interpolation filters are used for this purpose. The present invention provide a simple method for the conversion which does not require intermediate D/A or A/D conversion. For each line of the input signal, the phase of samples of the first sampling raster relative to the line synchronization pulse and the total number of the samples for this line are determined and are used to control of the interpolation filter.

Abstract: A display apparatus for displaying a video image operates with plural horizontal scanning frequencies. The apparatus includes a horizontal scanning frequency oscillator for generating a signal in synchronism with a horizontal synchronous signal of an input video signal; and a control unit for controlling a frequency of an output of the horizontal scanning frequency oscillator corresponding to the horizontal synchronous signal of the input video signal. A multi-scan video monitor may be provided for displaying the image relative to any of the plural horizontal scanning frequencies without any turbulence.

Abstract: An apparatus for compensating a time base error of a video signal. A reference signal of no time base error is generated. A difference between a frequency of the reference signal and a frequency of a horizontal synchronizing signal included in an input analog video signal is detected and then a difference signal is outputted. In response to the difference signal, a phase of the reference signal is controlled. The video signal is sampled, based on the reference signal the phase of which is controlled, thus the video signal is converted into a digital signal in which the difference is cancelled. The digital signal is stored in a memory. And the stored digital signal is read out, based on the reference signal.

Abstract: When supplied with an external synchronizing signal from an input terminal (2), a synchronizing separating circuit (6) separates and detects a horizontal synchronizing signal from the input signal and generates an HD pulse. When supplied with the HD pulse, a flip-flop (9) is set to generate a pulse. This output pulse is integrated by an integrating circuit (8) and an integrated output from the integrating circuit (8) is used to adjust a width of an output pulse from the flip-flop (9) to a value corresponding to a horizontal scanning frequency. The flip-flop (9) can be set only when supplied with the HD pulse, thereby preventing the flip-flop (9) from outputting a pulse whose width is longer than the width of the HD pulse. Therefore, the length of the back porch can be prevented from being reduced more than it is needed.

Abstract: A method and circuit for preventing the deterioration of picture quality in a video processor is disclosed in which, when an input color video signal is input, a clock signal for a combfilter is locked with a phase-locked loop (PLL) by a burst signal and when a monochrome video signal without the burst signal is input, the clock signal is locked by the output (quasi-burst signal) of a voltage-controlled oscillator of the PLL circuit, before the lapse of one horizontal period, so that the clock signal is constantly locked by a multiple (4 fsc) of the burst signal regardless of the presence or absence of the burst signal of the input video signal. According to a color/mono signal discriminating result, either the burst signal or the quasi-burst signal is selected as a reference signal so that the reference signal is locked to provide a clock signal having a constant phase and frequency, thereby preventing aliasing due to clock variations when the monochrome signal is input and thus improving picture quality.

Abstract: A burst phase correcting circuit includes a first all-pass filter which receives a chrominance sign inputted from a terminal. A phase reference signal from an oscillator is applied to a first phase-comparator together with an output signal from the first all-pass filter, after the same is phase-shifted by 90 degrees by a first phase-shifter. A signal according to a phase difference of the both signals is outputted from the first phase-comparator and applied to the first all-pass filter via a first low-pass filter and a capacitor. Therefore, in the first all-pass filter, a delay time is varied in accordance with the phase difference between the chrominance signal and the phase reference signal. Therefore, a jitter component of the chrominance signal can be removed.

Abstract: A horizontal sweep control synchronization circuit fixes the phase relationship between a horizontal synch pulse signal and a flyback signal by utilizing a first phase-lock-loop to fix the phase relationship between an oscillator signal, generated by the first loop, and the synch pulse signal, and a second loop to fix the phase relationship between the flyback signal and the oscillator signal. The first loop locks an edge of the synch pulse signal to the center of the oscillator signal, thereby allowing the synch pulse signal to remain locked to the oscillator signal during vertical retrace. The synchronization circuit only utilizes a single ramp forming circuit, thereby eliminating the jitter associated with multiple ramp forming circuits.

Abstract: A digital phase-locked loop (PLL) which responds to a square-wave input signal of on expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals or different frequencies and precedes a main divider operating with a divisor D and which produces the output signal of the phase-locked loop. The change-over switch is activated as a function of the output signal and the input signal. In order to provide symmetrical locking in of the phase-locked loop and a small capture-and-hold range, the change-over switch is switched between a first square-wave signal of the frequency f.sub.1, a second square-wave signal of the second frequency f.sub.2 and a third square-wave signal of the frequency f.sub.3, in which:f.sub.1 .multidot.1/D=f.sub.Eandk.multidot.f.sub.1 =f.sub.2 +(k-1).multidot.f.sub.3,A switching logic is provided which controls the change-over switch in such that it is switched to the signal of the first frequency f.sub.

Abstract: A phase control circuit for controlling the relative phase of periodic components of two logic signals having the same frequency, and one of which periodic components has a pulse-duty factor different from 50:50, said circuit includes a signal source which provides a control signal for regulating the relative phase of the periodic components of said logic signals. The control signal has a first value for phase relationships in a predetermined range of values and a second value for phase relationships outside said range of values. A phase lock detector detects the lock status of the periodic components of the logic signals. Another signal source provides a third logic signal having a periodic component having the same frequency as the periodic component of each of the two logic signals and a pulse width substantially wider than that of the two logic signals.

Abstract: A television receiver is subject to certain operational conditions which result in poor, unreliable or unusable separated sync pulse signals. During such conditions the use of unsuitable sync signals for synchronization and the like is inhibited to prevent mis-triggering or spurious synchronization. A television receiver contains circuitry for extracting a sync signal, a voltage controlled oscillator (VCO) for generating a scanning signal, and a comparator comparing the scanning signal to the separated sync signal. A microprocessor is used to verify the separate sync signal for invalid or unusable signals and has an output activated during such conditions. The phase comparator has a current output coupled to a integrating capacitor or LPF which develops a varying positive or negative voltage to raise or lower the frequency of the VCO for scanning in phase with the separated sync.

Abstract: A television receiver includes a long loop frequency and phase locked loop (FPLL) in which the tuner voltage is controlled by the output voltage of the FPLL. A SAW bandpass filter couples the IF signal from the tuner to a synchronous demodulator and to the FPLL. An oscillator includes a SAW resonator that is formed on the same substrate as the SAW bandpass filter for supplying a reference signal to the FPLL and to the synchronous demodulator. The common substrate assures tracking between the IF SAW bandpass filter and the oscillator SAW resonator with temperature changes and processing variations.

Abstract: A horizontal synchronization circuit uses a standard decoder to generate a stable first signal locked in frequency and phase to horizontal synchronizing pulses in a composite video signal. A waveshaping circuit reshapes the first signal to generate a second signal for input to a synchronizing circuit. The synchronizing circuit generates a higher-frequency third signal. A timing generator divides the frequency of the third signal to generate a fourth signal having the same frequency as the first and second signals, and a fifth signal having a higher frequency. The fourth signal is fed back to the synchronizing circuit, and can also be used for synchronization of video signal processing. The fifth signal can be used for horizontal scanning at a rate higher than the standard horizontal frequency.

Abstract: A circuit for detecting a jitter of an image signal reproduced from a recording media, comprises a variable oblique wave generating circuit for generating an oblique wave at timing according to the phase of the output pulse of a frequency dividing circuit wherein a tilt of the oblique wave is varied by an input control signal a sample-hold circuit for sampling and holding the tilt portion of the variable oblique wave in dependence upon reception of a horizontal synchronizing signal as a sample pulse.

Abstract: A television apparatus includes a display for a video signal representing a picture. The video signal has a vertical synchronizing component defining fields of horizontal lines which can have other than a standard number of horizontal lines per field under certain operating conditions. A counter measures the number of horizontal lines in each field. A panning circuit generates a vertical reset signal which is phase shifted by a selected number of horizontal lines relative to the vertical synchronizing component of the video signal for vertically panning the picture on the video display by the selected number of horizontal lines. The selected number of horizontal lines is adjusted responsive to the measured lengths of the fields to maintain the selected amount of vertical panning even under the certain operating conditions.

Abstract: A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.