Abstract: A converted digital signal is provided in an NRZI (non-return to zero, inverted) code with a zero DC component and with a maximum predetermined number of bits between level transitions in the signal. The base digital signal is divided into m-bit base words, each of which is then converted into an n bit converted code word to form a converted digital signal suitable for recording. The n-bit converted code word is selected from a plurality of primary combinations or code words having a DC component substantially equal to zero when NRZI-coded and a plurality of secondary combinations or code words having a DC component with an absolute value of two when NRZI-coded. A variance of the DSV (digital sum variation) of each primary combination when NRZI-coded and a polarity of the DC component of each secondary combination when NRZI-coded are altered in response to the DSV at the exit of the preceding converted digital signal.

Abstract: Magnetic recording of a data continuum is effected by means of sequential impulses of recording current. The impulses occur at regular intervals providing samples of the data continuum. The impulses are of very short time duration, in that each impulse extends for only a small fraction of the time interval that is required for a point on the record medium to traverse the effective recording field of the record head. The time spacing between impulses is approximately equal to said time interval, thereby providing a magnetic recording continuum corresponding to said data continuum.

Abstract: In a detecting and compensating circuit of an apparatus for reproducing a digital signal separated by frame synchronizing signals into frames, each having a predetermined frame period, the combination comprising a detecting circuit which detects the frame synchronizing signals and generates respective detection signals in response thereto, a gating circuit which receives the detection signals and which gates the latter in response to gating signals, and a windowing circuit which generates window signals of a predetermined length in response to the detection signals and which supplies the window signals as the gating signals to the gating circuit.

Abstract: An encoded signal free of dc content is provided by modifying the Miller encoding scheme for digital data streams. The digital data stream is broken up into a sequence of blocks delineated by a one-to-zero transition at the beginning of each block. Each block is further subdivided such that the first half contains only zeros and the second half contains only ones. The number of zeros and ones are counted and novel encoding rules are applied depending on whether the number of ones and zeros is odd or even. If both the number of zeros and ones is even or odd, or the number of zeros is even and the number of ones is odd, encoding is accomplished using standard Miller rules. If the number of zeros is odd and the number of ones is even, Miller rules are used except the last one in the group is ignored. When both the number of zeros and ones is odd, special encoding rules are applied to the next block, dependent on the content of the next block.

Abstract: Digital data formatted on a data storage medium, in which the medium has a plurality of bit cells and the data format is such that groups of n data bits of an N-bit data word are stored over n consecutive bit cells, respectively, and a clock information bit is stored between the groups at every n+1 bit cell. A decoding apparatus includes circuitry for reading the digital data and producing an analog signal corresponding to the n data bits and the clock information bit, circuitry for reconstructing the digital data in response to the analog signal, and circuitry for producing data-ready pulses at a time corresponding to the bit cells storing the n data bits and for inhibiting the data-ready pulses at a time corresponding to the bit cell storing the clock information bit.

Abstract: The use of delay modulation (or "Miller") phase coding to encode transmitted data is disclosed in a multinodal, peer network communication system. The use of delay modulation provides bandwidth compression and reduces the direct current (dc) voltage component of transmitted data. In addition, the delay modulation provides a unipolar communication in which the transmitted waveform contains both data and synchronization information and error detection capabilities.

Abstract: A data demodulator is composed of a data separation circuit which produces synchronizing clock pulses from M.sup.2 modulation data which is reproduced by a data recording device and separates the M.sup.2 modulation data into clock bits and data bits, and an M.sup.2 demodulation circuit which produces NRZ - L data by using the clock bits, data bits and synchronizing clock pulses which are output from the data separation circuit. M.sup.2 modulation data which is input to the M.sup.2 demodulation circuit is demodulated to a data signal in NRZ - L format by the demodulation circuit, which has a simple structure.

Abstract: Apparatus for use in recording digital words on magnetic tape without developing a net D.C. charge that would cause base line shift by use of a scheme of mapping of the words into code patterns from a larger number of bits and preselecting patterns which either have no D.C. weight or have a D.C. weight of .+-.4 or .+-.8 and in the latter two cases, providing alternate patterns for such words both with opposite sense to be used alternately to contract any charge buildup, the patterns also being selected to avoid frequency doubling.

Abstract: A converted digital signal is provided in NRZI code with a DC component of zero and with a maximum of four bits between level transitions in the signal by dividing the base digital signal into eight-bit base words, each of which is then converted into a ten-bit word signal that has 1024 (2.sup.10) possible combinations, of which there are 193 that begin with no more than two digital zeros, end with no more than one digital zero, have no more than three consecutive digital zeros anywhere else, and have a DC component of zero when NRZI coded, and each of which is used to represent one eight-bit base word. Each of the remaining 63 of the total 256 (2.sup.8) base words is converted into a secondary ten-bit combination having a "convention" DC component of +2 or -2.

Abstract: A method and system for high density data recording is provided. Parallel encoded digital data are converted to corresponding serial format data words. Individual cycles of a periodic signal are selectively attenuated in accordance with the logic state of individual bits of the serial data words. By determining the relative level of the periodic signal during periods defined by individual cycles of the signal, the sequence of logic data bits forming the serial data words can be reconstructed.

Abstract: A high-speed digital transceiver is provided for use in a PBX environment comprising twisted-pair wire cables interconnecting like transceivers, each transceiver being operative to exchange voice, data and control information in a packetized format over a common twisted-pair cable. Specifically, each transceiver communicates packetized pulse code modulated information in pure Alternate Mark Inverted (AMI) coding, that is, without the introduction of bipolar violation pulses to provide timing. Frame synchronization is acquired on the first pulse by the use of a digital circuit deriving synchronization from a local high-speed clock. The use of a high-speed clock-driven digital circuit for synchronization acquisition eliminates the need for a phase-locked loop synchronization scheme and its concomitant finite acquisition delay.

Abstract: A method and apparatus for transmitting binary sequential data by the multi-level encoding of grouped selected data bits are disclosed. A first number of data bit sequences of the grouped data bits are translated into uniquely chosen ones of a first group of differing level pairs of a multi-level signal and the remaining data bit sequences of the grouped data bits are translated, in a first mode of translation, into uniquely chosen ones of a second group of differing level pairs of the signal, and, in a second mode of translation, into uniquely chosen ones of a third group of differing level pairs of the signal, the mode of translation changing after the occurrence of any of the remaining data bit sequences.

Abstract: A method of run-length-limited encoding strings of data including a sequence of synchronizing bits having a value of binary zero for providing corresponding encoded bits which, when recorded on a magnetic storage medium, provide a maximum number of flux transitions. The steps of this method include serially receiving such a string of input bits, dividing the string of input bits into unique bit groups, replacing each group with a corresponding collection of encoded bits conforming with the limitations of the run-length-limited encoding scheme, including replacing each divided group of three input binary zeros into a collection of six encoded bits having two binary ones separated by two binary zeros, serially transmitting these collections of encoded bits for recording the same on the medium in the same sequence as the corresponding input bit groups are received.

Abstract: A class of ternary square wave signals is detectable by peak polarity detection alone without need for amplitude discrimination. The ternary codes are used to increase data density recording at the same clock rate as binary codes. This is satisfied by selective direction-constrained run length limited (RLL) signals. The direction constraint is that the half-step transitions can only occur in pairs of the same polarity. Alternate half-step pairs of opposite polarity are forbidden. This avoids the need for amplitude discrimination. The RLL (d,k) constraint includes "d" number of clock times when a transition is forbidden and "k>d" clock times within which consecutive transitions must occur. The latter determines a minimum frequency for clocking purposes. This eases peak shift detection.

Abstract: In an encode method in which a binary data stream is divided into data words each of three bits. Each of the data words is encoded into a binary code word of 9 bits. In the method, a code word to be encoded is encoded in consideration of a code word preceding the code word and two code words succeeding the code word. Then, one of the first two code bits in each code word and two of the last five code bits in the preceeding code word are inverted according to a pattern of code bits "0" and "1" in both the code words. As a result, consecutive 5 to 19 code bits "0" are arrayed between two adjacent code bits "1" in the code word stream.

Abstract: With the aid of a delay element and an EXCLUSIVE OR gate, from a binary input signal, upon the occurrence of a level change, an inhibit signal is obtained which blocks a freely-oscillating renewal pulse generator at its output, upon occurrence of level changes in the binary signal, so that the pulse transmission can proceed undisturbed by the renewal pulses through data pulse generators which are activated by the level changes of the binary signal occurring at a tap of the delay element, this is for the purpose of emitting a data pulse which is chronologically offset relative to a level change. The renewal pulses can follow a data pulse, however, at random times within a maximum time interval which is determined by the repetition frequency of the renewal pulses, since no chronological synchronization of the renewal pulses to a preceding data pulse is provided.

Abstract: A ternary magnetic recording system wherein groups of binary input digits are transformed into corresponding groups of ternary recording code symbols utilizing a hierarchical code substitution system in which the longest valid group in the code is encoded. The code substitution system provides retention of the advantageous properties of a prior ternary recording system while significantly enhancing the automatic gain control utilized in amplitude discrimination between two of the ternary recording symbols. Anomalous detection of chained doublets is also obviated. Data recovery is effected by decoding apparatus utilizing an eight bit addressable ROM addressed with a twelve bit ternary word.

Abstract: A method of encoding and decoding binary data, comprising the steps of: dividing the binary data into 2-bit data groups, converting each 2-bit data group into a 5-bit code having a minimum of 4 consecutive bits "0" between a bit "1" and the next bit "1", and converting reversely the encoded 5-bit codes into the original binary data with reference to another 5-bit codes located forwardly of and rearwardly of the 5-bit code. By employing this method, it becomes possible to obtain a density twice higher than that of "MFM" method.

Abstract: A method and apparatus for digital magnetic recording of data in which digital data is recorded on a magnetic recording medium after being demodulated by the NRZI (Non-Return-to-Zero Inverted) system and read thereoutof timed to magnetic flux reversal caused by the recorded data on the recording medium. The digital data is encoded in a predetermined manner before the NRZI modulation so that at least part of "false" bits contained in the digital data is converted into "true" bits, resulting in an increase in the number of "true" bits. The encoded data is written into the recording medium after the NRZI modulation. In the event of reproduction of the data from the recording medium, self-clocking occurs to generate a data readout timing. The increased number of "true" bits insures desirable self-clocking. The data read from the recording medium is decoded to the original digital data.

Abstract: A quaternary saturated digital magnetic recording system for enhancing information entropy provides an effective bit density increase of 100% or more over the MFM code. In the simplest implementation, groups of two input binary bits are mapped into one data cell, preferably into four combinations of long or short breaks and positive or negative polarity, with the break optionally centralized within the data cell for self-clocking. A system for reproducing the recorded information provides a peak detector, responsive to the recorded signal, coupled to pulse polarity and break width detector circuitry, with an internally synchronized clock, for remapping the recorded data into binary format.

Abstract: A method is disclosed for processing binary data prior to magnetic recording. The binary data is divided into 4-bit data segments which are converted to 8-bit codes according to a predetermined encoding transfer function describing the relationships between the 4-bit data segments and corresponding 8-bit codes, wherein the bit pattern of each 8-bit code has an intra-code run-length of at least two "0" bits and forms an inter-code run-length of from at least two "0" bits to at most nine "0"bits with an adjacent 8-bit code. The method further includes the step of generating a frame synchronization code and interleaving it with 8-bit codes to form a frame of binary digits. The frame sync code has a bit pattern which is unduplicatable by any combination of 8-bit codes that follow.

Abstract: Circuitry for distinguishing each value in a read signal magnetically recorded in ternary-3 position modulation in which the values 1, 2 and 0 are detected and equalized into a singlet, a doublet and absence of magnetic flux change. The circuitry first determines the position locations of each singlet peak and doublet crossover point to establish proper timing of the output signals and then identifies the particular type of signal appearing at the timing points in the read signal sequence. Singlets are identified by the much greater amplitudes in the integrated read signal. Doublets are identified as waveforms having slopes at zero crossovers that correspond in polarity to that of the previous singlet. A novel detector circuit is provided that can correctly identify doublets in a code sequence, irrespective of the presence of a previous singlet, when a recording rule is followed that includes the insertion of a number of consecutive ternary 0 symbols into the recorded signal.

Abstract: The present invention comprises circuitry for encoding and decoding data according to a (1,8) run-length-limited, variable-length code word scheme. The encoder comprises three four-stage shift registers, two groups of logic gates and a final set of flip flops for clocking the encoding data at twice the incoming data frequency. One set of logic gates uses the outputs of each shift register to produce the encoded data, which is then reclocked at the data frequency. The other set of logic gates uses the outputs of all three sets of shift registers to locate the word boundaries, and supplies this information as input to the third shift register. The decoder consists of a twelve-stage shift register, two sets of logic gates, three single flip flops and a two-to-one multiplexer. One set of logic gates provides decoding for the odd-numbered encoded bits and the other set decodes the even numbered bits.

Abstract: Method and apparatus for producing a binary information by a process comprising the steps of: dividing an input binary data sequence which has a predetermined bit cell length into blocks of a first data pattern thereby forming data blocks; converting information of said data blocks of a first data pattern into data blocks of a second data pattern; integrating accumulated charges of said converted data blocks of the second data pattern; and inverting data of a block of said second data pattern at least when said integrated amount is about to exceed a predetermined finite value in the case that an amount of accumulated charge in said second block is not zero, and producing a binary balanced output code from said second data pattern and said inverted data.

Abstract: Successive n-bit information words are converted into successive m-bit NRZI code words by assigning to each n-bit information word at least one m-bit code word having a respective NRZI disparity. The digital sum variation of the preceding m-bit NRZI code words is determined and the polarity of the conclusion of the immediately preceding m-bit NRZI code word is detected. An assigned m-bit code word is selected to represent the next n-bit information word as a function of the NRZI disparity of that code word, the determined digital sum variation and the detected polarity. The selected m-bit code word then is modulated in NRZI format such that the modulated code word has the same initial polarity as the detected polarity. The m-bit code word is selected such that its NRZI disparity, when combined with the determined digital sum variation, tends to prevent the digital sum variation from increasing.

Abstract: A digital information recording system comprises a randomized digital signal forming circuit for forming a randomized digital signal by carrying out modulo-2 addition of at least digital information signals of a plurality of channels in a digital signal and a random code sequence which is generated independently, a detector for successively detecting values of each of a predetermined number of words from each of the digital information signals of a plurality of channels in the randomized digital signal, in terms of one word, and generating a detection signal only when values of bits in the one word are all "1" or all "0", a timing circuit for generating a timing signal for every period corresponding to a transmission period of a least significant bit in one word from each of the digital information signals of a plurality of channels, a polarity inverting circuit for passing the randomized digital signal unchanged during a period in which the detection signal is not generated from the detector, and inverting t

Abstract: Apparatus and method for encoding binary data in a ternary format including ternary 0, ternary 1 and ternary 2 code symbols. In a preferred embodiment of the invention utilized for magnetic data storage, a ternary 0 is represented by the absence of signal change, a ternary 1 is represented by a single transition and a ternary 2 is represented by a pulse or pair of closely spaced transitions. Further features of the invention provide for merging ternary code symbols so as to prevent the spacing between adjacent symbols from becoming so small as to create undesirable crowding, and inserting and shifting symbols to prevent the spacing between adjacent symbols from becoming so great as to adversely affect recovery of the encoded data.

Abstract: A high speed all digital detector for Class IV partial response signalling, particularly to such detector wherein the detector recorded signals are precoded, is based upon a recognition that 1-D.sup.2 filters correspond to a pair of 1-D filters responsive to alternate bits. A detector in accordance with the present invention includes a decision making circuit for maximum likelihood sequence estimation (MLSE) that has operated at a speed of at least 120 megabits per second. Such a detector makes decisions by comparing a current signal sample S.sub.n with a stored, or pointer, signal sample S.sub.p and the prior state (T.sub.IN) of the system. When a decision as to a current sample can be made, the decision is stored serially in a memory for later reading out as part of a completely detected stream. When a decision cannot be made as to a current sample, the current sample is stored with an indication of the position of that sample in the data stream.

Abstract: The present invention provides translation circuitry, which in one mode of operation acts to encode variable length data words into fixed rate data coded words for use with a communication channel, or a recording means, such as a magnetic recording medium and which in another mode of operation acts to decode the coded words to data words. The translation circuitry functions such that in an encoding operation, the second and third bits of a three-bit coded word respectively have the same binary values as the first and second bits of the data word, which the coded word represents and the second and sixth bits of a six-bit coded word respectively have the same binary values as the third and fourth bits of the data word which the coded word represents.

Abstract: An encoder/decoder is described which allows data transmission on an A.C. coupled transmission system. The encoder converts a serial data stream comprised of combinations of logical "1"'s and "0"'s in an NRZ format to an output pulse train. The latter is characterized not only by phase reversal for each bit of data, as required for A.C. coupled systems, but by bit durations which are dissimilar for a logic "1" and "0". The encoded data is transmitted and subsequently applied to the decoder which restores the data to an NRZ format, and provides a corresponding series of clock pulses for interpreting the data. The encoder/decoder may be implemented in a simple logic configuration.

Abstract: An encoding system for converting first sequence of binary data into a second different sequence of binary data is arranged such that 4-bit data groups in a binary data sequence are converted to 6-bit data groups, and alternatively, 6-bit data groups are converted to 9-bit data groups whereby from one to seven code bits having a "0" value are arranged between any code bit having a `1` value in that converted code sequence and a code bit having a `1` value in the next code sequence.

Abstract: A method and apparatus are provided for encoding an n-bit information word into an m-bit code word, n.gtoreq.2 and m>n, wherein the DC component of successive code words is minimized. The digital sum variation (DSV) of a plurality of preceding m-bit code words is used to determine which of, for example, two m-bit code words should be generated to represent the n-bit information word to be encoded. The m-bit code word whose disparity, when combined with the digital sum variation, reduces the digital sum variation towards zero is selected.

Abstract: An encoding system for converting binary data to code sequences suitable for recording or reproducing where each 2-bit data word in a binary data sequence is converted into 4-bit codes so as thereby cause from not less than two and not greater than eight code bits of "0" value to exist between any code bit of value "1" and a next succeeding code bit of value "1" in this converted code sequence.

Abstract: A magnetic reproducing system reproduces a recording two-valued code signal from a magnetic recording medium, and detects the signal level of the reproduced signal to reproduce a digital signal of a desired two-valued code, where the recording two-valued code signal is obtained by passing the digital signal of the above desired two-valued code through a converter and a delay circuit and then feeding back this digital signal to carry out a modulo-2 addition. The magnetic recording medium is recorded with the above recording two-valued code signal.

Abstract: An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 2 bits of unconstrained into 3 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. The encoder requires a lookahead of one future input vector (2 bits) and a look back at the last channel bit generated during the immediately preceding encoding operation. The error propagation due to a random error is, at most, 4 bits in bursts of 5. The hardware implementation is extremely simple and can operate at very high data speeds.

Abstract: A unique dual track recording technique is described in which complementarily magnetically poled regions are simultaneously written in adjacent positions in two parallel tracks. Multi-track recording of magnetic data transitions in oppositely poled matched zones in the separate tracks provides a high flux coupling to a magnetic sensor. The sensor is exposed to the combined flux from both tracks. This also provides a high degree of data redundancy in the event of small physical anomalies in the magnetic medium or writing anomalies in one track or the other. Because a large magnetic field may be coupled, a magnetic sensor may be positioned at some substantial distance above the magnetic medium on which the data is recorded. This overcomes a significant problem in data reading and writing. The present limits of proximity to the magnetic medium of the sensor head or write head have been reached and still higher data density is desired.

Abstract: An improved circuit for encoding data to be stored according to a 2,7 run-length limited code is disclosed, which features substantial simplification compared with prior art circuitry. The simplified circuit uses half as many memory elements as the prior art circuit and employs Boolean identities to simplify the logic elements encoding the data. In a preferred embodiment, the circuit is implemented using emitter-coupled logic. If necessary, the capacitance required by resistor-capacitor networks used to eliminate race conditions may be formed between a planar conductor on one side of a circuit board on which the circuit is laid out and a circuit element on the other.

Abstract: A saturated flux equivalent to three amplitude level recording is attained by recording two levels by conventional saturation of the medium and the third level by writing a high frequency which erases old data and is read back as a zero level due to limited playback or read frequency response.

Abstract: A circuit is provided for encoding digital data to be recorded on high-density magnetic storage media. The circuit converts serial data to modified phase modulation encoded serial data with time encoding or write precompensation.

Abstract: A system for transmitting digital information including a coding arrangement, a transfer medium, for example a record carrier, and a decoding arrangement.In the coding arrangement the digital information is received as groups of input words which are encoded to form code words, each code word corresponding to an input word. Each code word has a time duration equal to s.tau..sub.O and each is assembled from M subgroups G.sub.m of I signal positions t.sub.mi spaced by equal time intervals .tau., where m is a number from 1 to M, inclusive, corresponding to a subgroup G.sub.m and i is a number within each subgroup G.sub.m from 1 to I inclusive. In each subgroup G.sub.m, k of these signal positions t.sub.mi are always occupied by a signal which is distinguishable from the signal in unoccupied positions, where k is an integer smaller than I (1.ltoreq.k.ltoreq.I-1). The first positions of the subgroups G.sub.m are located at mutually different time intervals .epsilon..sub.

Abstract: An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 1 bit of unconstrained into 2 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of three future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 3 bits. The hardware implementation is extremely simple and can operate at very high data speeds.

Abstract: A phase-lock loop is disclosed for synchronizing an oscillator signal with a train of input signal pulses, some of which may be missing. The phase-lock loop is of particular use in a decoder for decoding digitally encoded data employing a self-clocking coding scheme. The decoder generates a clock from the input signal stream for use in the decoding process.

Abstract: The present invention is directed to an improved method and apparatus for encoding binary data by which an improved sequence of encoded binary digits suitable for the NRZI modulation to produce a recording signal is obtained. The improved sequence of encoded binary digits obtained according to the invention consists of a plurality of binary digit blocks, each of which is formed with a predetermined number of the encoded binary digits obtained from the binary data and plural redundant codes, each of which is inserted between each successive two of the binary digit blocks, and can produce the recording signal forming a rectangular pulse train with the waveform which has the long minimum run length and does not contain the DC component or contains the diminished DC component therein when it is modulated in the NRZI modulation. By use of such a recording signal, high data density recording with a recording signal transmitted without distortions in its waveform can be achieved.

Abstract: For transferring data between a random access memory (RAM) and a rotating magnet memory on which the data are stored in tracks which can be addressed individually, the data are divided into blocks, each of which fits to one track of the magnetic memory, and each of the tracks of the magnetic memory is assigned to a different one of the data blocks. The addresses for the individual data in RAM are formed by adding the starting address indicating the beginning of the corresponding data block and the offset indicating the position of the individual data with regard to the starting address. The transfer of a data block starts at an address determined by the position of the magnetic memory when a transfer command occurs and it is performed by cyclically modifying the offset according to the number of storage locations belonging to one data block.

Abstract: Increased recording speed is possible, in a system in which an endless recording medium is used to record units of information, by dividing the medium, in the direction of its length, into at least first and second successive regions. Several units of information can be recorded during a single excursion of the endless medium by recording the first, n+1, 2n+1, 3n+1 . . . units in the first region and the second, n+2, 2n+2, 3n+2 . . . units in the second region, where n equals the total number of regions. This system is suitable for use with a recording medium which has plurality of parallel information recording tracks. Another expression to describe which information units are recorded in the jth region is (k-1)n+j, where j and k are positive integers.

Abstract: Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by squaring the audio waveform and measuring two successive time intervals occurring between three successive positive-going transitions and subtracting the resulting measurements. If the calculated difference is less than a predetermined amount, positive-going transitions of the waveform are selected as bit cell boundaries. If, on the other hand, the calculated difference is greater than the predetermined amount, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Abstract: The synchronization circuitry can be described as operating in essentially four states and is particularly useful at startup, to locate synchronization codes and spacing there between in the data flows. In operation, the synchronization circuitry looks in a data flow at startup for any sync code and, when such sync code is found, counts ahead to where the next sync code should be. If a proper sync code is found, again the circuitry counts ahead to where the next sync code should be, continuing looking at points along the data flow until a certain number (n) of properly located sync codes are discovered whereat synchronization is declared and normal playback is ordered. However, if sync codes are not located where they should be in the data flow, then such failures are subtracted from success until either (n) successes are found or a total of successes less failures reaches zero whereat the circuitry returns to the first state of looking for any sync code.

Abstract: A bi-level signal is recorded so as to minimize distortion when that signal is reproduced, comprising pre-distorting the duty ratio of the bi-level signal by increasing the duty ratio when the repetition rate of the bi-level signal increases abruptly, and then recording the distorted bi-level signal.

Abstract: A data exchange circuit to change modified frequency modulation (MFM) signals read from a magnetic memory media and converted into data pulse signals to non-return-to-zero signals. The circuit comprises an input flip-flop which receives MFM data pulse signals from a pulse forming circuit. Pre outputs of the input flip-flop is received by a phase locked loop and the other output of the input flip-flop is received by a delay circuit to vary the pulse width of the MFM pulse signal. Instruction signals are provided to the delay circuit to define data reading margins, and to accommodate variations in data widths or data shifts when no particular margin is determined. The phase locked loop synchronizes it's output when the output of the MFM data pulse signal in order to provide clock signals for non-return-to-zero data. The outputs of the phase locked loop and the delay circuit are converted to respective flip-flops in order to generate the non-return-to-zero signals.

Abstract: A method of representing decimal numbers in a quasi binary coded decimal (BCD) form is disclosed along with apparatus for using the same. The value assigned to a combination of binary bits is dependent on the location of the combination on the medium which is encoded. Use is made of the direction of motion of the medium to determine the position and hence the decimal value of specific combinations of binary bits. By interpreting certain combinations of bits in two different ways, an additional binary bit of information can be obtained from a given number of bits increasing the obtainable information from conventional BCD codes.