Abstract: To effectively suppress a signal in a low frequency region in which the medium noise and the signal distortion are concentrated, and in order to effectively utilize a detected component of the reproduced signal in the low frequency region, a target of partial response equalization to the perpendicularly recorded/reproduced signal is set so that the low-frequency component around the direct current is suppressed to a regulated quantity for both the effective suppression and the effective utilization. Accordingly, a maximum-likelihood decoding process is carried out through the target of partial response equalization. Reliability of data detection is made higher and a signal-to-noise ratio is improved, so that the noise from the recording medium can be reduced more and it is possible to provide a high-density magnetic recording/reproducing apparatus.

Abstract: Provided is a dynamic method for asymmetry compensation in a storage read channel. An asymmetry cancellation component in communication with an analog-to-digital converter receives an analog signal representing data read from a storage medium by a read head. The asymmetry cancellation component receives a digital signal from the analog-to-digital converter representing data read from the storage medium and computes an error signal indicating an asymmetry in the digital signal. The computed error signal is used to determine a coefficient. The digital signal is adjusted using the coefficient to produce a corrected digital signal.

Abstract: A method is provided for manufacturing a magneto-resistive device. The magneto-resistive device is for reducing the deterioration in the characteristics of the device due to annealing. The magneto-resistive device has a magneto-resistive layer formed on one surface side of a base, and an insulating layer formed of two layers and deposited around the magneto-resistive layer. The layer of the insulating layer closest to the base is made of a metal or semiconductor oxide. This layer extends over end faces of a plurality of layers made of different materials from one another, which make up the magneto-resistive device, and is in contact with the end faces of the plurality of layers with the same materials.

Abstract: Embodiments of the present invention provide a write-current control chip capable of effectively preventing adjacent track interference (ATI) that occurs depending on how a magnetic disk drive is used, and to provide a magnetic disk drive using the write-current control chip. In one embodiment, a write-current control chip and a magnetic disk drive using the same are provided. The write-current control chip includes: an acquisition module for acquiring the number of times of write processing in which a magnetic head writes data to a magnetic disk in the magnetic disk drive; a determination module, on the basis of the acquired number of times of write processing, for determining a write-current value used when the magnetic head writes data to the magnetic disk; and an instruction mechanism for instructing the magnetic head to write the data to the magnetic disk by use of the determined write-current value.

Abstract: To effectively suppress a signal in a low frequency region in which the medium noise and the signal distortion are concentrated, and in order to effectively utilize a detected component of the reproduced signal in the low frequency region, a target of partial response equalization to the perpendicularly recorded/reproduced signal is set so that the low-frequency component around the direct current is suppressed to a regulated quantity for both the effective suppression and the effective utilization. Accordingly, a maximum-likelihood decoding process is carried out through the target of partial response equalization. Reliability of data detection is made higher and a signal-to-noise ratio is improved, so that the noise from the recording medium can be reduced more and it is possible to provide a high-density magnetic recording/reproducing apparatus.

Abstract: A data storage device preamp circuit includes a write amplifier having an input and an output. A read amplifier has an input and an output. A loopback circuit selectively connects the output of the write amplifier to the output of the read amplifier. A read channel circuit for a data storage device includes a first counter that generates a first count of an attribute of a write signal that is output by the read channel circuit. A second counter generates a second count of the attribute of a read signal that is received by the read channel circuit. A comparator compares the first count and the second count.

Abstract: A magnetic device includes a write element having a write element tip and a conductive coil for carrying a current to induce a first field from the write element. A conductor proximate the write element tip carries the current to generate a second field that augments the first field. A driver provides the current to the conductive coil and the conductor, and a circuit phase shifts the current through the conductor relative to the current through the conductive coil.

Abstract: In a data-recording mode, a driver circuit supplies a recording head with a recording current corresponding to write data. In a degaussing mode, the driver circuit supplies the recording head with a degaussing current for eliminating the residual magnetism of the head as the recording current. The degaussing current has a rising period and falling period set longer than those of the recording current supplied in the data-recording mode.

Abstract: An equalizer coefficients generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector. An unacceptable error signal indicates a need to adjust the coefficient cyclic equalizer vector to yield an acceptable comparison of the DSS sequence and an equalization of the DSS readback sequence based on the coefficient cyclic equalizer vector.

Abstract: A thermal asperity detector for use in a hard disk drive includes a magnitude detector that produces a magnitude signal from a read head signal. A filter module filters the magnitude signal to produce a amplitude signal. A comparator compares the amplitude signal to an amplitude thermal asperity threshold and that generates thermal asperity data when the amplitude signal compares favorably to the thermal asperity threshold.

Abstract: Methods in accordance with the present invention can include determining a plurality of sets of write pre-compensation parameters. At baseline conditions, the hard disk drive can apply a first current and write pre-compensation parameters can be tuned to generate a desired write current waveform that can be applied to the read/write head to generate a magnetic field to define magnetization on the magnetic media. The hard disk drive can then apply a second current and write pre-compensation parameters can be tuned to generate the desired write current waveforms. A plurality of write pre-compensation parameters can then be generated based on the results for a plurality of corresponding temperatures and/or temperature ranges.

Abstract: The present invention provides a read channel and a drive capable of suppressing deterioration in performance of a PLL and a Viterbi decoder by using a DC component eliminating means capable of higher-speed operation than hitherto. The location of an edge is determined by using differential of a read signal, and a DC component is detected from the midpoint level of the edge. Detection of a pseudo-edge due to a long mark or space signal is prevented by limiting the absolute value of a maximum or minimum of a differential coefficient when the location of the edge is determined from the differential coefficient of the read signal. Internal operation of a DC component detector is controlled according to the state of the PLL and the magnitude of the DC component.

Abstract: A method is presented for writing data to a surface of a magnetic disk in a disk drive. The method includes determining a number of sector groups into which sectors of the data to be written will be grouped, loading registers with current values, kick-latching values, and precompensation values for each of said sector groups, and applying the current values, kick-latching values, and precompensation values for each of the sector groups to the write head while writing data to the sector groups of the recording media.

Abstract: A communications circuit comprises a first filter having a first corner frequency that is programmable. A data type identifier tracks first and second types of data flowing through the communications circuit. A control module communicates with the first filter and the data type identifier and adjusts the corner frequency of the first filter based on the first and second types of data.

Abstract: Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.

Abstract: Provided are a read channel, storage drive and method using a measured error to determine coefficients to provide to an equalizer to use to equalize an input signal. A read channel is incorporated in a storage device to process signals read from a storage medium. An equalizer uses coefficients to equalize input read signals to produce equalizer output signals. A detector processes adjusted equalizer output signals to determine output values comprising data represented by the input read signals. An equalizer adaptor is enabled to provide a reference measured error and coefficients used to produce the adjusted equalizer signals that are associated with the reference measured error. The equalizer adaptor computes new equalizer coefficients to use to equalize input read signals that result in a new measured error from the detector and computes a new measured error for the new equalizer coefficients.

Abstract: An apparatus, system, and method are disclosed for controlling gain in a magnetic media read channel. In one embodiment, a sampling module provides an asynchronous digital stream corresponding to encoded signals on a streaming magnetic medium, a stream synchronization module converts the asynchronous digital stream to a synchronous digital stream, and a gain control module processes the asynchronous digital stream and provides a gain control signal concurrent to synchronization of the asynchronous digital stream. The described apparatus, method, and system enables calibration of a read channel using a calibration signal (such as a VFO waveform) of shorter duration than attainable with currently available calibration means and methods.

Abstract: Provided is a read channel, storage drive, and method to process signals read from a storage medium. At least one data channel including an interpolator and equalizer and a servo channel includes an interpolator. A timing recovery function processes a timing error from the interpolator in the servo channel to calculate interpolation timing information used by the interpolator to interpolate a servo channel signal. A path is coupled to the timing recovery function and the interpolator in the at least one data channel to communicate the interpolation timing information to the interpolator in the at least one data channel. The interpolator in the at least one data channel is configured to use the interpolation timing information to interpolate an asynchronous data channel signal.

Abstract: Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.

Abstract: A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting data bus to notify a disk control device 2 of a conversion result via an NRZ data bus. The disk control device 2 includes means for storing the result of the analog-to-digital conversion of said servo positional signal. The positional signal of a head of the disk device is digitalized in an R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Abstract: A data storage device executes sector guarantee processing at an unexpected power supply disconnection. The sector guarantee processing can be accurately performed even if the fluctuation of power supply voltage during normal operation is high. The voltage of the power supply is monitored via an A/D converter. The control unit calculates a voltage change value, which is a relative value of the detected voltage of the power supply, and judges power supply disconnection by the level of the voltage change value, to perform sector guarantee processing. The voltage fluctuation during normal operation and the voltage fluctuation at power supply disconnection can be distinguished, power supply disconnection can be accurately detected, and write disable status can be judged.

Abstract: A dibit response estimation generator receives a DSS sequence and a DSS readback sequence, which is a function of a channel processing of the DSS sequence by a read channel. The generator generates a cyclic dibit response vector as a function of the DSS sequence and the DSS readback sequence. The generator further generates an error signal as a function of a comparison of the DSS readback sequence and a filtering of the DSS sequence based on the cyclic dibit response vector. An unacceptable error signal indicates a need to adjust the cyclic dibit response vector to yield an acceptable comparison of the DSS readback sequence and the filtering of the DSS sequence based on the cyclic dibit response vector.

Abstract: Various systems and methods for accessing data via a variable polarity head assembly are disclosed herein. As one example, a method for accessing data is disclosed that includes receiving a data set, and sampling the data set using positive synchronization to create one data set and negative synchronization to create another data set. A respective sync mark is identified in each of the data sets, and the identified sync marks are compared. Based at least in part on the comparison of the sync marks, a polarity of the data set is identified. Based on the determined polarity of the data set, the data set may be delivered in a known polarity.

Abstract: A readback system includes a magnetic sensor that receives a sensor current. The magnetic sensor senses magnetic bits at a bit frequency and generates a sensor output. The readback system includes a channel circuit that modulates the sensor current at a modulation frequency higher than the bit frequency. The channel circuit samples the sensor output and combines multiple samples of the sensor output per magnetic bit into a combined sample output.

Abstract: An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.

Abstract: A write driver (11) for a disk drive system is disclosed. The write driver (11) includes a normal H-bridge drive circuit (30) and a boost H-bridge drive circuit (32). The normal and boost H-bridge drive circuits (30, 32) are both biased from a Vcc power supply; however, system ground (GND) biases the normal H-bridge drive circuit (30), while a Vee power supply voltage, which is negative relative to system ground (GND), biases the boost H-bridge drive circuit (32). Diodes (46Y, 46X) are provided in the pull-down paths of the normal H-bridge drive circuit (30). During the boost portion of the write cycle, both of the normal and boost H-bridge drive circuits (30, 32) are on, and the pull-down current from the write head (HD) is conducted to the Vee power supply voltage. After the boost portion of the cycle, and thus after the desired overshoot current has been applied, only the normal H-bridge drive circuit (30) drives the steady-state write current, which is conducted to system ground (GND).

Abstract: A write driver circuit for a magnetic storage medium includes a first write driver sub-circuit that has an output that communicates with a first node of a write head. The first write driver circuit includes a first driver circuit and a first feedback path between the input and the output of the first driver circuit. A second write driver sub-circuit has an output that communicates with a second node of the write head. The second write driver sub-circuit includes a second driver circuit and a second feedback path between the input and the output of the second driver circuit. The write driver circuit has a substantially constant output impedance during operation, balanced differential and common mode resistances, and a substantially constant common mode voltage across the write head during operation.

Abstract: A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn?1, and Zn (n?2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn?1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier with an input, an output, and at least one stage. A feedback network communicates with the input and output of the amplifier. A feedback current cancellation module that provides a first current at the input of the amplifier that substantially cancels a second current provided at the input of the amplifier by the feedback network.

Abstract: A method for operating a tester for testing heads and disks of a magnetic recording disk drive during manufacturing calculates the readback signal amplitude asymmetry in the frequency domain without the need for measurement in the time domain with a peak detection channel. The tester first signals the write head to write a first pattern on the disk to generate a readback signal with positive pulses. The read head then detects this first recorded pattern and sends the readback signal to a spectrum analyzer connected to the tester. The tester then signals the write head to write a second pattern on the disk to generate a readback signal with negative pulses. The read head then detects this second recorded pattern and sends the readback signal to the spectrum analyzer. The spectrum analyzer measures the amplitudes of the first and second readback signals in the frequency domain using a bandpass filter.

Abstract: A write driver system comprises first switching devices that generate gate drive signals. A write driver circuit includes second switching devices that are controlled by the gate drive signals. The second switching devices have higher voltage stress thresholds than the first switching devices and wherein the second switching devices have slower switching times than the first switching devices.

Abstract: An apparatus and method for demagnetizing a write head of a disc drive. Under control of a clock oscillator, synthetic demagnetizing pulses are generated and applied to a writer-driver bridge. Also under control of the clock oscillator, a write current produced by the writer-driver bridge incorporates the demagnetizing pulses and ramps down to about zero. The train of demagnetizing pulses and the write current ramp down demagnetizes the head, reducing write head magnetic bias that may influence the proximate read head of the disc drive head.

Abstract: A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.

Abstract: A reproducing head including a read element, first and second electrodes provided at the opposite ends of the read element, a ground electrode provided between the first and second electrodes, a first constant current circuit for passing a first constant current between the first electrode and the ground electrode, and a second constant current circuit for passing a second constant current between the second electrode and the ground electrode. The reproducing head further includes a computing unit connected to the first and second electrodes for synthesizing an output from the first electrode and an output from the second electrode, and a storing unit having a table showing the relation between a synthetic value computed by the computing unit and the outputs from the first and second electrodes.

Abstract: Systems and techniques relating to interpreting signals on a noisy channel with polarity uncertainty. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes a detector operable to find a data pattern that indicates control information in a read signal and to determine a signal polarity of the read signal by determining Euclidean distances between a sampled sequence from the read signal and multiple possible sequences corresponding to preamble-shifted and polarity-reversed versions of the data pattern. The read signal is obtained from a partial response channel, such as in a storage device, and the data pattern can be a servo mark selected based on Euclidean distances between the servo mark and preamble-shifted and polarity-reversed versions of the servo mark generated according to a target channel and an encoding scheme specified for the storage medium.

Abstract: A broadband transmission path apparatus connects a head IC and a head in a suspension. Either one of the head IC and the head is assumed as a transmission terminal and the other is assumed as a reception terminal to divide a required transmission frequency band into at least two, one of which is assumed as a low band transmission path for low frequency transmission band and the other of which is assumed as a high band transmission path for high frequency transmission band. The high band transmission path forms a resonant circuit by a resistor component, an inductance component and a capacitor component of the transmission path itself, and realizes the high frequency transmission band characteristic by a resonant frequency characteristic of the resonant circuit.

Abstract: There is provided a storage apparatus and the like capable of performing control of write current and overshoot that can ensure stable and highly reliable write capability. A storage apparatus comprises: a current parameter varying section that can make a write current used for writing information on the storage medium and an overshoot amount corresponding to the write current variable; a detection section that detects an error rate or its corresponding error rate parameter for a plurality of combinations of the write current and overshoot amount varied by the current parameter varying section; a saturation factor calculation section that calculates a saturation factor representing a change in the error rate relative to a unit write current value from the error rate or error rate parameter detected by the detection section; and a current parameter setting section that determines current parameters based on the saturation factor obtained by the saturation factor calculation section for setting.

Abstract: A preamplifier that includes an input configured to receive a preamplifier control signal and a fault detection circuit configured to monitor the preamplifier control signal received at the input is provided. The fault detection circuit is further configured to identify a fault condition triggered by an improper temperature control signal provided by the preamplifier.

Abstract: A circuit (40) for use in a mass data storage device (10) has first (44) second (46) current driver circuits for providing write currents to the data transducer (18). The first and second current levels are different, the second current level being lower than the first. The first current driver circuit (44) may be used to apply currents representing user data to the data transducer (18) and the second current driver circuit (46) may be used to apply currents representing servo information to the data transducer (18). In addition, the first (44) and second (46) current drivers circuits may be operated at different frequencies. The first (44) and second (46) current driver circuits additionally may share at least some circuit components (70, 72, 74-75, 64-65), and may operate at different write speeds.

Abstract: An asymmetry compensator for measuring and correcting of asymmetry in magnetic recording devices. The magnetic recording device includes a read head, an asymmetry compensator, a data decoder, and an analog-to-digital converter. The read head produces a read data signal that contains potential errors due to asymmetry. The read data signal is processed into a compensated data signal by the asymmetry compensator. The asymmetry compensator includes a power of two squaring device, a gamma amplifier, and a summing junction connected in a feed forward manner. The gamma amplifier uses an approach involving, for a positive isolated pulse, the amplitude of the positive pulse and the undershoot and, for a negative isolated pulse, the amplitude of the negative pulse and the overshoot. The approach further involves probabilities and weights in a weighted average to account for any variations with frequency. The approach may be performed in either the analog or digital domain.

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract: Embodiments of the invention provide a hard disk drive that is capable of performing degaussing promptly and properly and a recording method for use with such a hard disk drive. A hard disk drive according to one embodiment of the present invention comprises a current source for supplying a first current, which flows to a write head for writing data onto a magnetic disk; a current source for supplying a second current, which flows to the write head when the polarity of the first current changes; transistors for reversing the polarity of a current flowing to the write head; and a control circuit for exercising control so that the second current I2, which flows from the current source to the write head when the polarity of the first current I1 is reversed, becomes approximately zero before the first current I1 converges to approximately zero during a degauss period.

Abstract: In one exemplary embodiment, a noise signal is introduced into a read-back signal when data is written to a removable data storage medium. While writing the data to the removable data storage medium, a portion of the data written to the removable data storage medium is read from the removable data storage medium. An error rate is determined based on the portion of the data read from the removable data storage medium. A read-back signal is generated corresponding to the portion of the data read from the removable data storage medium, which is used to detect if an error occurred in writing the portion of the data to the removable data storage medium. A noise signal is added to the read-back signal. The noise signal is adjusted based on the determined error rate.

Abstract: An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Abstract: A disk drive is disclosed comprising a disk having top and bottom surfaces, and top and bottom heads actuated over the top and bottom surfaces, respectively. Control circuitry detects a warping of the disk by writing a first test pattern to the top surface, reading the first test pattern to generate a first read signal, monitoring a first read signal value proportional to an amplitude of the first read signal, writing a second test pattern to the bottom surface, reading the second test pattern to generate a second read signal, monitoring a second read signal value proportional to an amplitude of the second read signal, and processing the first and second read signal values to detect a negative correlation between the amplitudes of the first and second read signals.

Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.

Abstract: Method and apparatus for processing transmitted data. A sampling circuit preferably performs lossy sampling of a continuous signal to provide a corresponding sequence of discrete samples at a sampling rate less than a Nyquist rate of the continuous signal. A processing circuit reconstructs an informational content of the continuous signal from the discrete samples, and operates to periodically insert additional samples into the sequence, which preferably increases an effective rate of said sampling to match or exceed the Nyquist rate. Preferably, the lossy discrete samples are temporarily stored in a memory space prior to reconstruction by the processing circuit. The sampling circuit preferably comprises an analog-to-digital converter (ADC) of an analog front end (AFE). The processing circuit preferably comprises a digital back end (DBE) employing partial-response, maximum-likelihood (PRML) detection. The additional samples are preferably provided by an iterative timing recovery (ITR) block of the DBE.

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

Abstract: Apparatuses and methods for detecting reference marks on magnetic data storage mediums are described herein. In one variation, the apparatus comprises a magnetic servo position demodulator operable to extract information from the magnetic data storage medium utilizing Partial Response/Maximum Likelihood (PRML) technique. Synchronization marks stored within the PRML channel is then detected utilizing a digital filter. For each of the detected synchronization mark, a further refined position of the synchronization mark can be determined utilizing a mathematical prediction model.

Abstract: A reproducing apparatus, in which a reproduced information signal is equalized by an equalizer, includes a detecting circuit for detecting a digital signal from the reproduced information signal, and a controller for controlling an equalizing characteristic of the equalizer according to the reproduced information signal to be inputted to the detecting circuit and a detection result of the detecting circuit.