Abstract: A write driver system includes a logic circuit including first switching devices which receive input write signals and generate control signals. A plurality of predriver circuits includes second switching devices and generates drive signals based on the control signals. A write drive circuit includes third switching devices and generates write drive signals based on the drive signals. The third switching devices have higher threshold voltages than the first and second switching devices.

Abstract: A method for providing feedback current cancellation comprises providing an amplifier with an input, an output, and at least one stage, feeding back a first current based on the output of the amplifier to the input of the amplifier, and substantially cancelling the first current by supplying a second current to the input of the amplifier.

Abstract: A method of setting up a pre-amplifier for a hard disk drive and a hard disk drive incorporating the method. A serial interfacing mode of the pre-amplifier is checked by writing and reading data to/from the pre-amplifier. A chip ID of the pre-amplifier is checked and a vendor of the pre-amplifier is identified using the chip ID. Default values of the pre-amplifier stored in a ROM and adaptive codes of the pre-amplifier are automatically downloaded to a register of a hard-disk controller, simplifying the pre-amplifier installation and reducing errors which may occur during manual installation of the pre-amplifier.

Abstract: A method and apparatus for measuring latency in a communication path is provided. The technique includes driving a signal such as a square wave on the communication path, such as a write path such that it travels around the write-read path, and sensing a returned signal at one end of the write-read path. A square wave signal corresponding to the square wave driven on the write path is delayed by a predetermined phase thus generating a delayed signal. The returned signal and the delayed signal are mixed, producing a mixed signal. The mixed signal is integrated to obtain an integrated output. The phase by which the delayed signal is shifted is successively adjusted. Returned signals are mixed with such delayed signals until the integrated output is equal to zero. The phase shift amount that results in a nulled integrated output, less a quarter cycle of the square wave, is equal to the round trip latency of the write-read path.

Abstract: Apparatuses, circuitry, architectures, systems, methods, algorithms and software for performing automatic gain calibration on an input signal. The apparatuses and/or circuits generally include an amplifier, a filter, a comparator, and a controller. The amplifier is configured to receive a gain level signal and to amplify the input signal in accordance with the gain level signal to produce an amplified signal. The filter is configured to filter the amplified signal to produce a filtered signal. The comparator is configured to compare the filtered output to a threshold value and to produce a comparison signal in response thereto. The controller is configured to iteratively reset the filter and adjust the gain level signal in response to the comparison signal to select a gain level.

Abstract: Method, apparatus and computer program product adjust gain in a read channel of a magnetic media data storage device. A digital signal sample having a data-dependent noise component is received. A gain value, stored in a location in a gain table, is selected in a data-dependent manner. The gain of the signal sample is adjusted in response to the selected gain value. A bit pattern is detected from the gain-adjusted signal sample and a data output signal is output based upon the detected bit pattern.

Abstract: A head IC, which adjusts an amplitude level of a read signal of a head, for outputting to a read channel having an AGC amplifier, includes: a differential amplifier; an AGC circuit; external gain setting sections; and a switch. Since the AGC amplifier is disposed in the head IC, the amplitude from the head is automatically adjusted in the head IC, and the signal level, which enters the input dynamic range of the AGC amplifier of the read channel, can be adjusted. The AGC amplifier can be operated as a fixed gain amplifier using a gain value which is set from the outside, so the power consumption can be minimized even if automatic adjustment is performed.

Abstract: Various embodiments of the present invention provide systems and methods for write pre-compensation. For example, various embodiments of the present invention provide systems for on-the-fly estimation of write pre-compensation values. Such systems include a magnetic storage medium, a read/write head assembly disposed in relation to the magnetic storage medium, and an analog to digital converter that receives an analog signal from the read/write head assembly corresponding to a data set stored on the magnetic storage medium and provides a series of digital samples corresponding to the data set. The storage devices further include a read data processing circuit that receives the same series of digital samples and provides a user data output, and a pre-compensation value calculation circuit that receives the series of digital samples and provides an updated write pre-compensation value.

Abstract: Methods and apparatus for temperature compensation for hard disk drive writer overshoot current are disclosed. A disclosed system comprises creating a first delay based on the temperature of the hard disk drive, creating a second delay based on the temperature of the hard disk drive, and creating a pulse based on the first and second delay.

Abstract: A head IC adjusts an amplitude level of head read signals with regard to scattering in head output characteristics, so as to conform to the input dynamic range of the read channel AGC. An AGC amplifier is provided in a head IC connected to a read channel, and the feedback response speed of the AGC circuit of the head IC is set to be substantially slower than the feedback response speed of the AGC circuit of the read channel. Within the head IC, the amplitude of signals from the head is automatically adjusted, enabling adjustment of the input signal level to the input dynamic range of the AGC amplifier of the read channel. The AGC circuit of the head IC has no effect on the faster AGC operation of the AGC circuit of the read channel.

Abstract: A method for testing operation of a preamplifier circuit includes generating a first symbol, converting the first symbol into a write signal, transmitting the write signal to a write signal input of the preamplifier circuit, and looping the write signal back to a read signal output of the preamplifier circuit.

Abstract: A driver for driving a load over a transmission line, such as driving the magnetic head of a hard disk drive. The driver includes a signal switch for switching the signal to the load during a signal period, and a boost switch for boosting the signal during a boost period, so as to decrease rise time of the signal at the load by deliberately injecting an overshoot. A switchable protection device protects the signal switch and the boost switch. The protection device includes a reflection-suppression switch which is pulsed during a time corresponding to the expected return of a reflection corresponding to the overshoot signal, so as to force the protection device into saturation mode. Since the protection device is in the saturation mode during the return reflection of the boost signal, the returned reflection sees a matched impedance and thus reduces a re-reflection back to the load.

Abstract: Removing magneto-resistive asymmetry (MRA) from a signal is disclosed. Removing MRA includes determining an estimated offset error associated with error due to offset in the signal, determining an estimated signal error associated with error due to offset and MRA in the signal, and removing at least a portion of MRA from the signal based at least in part on the estimated offset error and the estimated signal error.

Abstract: A head IC adjusts an amplitude level of a read signal of a head and outputs the adjusted signal to a read channel having an AGC amplifier. A head IC includes: a differential amplifier; an AGC circuit; external gain setting sections; and a switch. The AGC amplifier is disposed in the head IC, and the amplitude from the head is automatically adjusted in the head IC. The signal level can be adjusted within the input dynamic range of the AGC amplifier of the read channel. An estimated gain value converted from a result of measuring a resistance value of the head is used as an initial value for the adjustment of the AGC amplifier. It becomes possible attempting to prevent an increase in the lock-in times of the AGC, to guarantee stability, and to prevent judgment errors of the AGC.

Abstract: A write current circuit (300, 400) adapted to drive a thin film write head (202) of a mass media information storage device. The write current circuit (300, 400) further includes programming circuitry (311, 411) driven such that parameters of the write current waveform can be varied, including the write current overshoot amplitude and/or overshoot duration. The present invention achieves technical advantages by providing the ability to program out or adjust for system introduced asymmetries in the write current waveform.

Abstract: A point of sale terminal includes a microcontroller integrated circuit. In one aspect, a regulator within the IC receives power from a supply voltage terminal and/or a battery terminal. If the regulator does not receive adequate power from either terminal, then energy stored on-chip in a capacitor is used to erase secure memory. In another aspect, pulses of current are made to pulse through conductors of a conductive mesh. A tamper condition is detected if an improper voltage is detected on the IC terminal through which the pulse is conducted. In another aspect, each vendor signs his/her firmware with his own vendor ID. A bootloader uses the vendor ID to lookup a public key that is then used to verify a private key supplied by the firmware to be executed. In another aspect, a magnetic card reader includes a digital peak detector circuit involving programmable positive and negative thresholds.

Abstract: Baseline wander is removed. A first decision signal is generated from an input signal using a first detector. Baseline wander associated with the input signal is estimated using the first decision signal. The estimated baseline wander is removed from the input signal. A second decision signal is generated from the input signal with the baseline wander removed using a second detector.

Abstract: One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system comprises a read amplifier configured to generate a read signal corresponding to data that is read from a magnetic disk via a magneto-resistive (MR) read head. The system also comprises a gain control amplifier that is configured to amplify the read signal based on a digital gain value to generate an amplified read signal. The system further comprises a feed-forward automatic gain controller (AGC) configured to set the digital gain value based on an amplitude of the read signal.

Abstract: A magnetic storage circuit comprises a preamplifier writer that selectively generates a write current that has a boost stage and a settling stage. An impedance changing circuit communicates with the preamplifier writer and provides a lower resistance value during the boost stage and a higher resistance value during the settling stage.

Abstract: One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.

Abstract: Embodiments of the present invention reduce lowering of a recording current and a recording magnetic field that might occur upon execution of write pre-compensation for compensating the NLTS according to a perpendicular magnetic recording method. According to one embodiment, the recording current overshoot is increased for recording a high NLTS recording data pattern. The read signal quality is improved, thereby a highly reliable magnetic disk can be provided.

Abstract: A head IC adjusts an amplitude level of a read signal of a head and outputs to a read channel having an AGC amplifier, includes an AGC amplifier. The AGC amplifier has a feedback loop control type first amplifier and a feed-forward control type second amplifier. The precision of control with respect to a target value is improved, and an AGC amplifier with fast response can be configured. Further, increases in the AGC pull-in type can be prevented, stability can be assured, and erroneous AGC judgments can be prevented.

Abstract: A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Abstract: A magnetic head, includes a magnetic oscillation element, the oscillation frequency of which is modulated by a medium magnetic field, and a reproducing device configured to detect a phase difference between the adjacent oscillation signals derived from the magnetic oscillation element and output a phase difference signal as a reproduced signal.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

Abstract: According to an aspect of an embodiment, a storage apparatus has a storage for storing a plurality of compensation values in association with a plurality of bit sequence patterns, a head for writing data into a medium and a controller for controlling the apparatus and driving the head, the controller determining whether to use one of the compensation values to drive the head to write an instantaneous data bit in dependence upon the immediate preceding data bits in reference to the bit sequence patterns.

Abstract: A controller for use in a disk drive includes a comparison signal generator for comparing a period of time when a write unsafe signal output from a pre-amplifier is activated with a reference period of time to generate a comparison signal; a write failure signal generator for generating a write failure signal according to a write gate signal and the comparison signal; and a logger for logging at least one of the period of time when a write unsafe signal output from a pre-amplifier is activated and the number of times of activations of the comparison signal.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response can include generating multiple asymmetry matrices that model asymmetry in a received analog signal, including an effect of asymmetry spreading in a read channel; comparing the multiple asymmetry matrices; and selecting indicators of asymmetry from the matrices based on the comparing. Systems and techniques can include saving in memory an indication of the selected indicators of asymmetry.

Abstract: A read-channel module includes a variable-gain amplifier (VGA) module, an analog-to-digital converter (ADC) module, an amplitude measuring module, a gain adjusting module, and a zero phase start (ZPS) module. The VGA module has a variable gain, amplifies input signals, and generates amplified signals. The ADC module converts the amplified signals from analog to digital format and generates samples. The amplitude measuring module receives N of the samples and measures amplitudes of the N samples, where N is an integer greater than 1. The gain adjusting module communicates with the amplitude measuring module and selectively adjusts the variable gain of the VGA module based on the amplitudes. The zero phase start (ZPS) module communicates with the amplitude measuring module, receives the samples, and selectively generates phase information from the samples based on the amplitudes.

Abstract: A method and an apparatus for improving performance of a hard disk drive at low temperature are provided. The method includes: measuring an internal temperature of the hard disk drive; checking whether a measured internal temperature is not more than a predetermined critical temperature; if the measured internal temperature is not more than the predetermined critical temperature, driving a motor of the hard disk drive for a predetermined time and proceeding to the operation of the measuring of the internal temperature of the hard disk drive; and if the measured internal temperature is greater than the predetermined critical temperature, determining that reading/writing operations with respect to the hard disk drive are available.

Abstract: One embodiment of the invention includes a preamplifier system for a magnetic disk-drive. The system includes a current distributor configured to generate a reference current and to decay the reference current from a first magnitude to a second magnitude during a degauss period to degauss a magnetic disk write head. The degauss period defines a transition from a write cycle to a read cycle of the magnetic disk-drive and has a predetermined time duration that is independent of the first magnitude of the reference current during the write cycle. An output driver is configured to provide a write current to the magnetic disk write head having a magnitude with an absolute value that is based on the reference current.

Abstract: A signal processing circuit performs processing for an analog signal output from a head. The signal processing circuit includes: a conversion section that generates a digital signal based on the analog signal; a first filter that equalizes the output of the conversion section; a demodulation section that demodulates data from the output of the first filter; a modulation section that modulates a waveform based on the data demodulated by the demodulation section; a second filter that equalizes the output of the modulation section; and an adaptation section that adapts the response of the second filter such that the output of the second filter becomes equal to the output of the conversion section.

Abstract: A printed circuit cable assembly (PCCA) for a hard disk drive (HDD) is disclosed. The PCCA includes a stiffener portion having an elongated shape that includes an integrated circuit (IC) chip. The PCCA also includes a flexible portion extending from the elongated stiffener portion, wherein the PCCA is configured to be mountable on a headstack of the HDD such that an entire footprint of the IC chip overlays a metallic portion of the headstack of the HDD.

Abstract: An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the writing circuit (334) for sequentially receiving the main data and the parity data, and outputting to the storage apparatus via a write pre-compensation unit (305), a driver (306), and the like.

Abstract: A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.

Abstract: A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel.

Abstract: In a method for causing data to be written to a non-volatile medium, an indication of a size of a sector or a sector fragment may be transmitted to a channel device, and an indication of a size of a codeword to be written in the sector may be transmitted to the channel device. Data to be iteratively encoded and written in the sector as the codeword may be transmitted to the channel device. A write gate signal corresponding to the sector or the sector fragment may be transmitted to the channel device to indicate to the channel device when to write to the sector or the sector fragment.

Abstract: Systems and techniques relating to interpreting signals on a noisy channel with polarity uncertainty. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes a detector operable to find a data pattern that indicates control information in a read signal and to determine a signal polarity of the read signal by determining Euclidean distances between a sampled sequence from the read signal and multiple possible sequences corresponding to preamble-shifted and polarity-reversed versions of the data pattern. The read signal is obtained from a partial response channel, such as in a storage device, and the data pattern can be a servo mark selected based on Euclidean distances between the servo mark and preamble-shifted and polarity-reversed versions of the servo mark generated according to a target channel and an encoding scheme specified for the storage medium.

Abstract: A disk drive is disclosed comprising a disk including a plurality of servo sectors, a head actuated over the disk, the head for generating a read signal, and a gain control circuit for adjusting a gain of the read signal in response to a gain setting. A bias setting is initialized for the head, and the gain setting for the read signal is initialized. The read signal is processed to detect at least one of the servo sectors, and when at least one of the servo sectors is not detected, the gain setting is adjusted. The read signal is processed with the adjusted gain setting to detect at least one of the servo sectors, and when at least one of the servo sectors is not detected with the adjusted gain setting, the bias setting is adjusted in response to the adjusted gain setting.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.

Abstract: A system includes an amplifier and a feedback network that includes a first resistance having one end that communicates with an input of the amplifier and an opposite end that communicates with an output of the amplifier. A first replica circuit provides a replica of a DC characteristic at the output of the amplifier. A second replica circuit provides a replica of a DC characteristic at the input of the amplifier. An input of a first buffer communicates with the first replica circuit, and an input of a second buffer communicates with the second replica circuit. A second resistance communicates with an output of the first buffer and an output of the second buffer. A first current source provides a first current at the input of the amplifier that is proportional to a second current flowing through the second resistance.

Abstract: A current mirror circuit providing a fast turn on time. A node within the circuit is held at a first voltage when the current mirror is off to permit the node voltage to quickly reach a necessary value when the current mirror circuit is turned on.

Abstract: Methods and apparatus to provide dynamically biased write drivers for hard disk drive applications are described. According to one example, a hard disk drive write system includes a drive signal generator to receive data to be written to a hard disk drive platter and to generate drive signals including a boost signal. A drive circuit is configured to receive the drive signals and to generate currents for output to the transmission line based thereon, wherein the currents include a boost current. A variable bias circuit is configured to detect the boost signal generated by the drive signal generator and to vary a bias signal provided to the impedance matching circuit based on the detection of the boost signal. In such an example arrangement, the impedance matching circuit matches impedances between the drive circuit and the transmission line in response to the bias signal provided by the variable bias circuit.

Abstract: An apparatus and method are disclosed for decoding servo data recorded on a magnetic disk drive and detecting pinned layer reversals and signal errors, for example, errors due to noise. The servo data is encoded using wide-bi-phase encoding. This encoding is detected by a magneto-resistive sensor that senses the magnetization in domains passing by the sensor. The decoder includes an A/D converter for sampling the signals emitted by the sensor, to provide a sequence of the encoded data. A trellis, such as a Viterbi trellis, is employed to decode the samples generated by the converter. The trellis includes nodes representing states, connected by paths representing transitions, among the nodes. A quality value is generated for the transitions, the quality value representing the distance between each sample in the sequence output by the A/D converter and a corresponding expected sample.

Abstract: A storage drive implements a method for operating the storage drive between a plurality of operational modes. For a test mode of the storage drive, a write current driver circuit and a test current sensor are electrically connected to the write head, wherein the test current sensor generates a sense signal indicative of a degree of a flow of a test current through the write head to thereby facilitate a detection of any presence of an open write condition of the storage drive (i.e., any impedance condition impeding a flow of a write current through the write head). For a write mode of the storage drive, the write current driver circuit is electrically connected to the write head and the test current sensor is electrically disconnected from the write head, wherein the write head records data on a magnetic media based on a flow of the write current through the write head.

Abstract: Embodiments of the present invention allow for media erasure. Various embodiments allow for controlling an actuator based on feedback signal measurements and disk phase to seek a head across a surface of a disk systematically for an erasure operation. Also, in various embodiments, a substantially repeatable seek motion of a head across a stroke may be determined, and launch points at which the head is launched over a disk in the seek motion for erasing at least a portion of the disk are determined based on disk phase.

Abstract: A recording system employing a magneto-resistive (MR) element senses a resistance value of the MR element and generates one or more MR resistance (MRR) signal values based on the sensed MR element resistance value. The MRR signal values might be, for example, current or voltage values proportional or inversely proportional to the MR element resistance value. The MRR signal values might be employed to control one or more of: i) a unity gain bandwidth of a bias loop for the MR element, ii) an MR read head preamplifier low corner frequency, and iii) a slew rate across the MR element.

Abstract: One embodiment of an equalizer circuit has an FIR filter 116 in the asynchronously oversampled domain with a filter coefficient adaptation module that adapts the filter coefficients to the transfer function of a data read channel. Applications include tape drives, drives for optical and magnetic discs as well as receivers. The filter adaptation is performed on the basis of an error signal delivered by a slicer 128 which operates on synchronous samples after timing recovery and sample reconstruction.

Abstract: A disk drive controller including a preamplifier and a controller is disclosed, in which communications between the controller and the preamplifier are carried out over at least some shared terminals and conductors. A first pair of differential lines is provided to communicate data, sensed at read/write heads of the disk drive, from the preamplifier to the controller, and a second pair of differential lines communicates data to be written to the disk drive from the controller to the preamplifier. Control signals are communicated over a serial interface between the controller and preamplifier, over the first pair of differential lines, so that serial communication can be carried out simultaneously with the writing of data from the controller to the preamplifier. Alternatively, the control signals are communicated over the second pair of differential lines, simultaneously with the reading of data from the preamplifier to the controller.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. Baseline wander of the signal is corrected sequentially by each of the plurality of baseline wander correcting units. At least a baseline wander correcting unit placed in the initial stage may correct baseline wander by a feedback control. The baseline wander correcting units correct the baseline wanders, respectively, so that the wander of baseline can be efficiently corrected.