Abstract: A communications circuit includes a first filter having a corner frequency that is adjustable. A data type identifier that tracks first and second types of data flowing through the communications circuit. A control module that adjusts the corner frequency of the first filter to provide alternating current (AC) coupling during the first type of data and adjusts the corner frequency of the first filter to provide direct current (DC) coupling during the second type of data.

Abstract: An apparatus and method for controlling the common mode voltage across a data storage device write head. The write current is supplied by a first plurality of parallel current sources each independently activated to limit the common mode voltage generated across the write head. A plurality of parallel resistive elements responsive to current supplied by a second plurality of parallel current sources bias an output transistor that further controls the write current. Each of the plurality of parallel resistive elements and each of the second plurality of parallel current sources is also independently activated to limiting the common mode voltage generated across the write head.

Abstract: A storage apparatus comprises: a current parameter varying section that can make a write current used for writing information on the storage medium and an overshoot amount corresponding to the write current variable; a detection section that detects an error rate or its corresponding error rate parameter for a plurality of combinations of the write current and overshoot amount varied by the current parameter varying section; a saturation factor calculation section that calculates a saturation factor representing a change in the error rate relative to a unit write current value from the error rate or error rate parameter detected by the detection section; and a current parameter setting section that determines current parameters based on the saturation factor obtained by the saturation factor calculation section for setting.

Abstract: A circuit includes a slider, a data storage medium and a contact detection circuit electrically coupled to the slider and to the data storage medium. The contact detection circuit is configured to sense an electrical current indicative of contact between the slider and the data storage medium and responsively provide a contact detection output. The electrical current is produced without the application of a separate voltage between the slider and the data storage medium.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes a digital filter that receives a series of digital samples and provides a filtered output. The filtered output is provided to a data detector that performs a data detection on the filtered output to create a detected output. A first summation element subtracts the filtered output from the detected output to create an error signal, and a second summation element subtracts the error signal from the filtered output to create a wander basis signal. A baseline correction feedback circuit receives the wander basis signal and provides a wander compensation signal. A derivative of the wander compensation signal is provided as feedback to the digital filter.

Abstract: A signaling apparatus and method are described that use reflected signals to increase the total current delivered to a receiver. Dynamic source-side transmission line termination control is employed to generate reflected signals that constructively add to a nonreflected signal to enhance the signal at the receiver. Switching controls selectively connect and disconnect the transmission line source-side termination resistors to either provide signal termination or remove it. Driver designs using either voltage or current sources for use in signaling systems (including, for example, magnetic storage devices with inductive coil based write heads) are described.

Abstract: A preamplifier circuit for a disk drive system is disclosed. The preamplifier circuit has first and second inputs that sense the voltage on either side of a magnetoresistive (MR) head element, which presents a varying resistance according to the localized magnetic field at a nearby disk surface. The preamplifier circuit includes a programmable input impedance circuit, which presents an impedance in parallel to feedback impedance at each of the first and second inputs. The parallel impedance presented by the programmable input impedance circuit is controlled by controlling a current source in the programmable input impedance circuit; a higher current results in a lower input impedance.

Abstract: Apparatus, systems, and methods implementing techniques for converting a signal. In an apparatus form, an input circuit receives a differential input signal and produces a single-ended intermediate signal. An amplifier circuit receives the intermediate signal and produces an amplified signal, and a feedback path couples the amplified signal to the intermediate signal. An inverter circuit receives the amplified signal and produces an output signal.

Abstract: Embodiments of the present invention provide a mixed-mode amplifier for amplifying signals in data storage devices such as disk drives. In one embodiments, a circuit for amplifying data signals comprises a magnetoresistive sensor having a bias voltage applied thereto; a signal amplifier which amplifies a signal detected by the magnetoresistive sensor having the bias voltage applied thereto; a feedback control block which is coupled to an output of the signal amplifier and outputs a feedback current used to vary a loop gain of the circuit; a bias setting circuit which outputs a bias setting current; and a transimpedance amplifier which receives the bias setting current from the bias setting block and the feedback current from the feedback control block and generates the bias voltage applied to the magnetoresistive sensor.

Abstract: Provided is a highly reliable disk array device.

Abstract: Apparatus and computer program products are provided to monitor and report performance data of a device such as a data storage drive. A plurality of quantitative values are obtained from feedback and measurement mechanisms in a data storage device of a first model during operation of the storage device. The plurality of quantitative values are normalized. Then, one or more qualitative values are generated from one or more normalized quantitative values and evaluated against corresponding baseline performance values established for the first model.

Abstract: Embodiments of the invention control a recovery procedure effectively in accordance with write conditions. In one embodiment, the data to be written into a sector includes not only user data but also recording condition data, which indicates the temperature prevalent during a write. If a data read is not accurately performed, a recovery procedure is executed. If a data read is accomplished by a retry and the temperature prevalent during a write is lower than predetermined, it is concluded that the employed medium is nondefective. Thus, the read data is rewritten into the same sector without being stored in a spare area. This prevents the spare area from being unnecessarily consumed.

Abstract: Disclosed is a self servo-writing disk drive that pre-programs a preamplifier to improve servo-writing characteristics in writing servo sectors to a disk. The disk drive implements operations including: writing servo sectors to define track bands according to sets of write setting values wherein the preamplifier adjusts write signals utilizing a set of write setting values for each track band; reading servo variable gain amplifier values from the tracks bands; selecting a set of write setting values associated with a minimum servo variable gain amplifier value; programming the preamplifier's write settings with the selected set of write setting values; and self-servo writing the disk with servo sectors utilizing the selected set of write setting values that are pre-programmed in the preamplifier.

Abstract: A circuit is adapted to activate a writer head of a data storage media drive during both the boost periods as well as the steady state periods. The current supplied to the writer head during the boost periods exceeds the steady state current and flows between positive and negative voltage supplies so as to provide the required magnetic flux change in the inductor disposed in the write head. During the steady state periods, a switch circuit is turned on to provide a second current path across the writer head. During the steady state periods, the current flows between the positive voltage supply and the ground to reduce power consumption. The switch circuit is turned off during the boost periods.

Abstract: The disclosure is related to detecting a fault condition of a transducer for reading and writing data to a data storage medium. The fault condition can be detected based on a potential difference between a reference voltage and a common mode of the transducer.

Abstract: A system includes a hard disk controller (HDC) module that controls a hard disk and a read channel (RC) device that communicates with the HDC module via a read bus and a write bus. The RC device includes a loopback circuit that selectively loops back the write bus to the read bus. The RC device generates a write clock for the HDC module to write data on the write bus and a read clock for the HDC module to read the data on the read bus, wherein the write clock is independent of the read clock.

Abstract: A system reads data from a magnetic storage media. A read head reads data from the magnetic storage media and produce an analog signal. A variable gain amplifier amplifies the analog signal. An offset adjust module substantially centers the amplified analog signal to a midscale. A Magneto Resistive Asymmetry (MRA) collection module MRA corrects the amplified analog signal. A Continuous Time Filter (CTF) compensation module processes the amplified analog signal. An Analog to Digital Converter (ADC) samples the amplified analog signal based upon a control signal to produce a digital signal. A Disk Lock Clock (DLC) system produces the control signal to the ADC. The control signal is representative of a frequency offset caused by at least one servo wedge rate error. A Finite Impulse Response (FIR) filter module filters the digital signal. A sequence detector processes the digital signal and detects a bit sequence from the digital signal.

Abstract: Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values.

Abstract: A recording current optimization method to optimize a recording current according to a change of a driving voltage applied to a pre-amplifier that generates the recording current supplied to a head, a recording medium storing a program that executes the method, and an apparatus that employs the method. The method of optimizing the recording current provided to the recording head of the hard disk drive includes detecting a driving voltage of the pre-amplifier, determining a voltage difference between the detected driving voltage and a reference driving voltage of the pre-amplifier, and optimizing the recording current according to the determined voltage difference. The recording current is adaptively optimized according to the change of the pre-amplifier driving power to provide the recording current to the head such that adjacent track erasure (ATE) and weak write (WW) are prevented from occurring due to the change of the driving power.

Abstract: An apparatus and method for determining a resistance of a magneto-resistive head. A current drawn by the head, in response to a fixed bias voltage across the head, is converted to a zero temperature coefficient current such that when supplied to a resistor connected to an input terminal of a comparator the effects of variations in the resistance value are avoided. An output signal of the comparator indicates the resistance of the magneto-resistive head.

Abstract: Circuits and methods are provided for write through drivers in disk drive systems. A write through driver is a transceiver that includes a write driver circuit and a receiver circuit. The write driver drives a current signal to a write element through a first conductive interconnect. The write element writes data patterns to a magnetic hard disk in response to the current signal from the write driver circuit. The current signal returns to the receiver circuit through a second conductive interconnect. The return signal can be used for the diagnosis of write-safe conditions.

Abstract: A disk drive is disclosed including a disk having a plurality of data tracks, wherein each data track comprises a plurality of data sectors and a plurality of servo sectors, and each servo sector comprises a plurality of servo bursts. A data path comprising a data decoder decodes a data read signal generated as a head passes over the data sectors, and a servo path demodulates a servo read signal generated as the head passes over the servo bursts. The servo path comprises a low pass filter operable to extract a low frequency component from the servo read signal, wherein the low pass filter does not operate on the data read signal. The servo path further comprises a subtractor operable to subtract the low frequency component from the servo read signal to generate a servo burst signal, and a servo demodulator operable to demodulate the servo burst signal.

Abstract: There is provided a magnetic disk device or the like which is capable of improving signal quality by suppressing occurrence of erasure of adjacent tracks due to spreading of a writing spot. The magnetic disk device is capable of controlling a steady state value of a write current for writing into a magnetic disk, an overshoot value, or a width thereof. The magnetic disk device comprises a VMM measurement section that measures a VMM, and a write current setting section that sets the write current, based on a value of the VMM measured by the VMM measurement section, such that a data writing spot is prevented from spreading during writing into the medium and occurrence of side erasure is prevented.

Abstract: A recording current to be supplied to a magnetic head is regulated by a signal output control unit. A peak value (either of positive-going peak value and a negative-going peak value) is detected in each pulse of a digital signal resulting from analog-to-digital conversion of a servo signal recorded on a servo band of a magnetic tape. The peak value is transmitted as an input value which is allowed to follow a change in the peak value as long as a frequency calculated based upon times of detection of respective peak values is below a predetermined frequency. An output value of the recording current is determined based upon the transmitted input value.

Abstract: Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer is in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Abstract: A method for preventing electrical overstress from interfering with a magnetic read-write device by identifying one or more characteristic functions of the device that characterize electrical overstress, generating a wave form representative of the electrical overstress by using the one or more characteristic functions and enabling the generated wave form to be combined with a read signal to counteract the electrical overstress. The method can be implemented with a crosstalk cancellation circuit that includes a coupler filter configured to receive signals from the write driver, a differentiator to differentiate the signal, a gain adjust coupled to the coupler filter configured to adjust gain on the received signal, a phase adjust configured to adjust the phase to match the crosstalk, and an inverter coupled to invert the matched signal to enable cancellation of the crosstalk.

Abstract: Provided is a read channel incorporated in a storage device to process signals read from a storage medium. The read channel includes an equalizer equalizing input read signals to produce equalizer output signals. A detector senses an adjusted equalizer output signal to determine an output value comprising data represented by the input read signals. An equalizer adaptor receives the output value from the detector to determine a first error signal used to adjust the equalizer operations. A component adjusts the equalizer output signals being transmitted to the detector, wherein the component is adjusted by a second error signal calculated from the output value from the detector, wherein the first and second error signals are different.

Abstract: A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

Abstract: A dynamic threshold detector for a magnetic storage medium comprises a transition detector that receives data comprising pairs of values based on data received from the magnetic storage medium, each of the pairs of values including a first value and a second value, and that determines states of the first and second values in the pairs. A threshold selector varies a magnitude of a threshold based on the determined states.

Abstract: In an apparatus for recording and regenerating data, a pass metric is calculated based on a likelihood converted from a previous calculation result iteratively until all pass metrics of the same data recorded many times on a recording medium are calculated, and then data recorded on the recording medium is decoded.

Abstract: Values for baseline write current and/or kick amplitudes from the baseline are determined for each head for each disk sector it writes and stored in a table. The values are determined so as to achieve a desired overwrite level. During operation, the values are looked up and applied to the heads depending on the particular sector being written. The values may be dynamically varied for temperature deviations from a baseline value.

Abstract: An amplifier for amplifying a differential input signal. The amplifier comprises a parallel configuration of a first and a second transistor differential amplifier, each responsive to a different DC bias current, wherein a gain of the amplifier is based on a sum of the transconductance of each of the first and the second differential amplifiers.

Abstract: Magnetic tape read channel signal values are developed employing intermediate bits of the path memory of a PRML Viterbi detector. Identification logic identifies a most likely path memory state of the PRML Viterbi detector from the path metrics of the PRML Viterbi detector. An intermediate bit sequence of the identified most likely path memory state is obtained, the intermediate bit sequence extending from an initiation point of the path memory which is intermediate the output and the input of the PRML Viterbi detector. A sample value is determined which corresponds to the obtained intermediate bit sequence.

Abstract: A partial response is utilized to record information on a medium and then regenerate the information from the medium. A regenerating system undergoes equalization including subjecting a regeneration signal from the medium to the convolution of (k?s·D) (where D is one (1) bit delay operator, and k and s are positive integer). Such convolution is performed in the regenerating system so that low-frequency band noises are reduced with an improved error rate. The information is decoded from the equalized signal by use of maximum-likelihood detection.

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

Abstract: A method for optimizing read/write channel parameters of a hard disk drive. The process includes measuring a first bit error rate of a head using an initial set of read/write channel parameters and varying all of the read/write channel parameters with a random jump. The random jump may be created from the generation of a random number. The process then includes measuring a second bit error rate of the head using the varied read channel parameters and accepting the varied read/write channel parameters as the new optimum, if the second bit error rate is lower than the first bit error rate.

Abstract: A read/write channel for a hard disk drive comprising at least one analog read component and a fly height control system. The fly height control system controls fly height based on a current fly height value generated based on a fly height measurement signal that passes through the at least one analog read component. The read/write channel comprises a calibration signal generator and a processor. The calibration signal generator generates a calibration signal that is coupled to the at least analog read component to place the read/write channel in a calibration mode. The processor generates compensation data based on an output of the at least one analog read component when the read/write channel is in the calibration mode. The processor generates the current fly height value based on the fly height measurement signal and the compensation data when the read/write channel is in a fly height measurement mode.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector. The estimate can be a least mean squared estimate of the non-linearity in the equalized signal.

Abstract: A method for manufacturing a perpendicular magnetic write head having a trailing shield and with a tapered step. The method includes forming a write pole with a non-magnetic trailing gap and first and second non-magnetic side gap layers. A mask is formed having an opening over a portion of the write pole that is configured to define a non-magnetic bump. A non-magnetic bump material is deposited into the opening in a manner that defines a non-magnetic bump having a tapered front edge. A magnetic wrap around shield can then be formed over the non-magnetic bump, so that the bump forms a tapered stepped feature on the wrap-around magnetic shield. The bump location can be controlled by an electric lapping guide, which is defined to be aligned to the bump front edge.

Abstract: A head IC adjusts an amplitude level of a read signal of a head and outputs to a read channel having an AGC amplifier, includes an AGC amplifier. The AGC amplifier has a feedback loop control type first amplifier and a feed-forward control type second amplifier. The precision of control with respect to a target value is improved, and an AGC amplifier with fast response can be configured. Further, increases in the AGC pull-in type can be prevented, stability can be assured, and erroneous AGC judgments can be prevented.

Abstract: A head IC, which adjusts an amplitude level of a read signal of a head, for outputting to a read channel having an AGC amplifier, includes: a differential amplifier; an AGC circuit; external gain setting sections; and a switch. Since the AGC amplifier is disposed in the head IC, the amplitude from the head is automatically adjusted in the head IC, and the signal level, which enters the input dynamic range of the AGC amplifier of the read channel, can be adjusted. The AGC amplifier can be operated as a fixed gain amplifier using a gain value which is set from the outside, so the power consumption can be minimized even if automatic adjustment is performed.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier with at least one stage, a feedback network, first and second replica circuits, a buffer, second and third resistances, an operational amplifier (op-amp), a transistor, and a current mirror. The feedback network includes a first resistance that communicates with an input and an output of the amplifier. The first and second replica circuits approximately replicate DC characteristics of the output and the input of the amplifier, respectively. An output of the op-amp communicates with a control terminal of the transistor. The current mirror provides a current at the input of the amplifier that is proportional to a second current flowing through the transistor. The buffer communicates with the first replica circuit. The second resistance communicates with an output of the buffer. The third resistance communicates with the second resistance and with the second replica circuit.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier, a feedback network, an operational amplifier (op-amp), and second, third, and fourth resistances. The amplifier includes an input, an output, and at least one stage. The feedback network includes a first resistance that communicates with the input and the output of the amplifier. The operational amplifier (op-amp) includes an inverting input that communicates with the input of the amplifier, a non-inverting input, and an output. The second resistance communicates with the input of the amplifier and with the output of the op-amp. The third resistance communicates with the output of the op-amp and with the non-inverting input of the op-amp. The fourth resistance communicates with the non-inverting input of the op-amp and with the output of the amplifier.

Abstract: An apparatus, method, and system for providing dc offset reduction in a communications channel include a feedback loop to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

Abstract: Embodiments of the invention prevent erroneous writing/readout onto/from magnetic disks or other recording disks, even when data transfer between a controller such as an HDC, and a channel such as an R/W channel, and the read/write operation performed by the channel do not match each other in timing. In one embodiment, an HDC/MPU outputs to an R/W channel a starting instruction for data transfer to/from a head, and data that indicates data length of data to be transferred. In response to the data transfer starting instruction from the HDC/MPU, the R/W channel starts transferring, to/from the head, recorded data of the data length notified from the HDC/MPU.

Abstract: Methods and structures for detecting touchdown of the read/write head on its recording surface or for detecting other read signal amplitude modulations as proportional to variance of the value of the read channel variable gain amplifier (“VGA”). Variance in the VGA values caused by the standard feedback control electronics associated therewith is proportional to amplitude modulations of the sensed signal picked up by the read channel (or servo read sensor). These amplitude modulations are, in turn, reflective of flying height of the read/write head as well as generally indicative of other parameters of the read channel operation. Touchdown of the read/write head and other parameters of the disk drive operation may therefore be detected as variances in the VGA control values.

Abstract: A technique for de-gaussing the pole tips and yoke of a write transducer in a perpendicular magnetic recording system is provided. An oscillator in the read channel is configured to produce an adjustable signal pattern output to the preamplifier when a write operation ends for a given time and at a predetermined frequency, such that as the preamplifier write current decays, it decays with transitions (polarity reversals). This results in a decaying AC field being applied to the write transducer at the end of a media write operation, effectively de-gaussing it and reducing the effects of remanent magnetization remaining in the poles and yoke of the magnetic recording head after a write current is turned off. This defeats a potential pole tip lockup or yoke lockup circumstance in the magnetic recording media which can result in an inability to write further data or a possible erasure of valid data on the hard disk with which the write head is associated.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit operable to provide a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of nonlinearity derived from the equalized signal and multiple output values of the discrete time sequence detector, the multiple output values being values corresponding to at least two different discrete times.

Abstract: A method for controlling read velocity in a disk device is provided. When reading data on the disc, the method first reads each SYNC of blocks to form an ECC code, read data to decode, and checks and corrects decoded data to generate decoded errors. The type of decoded errors are classified and counted to form reference parameters of a rule base. A fuzzy engine checks if the counting number exceeds the threshold of the parameter, and executes the operation of the rule to control read velocity and enhance the data transfer rate in the disk device.

Abstract: A symmetrical read element circuit for reducing electrical and magnetic noise using signal processing, such as a differential preamplifier. The circuits are symmetrically created on both sides of the read element so that the noise is balanced on both sides of the read element to allow substantial noise reduction by the signal processing.