Abstract: Various embodiments of the present invention provide systems and methods for data equalization. For example, various embodiments of the present invention provide methods for generating equalization data. The method includes inputting N bits of an equalization data pattern into respective stages of a shift register, wherein inputting the N bits occurs synchronous to a system data clock having a system data rate, and shifting the N bits of equalization data to next adjacent next stages of the shift register synchronous to an equalization data clock having an equalization data rate N times the system data rate.

Abstract: Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

Abstract: In one embodiment, a storage-device-implemented method for estimating one or more channel parameters of a storage device including a read channel and a storage medium with a bit sequence stored on the storage medium. The method includes: (a) the storage device reading at least a portion of the bit sequence from the storage medium to generate a bit response; (b) the storage device convolving the bit response to compute an impulse response of the read channel; and (c) the storage device estimating one or more channel parameters based on the computed impulse response.

Abstract: A tail estimate signal which includes noise associated with baseline wander is generated. The tail estimate signal is generated by processing an input signal using a detector to obtain one or more decisions. Using the one or more decisions, the tail estimate signal is generated. The tail estimate signal is removed from the input signal.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: Impedance compensation features are used along the transmission-line path between a transmitter/driver/source and the receiver/transducer to compensate for the impedance discontinuities or mismatches (for example, those caused by physical interconnection features) and/or to improve the frequency response of the signal transfer along the transmission line. The impedance compensation features are non-uniformities with impedance characteristics selected to compensate for the target impedance discontinuities. The compensation features can be non-uniformities (geometric structures designed to have specific impedance characteristics) in the electrically conductive traces that are integrated in the interconnect transmission line between the transmitter/driver/source and the receiver/transducer. The effective impedance level of the transmission line can be lowered or raised using the compensation features.

Abstract: According to one embodiment, a storage apparatus includes: a read section that receives a predetermined electrical parameter to read out data from a recording medium; a characteristic detection section that detects a plurality of characteristic values corresponding to a plurality of different predetermined electrical parameters received by the read section, respectively, the characteristic values being predetermined indicators of the read section, respectively; a characteristic relation acquisition section that acquires a slope of a characteristic value versus a predetermined electrical parameter from the predetermined electrical parameters and the characteristic values; and a determination section that determines presence/absence of failure in the read section based on the slope acquired by the characteristic relation acquisition section.

Abstract: A write channel for a hard disk drive has a write current with a programmably adjustable rise time, and includes first and second analog write data signal paths having respective resistive nodes. First and second programmable capacitors are connected to the resistive nodes, whereby changes in capacitance of the first and second capacitors changes the rise time of the write current. A programmer selectively programs the first and second programmable capacitors. The rise time programmed is selected to provide a decreased bit error rate of an on-track write process and reduced adjacent-track interference.

Abstract: A magnetic device includes a write element having a write element tip and a conductive coil for carrying a current to induce a first field from the write element. A conductor proximate the write element tip carries the current to generate a second field that augments the first field. A driver provides the current to the conductive coil and the conductor, and a circuit phase shifts the current through the conductor relative to the current through the conductive coil.

Abstract: A substrate for mounting a preamp chip thereupon, fabricated using a stiffener layer made of a conductive material; an insulating layer provided over the circuitry area of the substrate; a circuitry made of a conductive material provided over the insulating layer; and a flap which is an extension of the stiffener layer having no insulating layer provided thereupon. The flap is fabricated to fold over the preamp chip to remove heat therefrom.

Abstract: A hard-disk drive (HDD) with a current adjustment component is provided. The current adjustment component changes an amount of current to a magnetic-recording head of the HDD to cause a change in the strength of a magnetic write field produced by the magnetic-recording head in response to a determination that a present position of the magnetic-head head is not in a desired position. To illustrate, in response to a determination that the present position of the magnetic-recording head is further away from an edge of a current track being written than a desired position of the magnetic-recording head, the current adjustment component increases the current to the magnetic-recording head to cause an increase in the strength of the magnetic write field. The change in the strength of the magnetic write field causes data, written by the magnetic-recording head, to be located at a desired location on the magnetic-recording disk.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response include an integrated circuit device including: an input to receive digital data corresponding to an asymmetry corrected analog signal of a read channel; an input to receive sequence data from a discrete time sequence detector, the sequence data generated by the discrete time sequence detector based on the digital data; an output to provide a coefficient adjustment to affect asymmetry correction of the analog signal; and circuitry to generate the coefficient adjustment based on an estimate of non-linearity for the read channel, the estimate derived from the digital data and the sequence data.

Abstract: When the format control circuit detects bit synchronization information in a sector to be reproduced on a magnetic disk, the format control circuit activates a read gate signal for commanding to read out the sector from the magnetic disk. When symbol synchronization information on the magnetic disk is detected, a SYNC detection circuit produces a synchronization information detection signal. The format control circuit calculates an end position of the sector on the magnetic disk on the basis of the synchronization information detection signal to inactivate the read gate signal. The data correction circuit and the decoding circuit reproduce data and ECC in the sector read out from the magnetic disk during the period that the read gate signal is active on the basis of the synchronization information detection signal to produce the data and ECC to a data bus.

Abstract: An object of the present invention is to provide a deterioration detection method of a head and a magnetic disk inspection apparatus in which the number of times of exchanging the head due to deterioration is decreased to improve the throughput of an inspection. In the present invention, a resistance value detecting circuit that is directly coupled to both terminals of an MR head is provided to measure the resistance value of the MR head, and the measured value is compared with the initial value of the exchanged head, so that it is possible to recognize a deterioration state of each head irrespective of a magnetic disk as a measurement target.

Abstract: In a method for causing data to be written to a non-volatile medium, first data to be encoded and written in a sector of the non-volatile medium as a codeword is transmitted to a write or read/write channel device, and a write gate signal corresponding to the sector is asserted. Asserting the write gate signal indicates to the write or read/write channel device when to write the codeword to the sector. While asserting the write gate signal to cause the codeword to be written, second data to be encoded and written to the non-volatile medium is transmitted to the write or read/write channel device.

Abstract: Write enhancement circuitry on the head carrier of a magnetic recording disk drive provides additional write current overshoot beyond that provided by the write driver circuitry. An enhancement capacitor is formed with a dielectric layer between two layers of electrically-conductive magnetically-permeable shield material that serve as the capacitor plates. The write enhancement circuitry may also include an enhancement resistor. The enhancement capacitor and resistor are connected between the two terminals on the head carrier that connect to the write head coil. The capacitor and resistor are fabricated on the head carrier at the same time and in the same process as the read head. The first and second capacitor plates are generally coplanar with and formed of the same electrically-conductive magnetically-permeable material that forms the first and second magnetic shields for the read head.

Abstract: A data storage device preamplifier circuit including (i) a write amplifier having an input and an output, and (ii) a read amplifier has an input and an output. The data storage device preamplifier circuit further includes a loopback circuit configured to selectively connect the output of the write amplifier to the input of the read amplifier.

Abstract: A disk drive is disclosed comprising a plurality of disk surfaces and a plurality of corresponding heads. The disk drive further comprises a preamp including a first integrated circuit coupled to a first plurality of the heads. The first integrated circuit comprises a first read-output for outputting a preamplified read signal, a first write-input for receiving a first write signal, a write-output-passthrough for outputting a passthrough write signal in response to the first write signal, and a read-input-passthrough for receiving a passthrough read signal. The preamp further comprises a second integrated circuit coupled to a second plurality of the heads, wherein the second integrated circuit comprises a second read-output for outputting the passthrough read signal, and a second write-input for receiving the passthrough write signal.

Abstract: Methods and apparatus for generating a hard drive write signal are here in disclosed. A disclosed method comprises generating a hard drive write signal on an output of a switch based on an edge of the first control signal and reducing the hard drive write signal based on an edge of a second control signal via a second switch.

Abstract: A method of protecting information written to a recording medium includes magnetizing the recording medium to form a first magnetic pattern corresponding to information to be stored, and magnetizing the recording medium to form a protective magnetic pattern having a phase difference of 180° from the first magnetic pattern at a position adjacent to where the first magnetic pattern is formed, with adjacent bits of the first magnetic pattern opposite and the protective magnetic pattern opposite to each other.

Abstract: Provided is a computer system including: a computer running as a DB server; a storage system including a plurality of disk drives for storing data; and a management module, in which: at least one of the plurality of disk drives stores data of a DB schema written by the computer; the management module specifies the DB schema to be accessed based on a received query, transmits, to the storage system, an instruction to copy at least a portion of the data of the specified DB schema from the disk drive to a memory, and transmits, to the storage system, an instruction to control an rpm of the disk drive that stores the data of the specified DB schema; and the storage system controls the rpm of the disk drive based on the instruction. Accordingly, power consumption of the storage system can be reduced even if installed disks increase in number.

Abstract: A system including a read channel device and a loopback circuit. The read channel device communicates with a hard disk controller module via a read bus and a write bus. The loopback circuit is configured to selectively loop back the write bus to the read bus. The read channel device is configured to generate a write clock for the hard disk controller module to write data on the write bus. The read channel device is configured to generate a read clock for the hard disk controller module to read the data on the read bus. The write clock is independent of the read clock.

Abstract: Embodiments of the invention provide a magnetic read/write device capable of reading/writing data even when a reversal of the output polarity of the readback signal occurs. In one embodiment, a magnetic read/write device is provided which constantly checks the output polarity based on the polarity of the waveform of a signal obtained as a result of equalizing the waveform of a readback signal of gray code (indicating a cylinder number) in each servo sector by use of a matched filter (MF), or based on the waveform of a readback signal read from areas of a magnetic disk which store a special pattern for detecting the output polarity. When a polarity reversal has occurred, the magnetic read/write device assumes that a read error has occurred and performs processing so as not to perform any track seek or track following operation using decoded positional information.

Abstract: A system and method for trapping electron assisted magnetic recording is disclosed. A magnetic recording system comprises a magnetic storage media, a read/write head, and a power supply for applying a negative DC electrical bias to the magnetic storage media in order to reduce the media switching field during the writing process. Recording is performed by applying an AC magnetic field produced by a write pole and a DC electrical field to assist in the writing. An embodiment of the invention uses a high electrical field to trap free electrons into an unfilled electronic shell of magnetic particles of the magnetic storage media, in particular, (3d) shell of transition elements, (4f) shell of rare earths of lanthanides series, and (5f) shell of actinides series. The trapped electron decreases anisotropy of magnetic particles due to reduced number of Bohr magnetron. As a result, a conventional head is able to write very high anisotropy magnetic storage media.

Abstract: An electronic device includes a power supply line connected between a DC power supply and an integrated circuit, and a first electronic element and a second electronic element serially connected between the power supply line and ground. The second electronic element is open when the first electronic element is short-circuited due to an overvoltage induced in the power supply line. When the overvoltage exceeds a breakdown voltage of the first electronic element, the first electronic element supplies an overcurrent induced in the power supply line to the second electronic element.

Abstract: A method of operating a servo track writer includes writing a clock pattern signal to a magnetic recording medium of a head disk assembly, reading the clock pattern signal written to the magnetic recording medium and dividing a frequency of a read clock pattern signal, and supplying a clock pattern signal having a divided frequency to a spindle motor for rotating the magnetic recording medium.

Abstract: A method of adjusting gain of a variable gain amplifier of a read/write channel circuit includes loading a first VGA gain value that is read channel optimized, in a first register, loading a second VGA gain value that is adapted, in a second register, calculating a third VGA gain value according to a result of operation of the first VGA gain value and the second VGA gain value, and overwriting the third VGA gain value to the first register.

Abstract: A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Abstract: A magnetic head, includes a magnetic oscillation element, the oscillation frequency of which is modulated by a medium magnetic field, and a reproducing device configured to detect a phase difference between the adjacent oscillation signals derived from the magnetic oscillation element and output a phase difference signal as a reproduced signal.

Abstract: A communications circuit includes a first filter having a corner frequency that is adjustable. A data type identifier that tracks first and second types of data flowing through the communications circuit. A control module that adjusts the corner frequency of the first filter to provide alternating current (AC) coupling during the first type of data and adjusts the corner frequency of the first filter to provide direct current (DC) coupling during the second type of data.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first gain control circuit coupled to the variable gain amplifier for controlling the gain of the analog signal; an analog to digital converter for converting the analog signal to a digital signal; a first gain error generation circuit for generating a first gain error signal based on an output of the analog to digital converter, the first gain error signal or derivative thereof being received by the first gain control circuit; and a second gain error generation circuit for generating a second gain error signal based on the digital signal, the second gain error signal or derivative thereof being received by the first gain control circuit, wherein the first gain control circuit uses at least one of the gain error signals to control the gain of the analog signals.

Abstract: Embodiments of the present invention help to efficiently determine the appropriate setting of the write current of a magnetic head relative to temperature. According to one embodiment, a test computer determines the set value of a write current as a function of temperature for each head device portion from the relationship between a write current and an error rate. A test execution controller sets a selected head device portion and a write current to an AE, and writes data on a magnetic disk using the components in a HDD. The test execution controller reads the written data, and the error rate of the data from an error correcting section. The test execution controller repeats the same process with the write current varied. Upon completion of the measurement at the preset write currents, the test execution controller transfers the measurement data to the test computer.

Abstract: A weighted combining scheme exploits information from two servo channels operating in parallel. A timing-based servo module servo module comprises two servo channels coupled respectively to receive two digital servo signals read from a data tape. Both channels have outputs for an unweighted metric and for a measure of the channel reliability. A weight computation module provides first and second weight signals using the measures of channel reliability from the servo channels. A first multiplying node receives a first unweighted metric and a first weight signal and is operable to output a first weighted metric. A second multiplying node receives a second unweighted metric and a second weight signal and outputs a second weighted metric. A summing node receives the first and second weighted metrics and outputs a combined weighted metric to an LPOS word decoder.

Abstract: Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output.

Abstract: According to one embodiment, A system includes a first LSI, a second LSI, a controller and a current monitoring and determination module. The first LSI operates on a first power supply voltage generated by a first voltage regulator included in the second LSI. The module operates on a device power supply voltage supplied from the device power supply. The module monitors current flowing between the first LSI and the first voltage regulator, determines an abnormality in the first LSI on the basis of the current monitoring result and transmits an abnormality signal to the controller on the basis of the abnormality determination result. The controller operates on a second power supply voltage generated by a second voltage regulator included in the second LSI and reports an abnormality in the first LSI to a host system in accordance with the reception of the abnormality signal.

Abstract: Various embodiments of the present invention provide systems and methods for using data equalization. For example, various embodiments of the present invention provide storage devices that include a semiconductor device having an equalization unit and a digital-to-analog converter, a read/write head assembly located in close proximity to the semiconductor device, and a control unit located less proximate to the read/write head assembly than the semiconductor device.

Abstract: A disk drive including a sensor element that senses contact between a head slider and a disk, a head integrated circuit (IC) comprising an amplification circuit section that amplifies a signal of the head slider, a controller IC comprising a controller that accesses a register of the head IC for controlling the head IC, and an identification section, within the head IC, that determines a contact frequency of the contact by the sensor element by using a timing control signal of the controller IC.

Abstract: Resistivity sense bias circuits are described herein. An example resistivity sense bias circuit for use with a magnetoresistive read head includes a current biasing portion configured to provide a bias current across the magnetoresistive read head thereby establishing a bias voltage across the magnetoresistive read head, a resistivity sensing portion coupled to the current biasing portion and configured to sense a change in the bias current based on a resistivity change of the magnetoresistive read head, and a voltage source to provide the bias voltage and to adjust the bias voltage in response to the resistivity change of the magnetoresistive read head.

Abstract: Various embodiments of the present invention provide systems and methods for performing data equalization. For example, various embodiments of the present invention provide data equalization circuits that include an equalization circuit and a transition adjustment circuit. The equalization circuit receives a series of at least two original data bits and replaces at least one of the two original data bits with an equalization pattern including two or more equalization bits. The original data bits correspond to an original data clock, and the two or more equalization bits correspond to an equalization data clock. The transition adjustment circuit is operable to modify an occurrence of a transition from one logic state to another logic state within the equalization pattern on a sub-equalization data clock basis.

Abstract: Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds.

Abstract: Aspects of the present embodiment are related to a power supply voltage supply circuit and the disk apparatus that are capable of reducing power consumption in data writing and reading. The power supply voltage supply circuit includes a data processing unit writing data onto a disk medium and/or reading data from the disk medium=having a plurality of zones assigned a cylinder number, a data input-output unit transmitting data to the data processing unit at a transfer rate in accordance with the zones, a power supply voltage supply unit supplying a voltage to the data input-output unit and a control unit controlling the power supply voltage supply unit in order to supply the voltage in accordance with the transfer rate.

Abstract: A signal conversion circuit includes: an input circuit that rejects common mode inputs and is configured to receive a differential input signal and shift a first bias of the differential input signal to produce a single ended intermediate signal with a second bias; and an amplifier circuit configured to amplify the single ended intermediate signal to produce an amplified signal. The input circuit can include: first and second transistors with drains configured to couple with a supply voltage, and gates of the first transistor and the second transistor are configured to receive the differential input signal; a first resistor coupled to a source of the first transistor and a drain of a third transistor; and a second resistor coupled to a source of the second transistor and a drain of a fourth transistor; where the third transistor and the fourth transistor are connected in a current mirror configuration.

Abstract: A method according to one embodiment includes generating a first gain error, comprising: receiving an output of an equalizer; and comparing a magnitude of the output to a saturation threshold level; if the output is higher than the saturation threshold level, generating a first gain error. The method further including generating at least one of a second and a third gain error, wherein generating the second gain error comprises: using either a slicer or a trellis for generating the second gain error, wherein the slicer generates a gain error based on an output of an interpolator, wherein the trellis generates a gain error based on an output of a maximum likelihood detector; wherein generating the third gain error comprises: receiving an output of an equalizer; generating a threshold qualified peak from the equalizer output and a tracking threshold level; comparing the threshold qualified peak to a second threshold; and generating a third gain error based on the comparison.

Abstract: A method for determining runout disc is disclosed. The method comprises: focusing on a focal point on a disc; driving the disc to spin the disc; generating a crossover signal according to a track of the disc crossing the focal point; and determining that the disc is a runout disc when the frequency of the crossover signal exceeds a pre-determine value.

Abstract: A reception device configured to receive a signal of a transmitted bit string transmitted from a transmission device which transmits a bit string includes: a receiving unit arranged to receive a signal from the transmission device and output a received bit string corresponding to the transmitted bit string; a storing unit arranged to store an error rate table wherein said received bit string is correlated with an error rate of post-data which is data of one bit or greater received following the received bit string being in error; and an error correcting unit arranged to perform error correcting of the post-data of the received bit string.

Abstract: A method of operating a pre-amplifier of a hard disk drive is provided. The method includes generating a comparison signal corresponding to a result of comparing a reference signal with a difference between differential signals corresponding to write data, and controlling transmission of the differential signals to a write head in response to the comparison signal.

Abstract: Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Abstract: A read channel includes a variable gain amplifier, a low-pass filter, an AGC, an analog-to-digital converter, a frequency synthesizer, a filter, a soft-output detector, an LDPC decoding unit, a synchronizing signal detector, a run-length limited decoding unit, a descrambler, and a first baseline wander corrector. The first baseline wander corrector corrects a baseline variation by a feedforward control.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector. The estimate can be a least mean squared estimate of the non-linearity in the equalized signal.

Abstract: A write driver circuit includes a first write driver that communicates with a first node of a write head. A first feedback path communicates with a control input and an output of the first write driver. The first feedback path includes a first resistance connected between the output of the first write driver and the control input of the first write driver. A second write driver communicates with a second node of the write head. A second feedback path communicates with a control input and an output of the second write driver. The second feedback path includes a second resistance connected between the output of the second write driver and the control input of the second write driver.