Abstract: A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes facing each other with one dielectric layer therebetween and alternately exposed to the first or second side surface; upper and lower cover layers disposed on and below the active layer; and a first external electrode disposed on the first side surface and a second external electrode disposed on the second side surface. Thickness T and width W of the ceramic body satisfy 0.75W?T?1.25W, gap G between the first and second external electrodes satisfies 30 ?m?G?0.9W, and an average number of dielectric grains in a single dielectric layer in a thickness direction thereof is 2 or greater.

Abstract: A capacitor includes a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first and second planes; a first external electrode layer disposed on the first plane; a second external electrode layer disposed on the second plane; a first internal electrode having first and second electrode portions, the first and second electrode portions being formed of a first conductive material, and a second conductive material, respectively, the second electrode material connecting the first electrode portion with the first external electrode layer, the second conductive material having a smaller Young's modulus than the first conductive material, the first internal electrode being formed in a part of the plurality of through-holes; and a second internal electrode formed in another part of the plurality of through-holes, the second internal electrode being connected to the second external electrode layer.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having first and second leads and a fourth internal electrode having third and fourth leads, the third and fourth internal electrodes being disposed on one dielectric layer in the ceramic body, and fifth and sixth internal electrodes disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: A metal-insulator-metal capacitor includes a bottom metal line and a top metal line disposed above the bottom metal line. An insulating material layer is between the bottom metal line and the top metal line, which the insulating material layer is an inter-metal-dielectric layer.

Abstract: A multilayer ceramic capacitor may include a ceramic body having a plurality of dielectric layers stacked therein; an active part including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body; upper and lower cover layers; and first and second external electrodes covering both end surfaces of the ceramic body. When a thickness of the upper or lower cover layer is defined as C, a margin between the active part and a side surface of the ceramic body in a width direction is defined as M, a cross-sectional area of the ceramic body in a width-thickness direction is defined as Ac, and a cross-sectional area of the active part in the width-thickness direction, in which the internal electrodes are overlapped in a thickness direction, is defined as Aa, 1.826?C/M?4.686, and 0.2142?Aa/Ac?0.4911.

Abstract: A multilayer ceramic capacitor may include: an active part including a plurality of first and second internal electrodes; upper and lower cover layers; and first and second external electrodes including head parts and band parts. When a thickness of the upper or lower cover layer is defined as C, a width of a margin portion of the ceramic body in a width direction is defined as M, a cross-sectional area of the ceramic body in a width-thickness direction is defined as Ac, a cross-sectional area of the active part in a width-thickness direction in a portion thereof in which the first and second internal electrodes are overlapped with each other in a thickness direction is defined as Aa, and a width of the band part of the first or second external electrode is defined as B, 1.826?C/M?4.686, 0.2142?Aa/Ac?0.4911, and 0.5050?C/B?0.9094 may be satisfied.

Abstract: A ceramic electronic component includes a ceramic body; a plurality of internal electrodes provided in the ceramic body and including ends exposed on a surface of the ceramic body; a coating layer covering a surface portion of the ceramic body on which the internal electrodes are exposed, the coating layer being made of a glass or resin medium in which metal powder particles are dispersed; and an electrode terminal provided directly on the coating layer and including a plating film. The metal powder particles define conduction paths electrically connecting the internal electrodes with the electrode terminal and have an elongated shape in cross section along a thickness direction of the coating layer. The metal powder particles defining the conduction paths have a maximum diameter not smaller than the thickness of the coating layer.

Abstract: In a multilayer capacitor 1, burned layers 17A, 17B are formed so as to cover all of lead conductors 12A, 12B drawn from inner electrodes 6A, 6B to end faces of a multilayer body 2. This can keep a plating solution from infiltrating onto the inner electrodes 6A, 6B when forming plating layers 18A, 18B and prevent insulation failures from occurring. Since the burned layers 17A, 17B cover a part of dummy electrodes 13C, 13F, 13G, 13H, the area of the burned layers 17A, 17B can be suppressed. This can inhibit excessive stresses from occurring in the burned layers 17A, 17B and thus can prevent cracks from being generated by stresses in the burned layers 17A, 17B.

Abstract: Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers. The on-chip capacitor may comprise interdigitated electrically coupled metal fingers. The electrically coupled metal fingers may be arranged symmetrically in the semiconductor die to compensate for non-uniformities in the one or more metal layers. The metal fingers may be arranged with radial symmetry. Metal fingers in a first metal layer may be electrically coupled to metal fingers in a second metal layer. An orientation of metal fingers may be alternated when coupling metal fingers in a plurality of metal layers. The metal fingers may be coupled at the center or the outer edge of the on-chip capacitor. The on-chip capacitor may be configured in a plurality of symmetric sections wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern.

Abstract: There is provided a multilayer ceramic electronic component, including a ceramic body having first and second side surfaces facing each other, and first and second end surfaces facing each other; first and second internal electrodes having first and second lead portions; and first and second external electrodes extended from the first and second end surfaces of the ceramic body to the first and second side surfaces, respectively, wherein when a distance from an end portion of the first or second external electrode formed on the first or second side surface of the ceramic body to a point of the first or second external electrode connected to the first or second lead portion is defined as G, and a width of the first or second external electrode on the first or second side surface of the ceramic body is defined as BW, 30 ?m?G<BW is satisfied.

Abstract: There is provided a multilayer ceramic electronic component, including: a ceramic body formed by laminating dielectric layers having an average thickness of 0.7 ?m or less; external electrodes formed on external surfaces of the ceramic body; and internal electrodes respectively disposed on the dielectric layer so as to have a gap formed therebetween, wherein, when a narrowest gap between the internal electrode edges adjacent to one another is denoted by Gmin, 10 ?m?Gmin?60 ?m is satisfied.

Abstract: A multilayer ceramic electronic part to be embedded in a board includes a ceramic body including dielectric layers and having main surfaces, side surfaces, and end surfaces; first and second internal electrodes including first and second leads exposed to the main surfaces; and first and second external electrodes formed on the end surfaces and extending to the main surfaces, wherein when a length from one of ends of the first or second external electrode formed on the main surfaces to a point at which the first or second external electrode contacts the first and second leads is G, a length from one of the ends of the first or second external electrode to the end surfaces is BW, and a length from the end surfaces to a point at which the first or second external electrode contacts the first and second leads is M, 30 ?m?G<BM?M is satisfied.

Abstract: A metal capacitor includes a plurality of interconnect segments. A first plurality of L-shaped fingers is driven to a first voltage level by a first interconnect segment. A second plurality of L-shaped fingers is driven to a second voltage level by a second interconnect segment. Each of the L-shaped fingers from a set of the first plurality of L-shaped fingers is adjacent to at least one of the L-shaped fingers from a set of the second plurality of L-shaped fingers.

Abstract: A rectangular or substantially rectangular parallelepiped chip including first and second end surfaces and first and second side surfaces is produced by cutting a mother block along a first direction in a portion where, of conductive layers that are adjacent to each other in a stacking direction, a first one is present and a second one is not present and cutting of the mother block along a second direction in a portion where, of the conductive layers that are adjacent to each other in the stacking direction, the second one is present and the first one is not present. A first internal electrode formed from the first conductive layer is exposed at the first end and side surfaces and not exposed at either of the second end and side surfaces. A second internal electrode formed from the second conductive layer is exposed at the second end and side surfaces and not exposed at either of the first end and side surfaces.

Abstract: A method of manufacturing a multilayer ceramic electronic component includes a step of preparing a first ceramic green sheet on which at least one of a first internal electrode pattern and a second internal electrode pattern are printed, a second ceramic green sheet on which at least one of a first dummy conductor pattern and a second dummy conductor pattern are printed, and a third ceramic green sheet on which at least one of a third internal electrode pattern and a fourth internal electrode pattern are printed, wherein a width of the third dummy conductor pattern is made less than a width of the first dummy conductor pattern, and a width of the fourth dummy conductor pattern is made less than a width of the second dummy conductor pattern.

Abstract: Disclosed herein is a multilayered ceramic component having a structure in which internal electrode layers and dielectric layers are alternately multilayered, wherein the internal electrode layer includes 0.01 to 12 wt % of common material based on weight of metal powders, and an average particle size of the common material is 30 to 50% of an average particle size of a dielectric base material included in the dielectric layer. According to the first exemplary embodiment of the present invention, the particle size and the added amount of the common material squeezed out from the internal electrode layers at the time of firing thereof at a high temperature are controlled, thereby making it possible to improve the capacity and the reliability of the internal electrode.

Abstract: A chip component is provided with a block including a dielectric, input and output terminals, which are the first and second terminals that are provided on the surface of the block, an adjustment terminal that is a third terminal that includes an internal electrode extended into the block and that is provided on the surface of the block, and at least two inter-terminal circuits that are provided in the block and that are connected between at least two sets of two terminals of the first, second, and third terminals.

Abstract: Disclosed herein is an apparatus for storing an electric energy, the apparatus including: an electrode stack in which a cathode and an anode in which a cathode lead and an anode lead are respectively formed are alternately stacked; and collector plates disposed at both sides of the electrode stack, connected to the cathode lead and the anode lead, and provided with external terminals and one or more electrolyte flow holes.

Abstract: A biaxially stretched polypropylene film includes protrusions on both surfaces, in which the biaxially stretched polypropylene film has a thickness t1 of 1 ?m to 3 ?m, has a tensile strength in the machine direction of 120 MPa to 250 MPa, has a tensile strength in the transverse direction of 250 MPa to 400 MPa, has a minimum protrusion height Pmin of 100 nm or greater and a maximum protrusion height Pmax of 1,600 nm or smaller for either surface, and satisfies all of Formulae (1) to (3) when one of the surfaces is surface A and the other is surface B: 0.5?Pa250-450/Pa?1.0 (1), 0.5?Pb450-1600/Pb?1.0 (2), and 600?Pa+Pb?1,200 (3).

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body, first to third capacitor parts, first and second internal connection conductors, and first to fourth external electrodes, wherein the first capacitor part is connected in series with the second internal connection conductor, and the second capacitor part is connected in series with the first internal connection conductor.

Abstract: A variable capacitor device is disclosed in which the capacitive tuning ratio and quality factor are increased to very high levels, and in which the capacitance value of the device is tuned and held to a desired value with a high level of accuracy and precision using a laser micromachining tuning process on suitably designed and fabricated capacitor devices. The tuning of the variable capacitor devices can be performed open-loop or closed-loop, depending on the precision of the eventual capacitor value needed or desired. Furthermore, the tuning to a pre-determined value can be performed before the variable capacitor device is connected to a circuit, or alternatively, the tuning to a desired value can be performed after the variable capacitor device has been connected into a circuit.

Abstract: There is provided a multilayer ceramic capacitor to be embedded in a board, including: a ceramic body; first and second internal electrodes alternately exposed through end surfaces of the ceramic body; first and second external electrodes formed on end surfaces of the ceramic body; and first and second plating layers enclosing the first and second external electrodes, wherein when distance from one end of bands of the first or second external electrode to the other end thereof is ‘A’ and distance between points at which a virtual line drawn from a point vertically spaced apart from a surface of the first or second plating layer at a point ½×A from one end of the bands inwardly of the ceramic body by 3 ?m in length direction of the ceramic body intersects points on the surface of the first or second plating layer is ‘B,’ B/A?0.6.

Abstract: A multilayer ceramic capacitor includes a body including a multilayer unit with ceramic dielectric layers and conductive layers alternately stacked on each other. The body includes a thickness-direction inner layer section including the multilayer unit and thickness-direction first and second outer layer sections that sandwich the thickness-direction inner layer section therebetween. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. A width of a second outermost conductive layer closest to a second principal surface of the body is smaller than a width of a central conductive layer closest to a center of the multilayer unit in the thickness direction.

Abstract: A supercapacitor comprising a two electrodes, a porous separator disposed between the two electrodes, and an ionic liquid electrolyte in physical contact with the two electrodes, wherein at least one of the two electrodes comprises a meso-porous structure being formed of a plurality of nano graphene platelets and multiple pores having a pore size in the range of 2 nm and 25 nm, wherein the graphene platelets are not spacer-modified or surface-modified platelets. Preferably, the graphene platelets are curved, not flat-shaped. The pores are accessible to ionic liquid molecules, enabling the formation of large amounts of electric double layer charges in a supercapacitor, which exhibits an exceptionally high specific capacitance and high energy density.

Abstract: There is provided a multilayered ceramic capacitor, including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer, the lower cover layer being thicker than the upper cover layer; a dummy electrode formed inside at least one of the upper and lower cover layers; and first and second external electrodes, wherein, when A is defined as ½ of an overall thickness of the ceramic body, B is defined as a thickness of the lower cover layer, C is defined as ½ of an overall thickness of the active layer, and D is defined as a thickness of the upper cover layer, a ratio of deviation between a center of the active layer and a center of the ceramic body, (B+C)/A, satisfies 1.063?(B+C)/A?1.745.

Abstract: There is provided a multilayer ceramic electronic component including a lamination main body including a plurality of inner electrodes. When T1 represents a distance between vertically adjacent inner electrodes in a central portion of the lamination main body, and T2 represents a distance between vertically adjacent inner electrodes at an edges of the inner electrodes in a widthwise direction, a ratio (T2/T1) of T2 to T1 is 0.80 to 0.95.

Abstract: A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m?3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.

Abstract: Disclosed herein is a multilayer capacitor comprising: a laminate in which a plurality of first sheets and second sheets are alternately laminated, wherein the first sheets and the second sheets are disposed in a direction perpendicular to a mounting surface; a first inner electrode formed on the first sheets, wherein the first electrode is exposed through upper, lower, and first lateral surfaces of the laminate; a second inner electrode that is formed on the second sheets and has a horizontally symmetrical shape with respect to the first inner electrode; a sealing portion encapsulating the first and second inner electrodes exposed through two lateral surfaces of the laminate; and an external electrode that is electrically connected to the first and second inner electrodes exposed through the upper and lower surfaces of the laminate.

Abstract: A electronic device is provided. In one configuration, the electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are reflection symmetrically disposed; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode. The shape of the first electrode is the same shape as the second electrode.

Abstract: A capacitor structure includes at least two capacitors. A first electrode includes a bottom conductive plane and first vertical conductive structures. The bottom conductive plane is disposed over a substrate. The bottom conductive plane has a first area and a first shape. At least two second electrodes include top conductive planes and second vertical conductive structures. A combined area of the top conductive planes and a gap area between adjacent top conductive planes has a second area and a second shape. The first area and the second area are about the same and the first shape and the second shape are about the same. An insulating structure is disposed between the first electrode and the second electrodes. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other. The capacitors share the bottom conductive plane and have separate top conductive planes.

Abstract: A multilayer ceramic electronic component includes a ceramic body including dielectric layers stacked in a thickness direction and satisfying T/W>1.0 when a width thereof is W and a thickness thereof is T; first and second internal electrodes; and first and second external electrodes, wherein when the ceramic body is divided into five regions in a width direction and a central region among the five regions is CW1 and regions adjacent to the central region CW1 are CW2 and CW3, a difference between electrode connectivity of the central region CW1 and electrode connectivity of the region CW2 or CW3 satisfies 0.02?(CW2 or CW3)?CW1?0.10.

Abstract: A capacitor array includes a plurality of comb capacitors sharing a common comb electrode. At least one of the comb capacitors has a comb electrode as a single base part. Each of the other ones of the comb capacitors has an electrode formed by coupling a plurality of base parts. In the other ones of the comb capacitors, a space between a wire coupling the base parts and an end of each of comb teeth of the common electrode, which is interposed between the base parts, is larger than a space between a base of each of the base parts of the plurality of comb capacitors and an end of each of the comb teeth of the common electrode, which is interposed between comb teeth of the base part.

Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.

Abstract: In one embodiment, a system, comprising: a first non-magnetic conductive electrode; a second non-magnetic conductive electrode; a dielectric layer disposed between the first and second electrodes, the dielectric layer extending between the first and second electrodes; and first and second layers comprising plural pairs of magnetically coupled pairings of discrete magnets, the first and second layers separated by a non-magnetic material, wherein the magnets of at least the first layer are conductively connected to the first non-magnetic conductive electrode.

Abstract: A method for manufacturing a monolithic ceramic electronic component includes the steps of preparing a first ceramic outer layer, stacking a plurality of inner electrodes and a plurality of ceramic green sheets on the first ceramic outer layer, forming an inner portion, applying first pressing in the stacking direction, forming an outer portion on the inner portion to form a second ceramic outer layer, applying second pressing in the stacking direction to form a multilayer body, cutting the mother multilayer body to obtain individual multilayer bodies, sintering the individual multilayer bodies to obtain ceramic bodies, and forming first and second outer electrodes on the outer surface of each of ceramic bodies.

Abstract: A multilayer ceramic capacitor includes a ceramic element body including internal electrodes therein. External electrodes are provided on end surfaces of the ceramic element body and electrically connected to exposed portions of respective ones of the internal electrodes. Each of the external electrodes includes a sintered metal layer, a conductive resin layer, and a plating layer. In a cross section of the multilayer ceramic capacitor, at an interface between the sintered metal layer and the conductive resin layer, recesses having a shape in which a dimension of an inner portion is larger than a dimension of an inlet are present, and a number of recesses in which a material of the conductive resin layer is present is 2 or more within a length range of about 70 ?m along the interface.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; first and second internal electrodes including respective lead-out portions having an overlapping area, the overlapping area being exposed to one surface of the ceramic body; first and second external electrodes extended from the one surface of the ceramic body to side surfaces thereof in a y-direction, in which the first and second internal electrodes are laminated, and connected to the respective lead-out portions; and an insulation layer formed on the one surface of the ceramic body.

Abstract: In one embodiment, an apparatus includes a first reference voltage coupled to a first metal layer and a second reference voltage coupled to a second metal layer. A first finger type in the plurality of fingers is coupled to the first metal layer at a first area and coupled to the first metal layer and the second metal layer at a second area. A second finger type in the plurality of fingers is coupled to the second metal layer at the first area and coupled to the first metal layer and the second metal layer at the second area. Also, the first finger type and the second finger type alternately positioned next to each other.

Abstract: A monolithic electronic component includes a laminate including a plurality of stacked insulating layers and a plurality of internal electrodes which extend between the insulating layers and which have end portions exposed at predetermined surfaces of the laminate, first plating layers disposed on the predetermined surfaces of the laminate, and second plating layers disposed on the first plating layer. The first plating layers are made of a metal different from that used to make the internal electrodes. The first plating layers are formed by electroless plating. The second plating layers are formed by electroplating.

Abstract: A design for an improved metal-on-metal capacitor design is described. The design includes a substantially diagonal feedline (411, 412, 413) in each metal layer. Each metal layer (21, 22, 23) comprises two sets of metal fingers which are interleaved. Each set of fingers comprises two subsets of fingers and the subsets of fingers are arranged at right angles to each other. Fingers in a first of the two sets are all connected to the diagonal feedline, while fingers in the other set are connected together via fingers at the periphery of the device. The design is repeated in adjacent layers, where the design may be identical or rotated (e.g by 180°) between adjacent metal layers.

Abstract: A electronic device is provided. The electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are symmetrically disposed with respect to a first point; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode.

Abstract: Multilayer ceramic electronic component includes: a ceramic body including dielectric layers and having first and second main surfaces, first and second side surfaces, and first and second end surfaces; a first internal electrode including a capacitance forming portion having an overlap region for forming capacitance and a first lead-out portion extended from the capacitance forming portion to be exposed to the first side surface; a second internal electrode alternately stacked with the first internal electrode, having the dielectric layer interposed therebetween, insulated from the first internal electrode, and having a second lead-out portion extended from the capacitance forming portion to be exposed to the first side surface; first and second external electrodes connected to the first and second lead-out portions, respectively; an insulation layer.

Abstract: There are provided a multi-layered ceramic electronic component and a method of manufacturing the same. The multi-layered ceramic electronic component includes: a ceramic body; internal electrodes formed within the ceramic body and including non-electrode regions formed therein; and external electrodes formed on ends of the ceramic body and electrically connected to the internal electrodes, wherein in a cross section of the internal electrode, 70% or more of the non-electrode regions are distributed in a region formed between points inwardly spaced apart from each of the upper and lower boundary surfaces of the internal electrodes by 5%.

Abstract: A substrate comprising a capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via a via post standing on said capacitor.

Abstract: The multi-layer component has a main body (1) made of ceramic layers (2) and two-dimensional inner electrodes (3, 3a, 3b, 3c) in an alternating sequence. Outer electrodes (4, 4a) which are separate from each other are located on the outer surfaces (5, 5a) of the main body. The inner electrodes each have a connecting region and an overlapping region adjacent thereto. A rectilinear edge (16) of the connecting region is connected in an electrically conductive manner to one of the outer electrodes. The overlapping region is arranged at distances (6, 6a) from the outer electrodes. The edge of the connecting region that is connected to the outer electrode is at least as long as the extent of the overlapping region along straight lines running parallel to said edge, and the overlapping region is multiply interrupted at least along a number of said straight lines.

Abstract: The hollow tubular capacitor includes one side electrode connecting portion having an inner peripheral tubular portion and one side surface portion, the other side electrode connecting portion having an outer peripheral tubular portion and the other side surface portion and an electrostatic capacitance portion having one side electrode plate, the other side electrode plate and a dielectric body, wherein the electrostatic capacitance portion is accommodated in an annular space formed at the inner peripheral tubular portion, the one side surface portion, the outer peripheral tubular portion and the other side surface portion in a high density to reduce inside inductance component. The inverter device is formed such that the hollow tubular capacitor and an annular inverter circuit portion having three-phase upper and lower arms are integrally arranged coaxially on the central axis line.

Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

Abstract: There is provided a multilayer ceramic electronic component. The multilayer ceramic electronic component includes a ceramic main body including a dielectric layer, and first and second internal electrodes disposed to face each other within the ceramic main body and having the dielectric layer interposed therebetween. When an average roughness of center lines of the first and second internal electrodes is Ra, a maximum distance from a virtual line corresponding to Ra to a bottom of a pit (d) formed below the virtual line is 0.1 ?m to 13 ?m. The surface roughness of the internal electrode printed surface is improved to decrease the occurrence of electrical shorts.

Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.

Abstract: Provided is a laminated ceramic electronic component which has excellent mechanical characteristics, internal electrode corrosion resistance, high degree of freedom in ceramic material design, low cost, low defective rate, and various properties. The laminated ceramic electronic component includes: a laminate which has a plurality of laminated ceramic layers and Al/Si alloy-containing internal electrodes at a plurality of specific interface between ceramic layers; and an external electrode formed on the outer surface of the laminate, wherein the Al/Si ratio of the Al/Si alloy is 85/15 or more.