Abstract: An electrostatic discharge (ESD) device includes a pair of depletion mode MOSFETs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs, and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike (in an automobile, sometimes referred to as a "load dump"), while the second MOSFET saturates, limiting the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide.

Abstract: Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride.

Abstract: The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor includes a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.

Abstract: A pad printer is used to apply multiple patterned layers of alternating materials to form capacitors and resistors within or on ceramic packages. Fast drying resistive, conductive and dielectric inks are used to form very thin (from about 5 to 20 micron) patterned layers for integrated resistors and capacitors. The integrated capacitors may be interconnected in various configuration by patterning clearance holes into the conductive layers which allows the pass-through of electrical connections.

Abstract: In a multi-functional multilayer device including a body (10) having a varistor section (2) and a capacitor section (3) stacked and integrated therewith, the adhesion between a varistor layer and a dielectric layer is improved when the varistor layer (22) contains zinc oxide as a main component and at least one lanthanide oxide as an auxiliary component, and the dielectric layer (32) contains titanium oxide or lanthanum/titanium oxide as a main component. The device experiences little warpage upon firing when glass is added to the dielectric layer. A high resistivity intermediate layer (5) disposed between the varistor and capacitor sections (2 and 3) prevents the deterioration or loss of varistor and capacitor properties by interdiffusion of elements between the varistor and capacitor sections.

Abstract: An in situ method for forming a bypass capacitor element internally within a PCB including the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides thereof and laminating the conductive foils to the dielectric sheet simultaneously as the PCB is formed by a final lamination step, the conductive foils preferably being laminated to another layer of the PCB prior to their arrangement adjacent the dielectric sheet or sheets, the dielectric foils even more preferably being initially laminated to additional dielectric sheets in order to form multiple bypass capacitive elements as a compound subassembly within the PCB. A number of different dielectric materials and resins are disclosed for forming the capacitor element.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.

Abstract: A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive electrode. A tantalum pentoxide film is then formed on the oxidized and nitrated surface of the conductive electrode. The tantalum pentoxide film may then be thermally treated in the presence of oxygen gas. High performance microelectronic capacitors are thereby provided.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: A monolithic ceramic capacitor has dielectric ceramic layers of a material comprising barium titanate having alkali metal oxides impurities in an amount of not more than about 0.02% by weight, manganese oxide, cobalt oxide, and nickel oxide; from about 0.5 to 5.0 mols MgO to 100 mols of a main constituent shown by the following composition formula;(1-.alpha.-.beta.-.gamma.){BaO}.sub.m.TiO.sub.2 +.alpha.M.sub.2 O.sub.3 +.beta.Re.sub.2 O.sub.3 +.gamma.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)Owherein M.sub.2 O.sub.3 is at least one of Sc.sub.2 O.sub.3 and Y.sub.2 O.sub.3 ; Re.sub.2 O.sub.3 is at least one of Sm.sub.2 O.sub.3 and Eu.sub.2 O.sub.3 and .alpha., .beta., .gamma., m, x, and y are0.0025.ltoreq..alpha.+.beta..ltoreq.0.0250.ltoreq..beta..ltoreq.0.00750.0025.ltoreq..gamma..ltoreq.0.05.gamma./(.alpha.+.beta.).ltoreq.40.ltoreq.x<1.00.ltoreq.y<1.00.ltoreq.x+y<1.01.000<m.ltoreq.1.035;an Li.sub.2 O--B.sub.2 O.sub.3 --(Si, Ti)O.sub.2 oxide glass in an amount of from about 0.2 to 3.

Abstract: A condenser and the production method thereof are disclosed, wherein the condenser is composed of a positive foil sheet, a negative foil sheet and an isolating sheet which are placed one on another in combination, a plurality of lead terminals and another plurality of lead terminals, the one plurality of lead terminals being positioned at a circumferentially same phase and arranged in alignment in one radial direction of the cylindrical condenser and the another plurality of lead terminals being positioned at a circumferentially same phase and arranged in alignment in another radial direction of the cylindrical condenser; and wherein the production method is to attach the one and another plurality of lead terminals to the positive foil sheet and the negative foil sheet respectively with a predetermined space provided therebetween, and then roll up the combined sheets by cooperation of a rotational sheet rolling up shaft and a rotational drive roller which is pressed against the circumferentially outer surface

Abstract: A cylindrical cell is fabricated with a cathode, an anode, a separated placed between the cathode and anode, and a separator fragment extending from a winding axis to the initial part of a cathode.

Abstract: One aspect of the present invention is directed to a capacitor. The capacitor includes a first layer and a second layer. The first layer includes a first electrically conductive substrate having a first surface and a second surface. A first dielectric film is deposited on the first surface of the first substrate and a second dielectric film is deposited on the second surface of the first substrate. The second layer contacts the first layer. The second layer includes a second electrically conductive substrate having a first surface and a second surface. A third dielectric film is deposited on the first surface of the second substrate, and a fourth dielectric film is deposited on the second surface of the second substrate.

Abstract: A nonuniform dielectric is located proximate to a conductive surface, the dielectric being substantially nonuniform with respect to the surface area of that conductive surface. If there are plural closely spaced conductors in a structure, then the nonuniform dielectric is located outside the space between these closely spaced conductors. Making the proximate dielectric nonuniform instead of uniform can provide advantages in better electrical performance for the proximate conductor.

Abstract: A monolithic ceramic capacitor having a plurality of dielectric ceramic layers, internal electrodes, and external electrodes electrically connected to the internal electrode, wherein the dielectric ceramic layers comprise (a) barium titanate having an alkali metal oxide impurity content of not more than about 0.02% by weight, (b) scandium oxide and/or yttrium oxide, (c) gadolinium oxide, terbium oxide and/or dysprosium oxide, (d) manganese oxide, (e) cobalt oxide, and (f) nickel oxide, and is a material containing (1) 100 mols represented by the compositional formula:(1-.alpha.-.beta.){BaO}.sub.m .cndot.TiO.sub.2 +.alpha.{(1-x)M.sub.2 O.sub.3 +xRe.sub.2 O.sub.3 }+.beta.(Mn.sub.1-y-z Ni.sub.y Co.sub.z)Owherein M.sub.2 O.sub.3 represents the above-mentioned (b); Re.sub.2 O.sub.3 represents the above-mentioned (c); 0.0025.ltoreq..beta..ltoreq.0.05; .beta./.alpha..ltoreq.4; 0<x.ltoreq.0.50; 0.ltoreq.1.0; 0.ltoreq.z1.0; 0.ltoreq.y+z<1.0; and 1.000<m.ltoreq.1.035, (2) about 0.5 to 5.

Abstract: A multilayer ceramic capacitor comprising an interlayer, which mitigates stress of a dielectric material cause by a counter piezoelectric phenomenon, provided between capacity-forming layers. The capacity-forming layer preferably comprises seven or more internal electrode layers including a first electrode layer and a second electrode layer, the first electrode layer having two or more electrodes, the second electrode layer having one or more electrodes which all face the first electrode layer, the first and second electrode layers forming two or more capacitor units connected in series. The interlayer preferably has a thickness of from 75 to 900 .mu.m. The interlayer preferably contains internal electrodes having a structure incapable of forming a capacity.

Abstract: A dielectric ceramic composition and a monolithic ceramic capacitor using the composition are provided. The dielectric ceramic composition includes: barium titanate; at least one rare earth oxide selected from terbium oxide, dysprosium oxide, holmium oxide, erbium oxide and ytterbium oxide; manganese oxide and nickel oxide; and magnesium oxide in an amount of from 0.5 to 3.0 mols in terms of MgO, and silicon oxide in an amount of from 0.2 to 5.0 mols in terms of SiO.sub.2, relative to 100 mols of the essential component having the following compositional formula:(1--.alpha.--.beta.){BaO}.sub.m TiO.sub.2 +.alpha.Re.sub.2 O.sub.3 +.beta.(Mn.sub.1-x Ni.sub.x)Owhere Re.sub.2 O.sub.3 is at least one selected from Tb.sub.2 O.sub.3, Dy.sub.2 O.sub.3, Ho.sub.2 O.sub.3, Er.sub.2 O.sub.3 and Yb.sub.2 O.sub.3 ; and.alpha., .beta., m and x are as follows:0.0025.ltoreq..alpha..ltoreq.0.0200.0025.ltoreq..beta..ltoreq.0.04.beta./.alpha..ltoreq.40.ltoreq.x<1.01.000<m.ltoreq.1.035.

Abstract: A multilayer feedthrough capacitor of the present invention has an internal structure of stacking one over another alternately dielectric sheets 1a, on each of which signal feedthrough electrodes 2a, 2b and 2c and separating earth electrodes 7a and 7b are disposed alternately, and dielectric sheets 1b, on each of which earth electrodes 3a and 3b having protrusions 8a and 8b, respectively, are formed. On one pair of the end surfaces of this stacked dielectric body are formed first external electrodes 4a, 4b and 4c that are connected to signal feedthrough electrodes 2a, 2b and 2c, respectively, and third external electrodes 9a and 9b that are connected to both separating earth electrodes 7a and 7b and protrusions 8a and 8b, respectively. On the other pair of the end surfaces are formed second external electrodes 5a and 5b that are connected to earth electrodes 3a and 3b, respectively.

Abstract: An encapsulated capacitor structure and method for fabricating same. The capacitor structure is created by selectively depositing a lower electrode, a dielectric thin film of BST or other ferrodielectric, and an upper electrode, onto a substrate, and subsequently depositing a conformal layer of a non-reductively deposited dielectric material. Contact windows are then opened through the encapsulating layer for contacting the capacitor electrodes. The underlying structure is protected by the encapsulating layer from metal deposition and post-processing which would otherwise damage the structure.

Abstract: Multi-terminal, layered capacitors having excellent attenuation characteristics over a wide frequency range. A four-terminal, layered capacitor has a dielectric sheet with an internal inductor electrode connecting an external input terminal to an external output terminal, dielectric sheets with internal capacitor electrodes connected to the external input terminal, and internal capacitor electrodes connected to the external output terminal, and dielectric sheets with internal ground electrodes connected to external ground terminals. All these dielectric sheets are integrally stacked and calcined to form a one-piece structure.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node, the capacitor plate comprising conductively doped polysilicon; c) providing a predominately amorphous electrically conductive layer over the first capacitor plate; d) providing a capacitor dielectric layer over the amorphous electrically conductive layer; and e) providing a second electrically conductive capacitor plate over the capacitor dielectric layer. A capacitor construction is also disclosed. The invention has greatest utility where the polysilicon layer covered with the amorphous conductive layer is a roughened outer layer, such as provided with hemispherical grain polysilicon. The preferred amorphous electrically conductive layer is metal organic chemical vapor deposited TiC.sub.x N.sub.y O.sub.z, where "x" is in the range of from 0.01 to 0.5, and "y" is in the range of from 0.99 to 0.

Abstract: An MIM capacitor includes a lower electrode; a first insulating film disposed on the lower electrode; a second insulating film disposed on the first insulating film and having a first opening exposing a portion of the surface of the first insulating film on the lower electrode, the first opening having a perimeter; a third insulating film disposed on the second insulating film and having a second opening exposing a portion of the surface of the second insulating film, the second opening having a perimeter that surrounds the perimeter of the first opening on the second insulating film; and an upper electrode disposed on the first insulating film through the first opening and extending onto the second insulating film.

Abstract: A method for forming a stacked container capacitor for use within integrated circuits. Formed successively upon a semiconductor substrate is a first dielectric layer, a second dielectric layer and a patterned mask layer. Within an isotropic etch process, the first dielectric layer etches slower than the second dielectric layer. By means of an anisotropic etch process employing the patterned mask layer as a mask, an aperture is etched at least partially through the first dielectric layer. By means of an isotropic etch process employing the patterned mask layer as a mask, the second dielectric layer is etched to yield a ledge formed above the first dielectric layer and below the patterned masking layer. The patterned mask layer is then removed. Formed then into the anisotropically and isotropically etched aperture is a first polysilicon layer, a third dielectric layer and a second polysilicon layer.

Abstract: A high energy multilayer ceramic capacitor formed of alternating ceramic and electrode layers, the capacitor being suitable for use in implantable medical devices. The ceramic layers are comprised of a dielectric composition of lead magnesium niobate with small amounts of dopants, namely, lithium niobate, copper oxide, magnesium titanate, manganese niobate, and zirconium oxide, with appropriate electrical terminations connected to the electrode layers. The capacitor thus fabricated exhibits greatly reduced ferroelectric effect, namely, less than 30% over a bias range of 0-1,000 volts. It has a breakdown voltage of at least 700 volts, a leakage current less than 10 pico amps at 1,000 volts, an energy density of greater than 10 J/cc, has a rectangular form factor 1.5 inches by 2.0 inches by 0.06 inch thick, and weighs no more than 30 grams.

Abstract: A multi-layer electronic part, such as a multi-layer ceramic capacitor, which comprises internal electrodes stacked alternately with layers of a dielectric material containing at least 50 wt % of lead in terms of PbO and external electrodes connected to the internal electrodes, the external electrodes each comprising a baked electrode layer connected to the internal electrodes; a plating layer having solderability; and a metal particle-containing electrode layer comprising a thermosetting resin and metal particles, between the baked electrode layer and the plating layer, the metal particle-containing electrode layer having a thickness of from 5 to 200 .mu.m, the metal particle-containing electrode layer being disposed between the baked electrode layer and the plating layer.

Abstract: A capacitor structure is described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.

Abstract: An overhanging separator structure with a post projecting from a surface which may be a substrate, an underlying layer on the surface, and a separator layer on the underlying layer, with the separator layer overhanging the underlying layer. A discontinuous film is then formed in a single process step having a first portion on the separator layer and a second portion on the post, the discontinuity caused by the overhanging separator layer. The structure is made into a stacked capacitor with the second (post) portion of the discontinuous film being the bottom electrode, by forming a continuous dielectric layer on the bottom electrode and a continuous top electrode layer on the dielectric layer.

Abstract: A high-capacitance thin film capacitc is compact and has a low profile. A dielectric layer 3 is formed between opposed electrodes 1 and 2. Between the electrodes and the dielectric layer are two layers of conductive particles, 4 and 5.

Abstract: A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

Abstract: A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode.

Abstract: A method of fabricating a multilayer capacitor includes depositing a plurality of electrode layers on a substrate alternately with a plurality of amorphous hydrogenated carbon dielectric layers, forming at least two holes in the electrode and dielectric layers with each hole intersecting alternating ones of the electrode layers, and providing an electrically conductive material in each hole for coupling the alternating ones of the electrode layers. Forming the holes can include forming initial holes and then further exposing selected edge portions of the electrode layers by widening dielectric layer portions of the initial holes. Providing the electrically conductive material can include coating surfaces of the holes with an electrically conductive layer and pouring an electrically conductive filler material into the holes. If filler material is poured into the holes, a capacitor lead can be positioned adjacent the filler material and attached by hardening the filler material.

Abstract: Capacitors and methods of fabricating high dielectric capacitors which do not create a step difference where the high dielectric material is formed are provided. These methods include forming a first electrode layer on an integrated circuit device substrate and a layer of high dielectric material on the first electrode layer opposite the integrated circuit device substrate. A second electrode layer is formed on the layer of high dielectric material opposite the first electrode layer. The first electrode layer, the high dielectric layer and the second electrode layer are patterned to form a capacitor cell unit having a sidewall which extends from the first electrode beyond the layer of high dielectric material and to the second electrode layer. An insulating spacer is formed on the sidewall of the capacitor cell unit extending from the first electrode layer to the second electrode layer.

Abstract: A voltage variable capacitor (VVC) is made by placing an intercalation compound between two electrodes of a capacitor. The VVC has a reservoir of an intercalant in proximity with the intercalation compound. The two materials are chosen from those known to exhibit the intercalation reaction. The extent of the intercalation reaction is controlled by applying a voltage to the intercalant reservoir and the intercalation compound. A variable capacitor is created by applying a signal to the device and appropriately controlling the .di-elect cons. of the device by using the input control voltages.

Abstract: A capacitor construction includes, i) a dense mass of electrically insulative oxide; ii) an electrically conductive inner capacitor plate overlying and contacting the electrically insulative oxide mass; iii) a capacitor dielectric layer overlying the inner capacitor plate and oxide mass, the capacitor dielectric layer comprising a nitride; iv) an electrically conductive outer capacitor plate overlying the capacitor dielectric layer; and v) the dense mass of electrically insulative oxide contacting the inner capacitor plate being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution.

Abstract: Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

Abstract: Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

Abstract: A multi-layer printed circuit board comprises a first metallic layer, a first Ta or Hf layer on one face of the first metallic layer, a first layer of Ta.sub.2 O.sub.5 or HfO on a face of the Ta or Hf layer opposite the first metallic layer, a second metallic layer on the Ta.sub.2 O.sub.5 or HfO layer opposite the Ta or Hf layer, a first dielectric layer on the first metallic layer opposite the Ta of Hf layer, and a second dielectric layer on the second metallic layer opposite the Ta.sub.2 O.sub.5 or HfO layer. A multi-layer printed circuit board is formed by adding the following layers to form the second capacitor. A third metallic layer on said second dielectric layer, a second Ta or Hf layer on a face of the third metallic layer, a second Ta.sub.2 O.sub.5 or HfO layer on a face of the second Ta or Hf layer opposite the third metallic layer, a fourth metallic layer on the second Ta.sub.2 O.sub.

Abstract: Method and apparatus for fabricating fine pitch pattern multilayer printed circuit boards involving laminar stackable board layers providing power distribution, signal distribution and capacitive decoupling. In one respect, the invention relates to the fabrication of board layers by beginning with a metallic core, patterning the core, selectively enclosing the core in a dielectric, selectively depositing metal to form vias, plugs and signal lines, and forming dendrites with joining metallurgy on the vias and plugs to provide stackable connection from above or below the plane of the board layer. In another aspect, the invention is directed to the use of a sol-gel process to form a thin high dielectric constant crystalline film onto a metallic sheet followed with a deposition of a metallic layer onto the high dielectric constant film.

Abstract: A multi-layer film capacitor structure has a bottom electrode layer on a monolithic substrate, intermediate pairs of layers of film electrode and dielectric material overlying the bottom electrode, and a top pair of layers of a film electrode and film dielectric overlying the intermediate pairs. The structure preferably has a mesa configuration, in which each electrode layer extends laterally beyond the periphery of the layers above it around the entire periphery of the device. Each electrode layer therefore has a top surface which is accessible at its projecting edge through a via, so that the electrodes can be accessed in any combination to permit any desired circuit connection. If desired the dielectric materials can have different frequency characteristics, allowing a single capacitor structure to be optimized for a filter. Either the bottom electrode or the top electrode or both can be grounded and capacitor connections can be made to intermediate layers, to reduce parasitic capacitance effects.

Abstract: A method for fabricating a capacitor on a substrate includes the steps of forming an insulating layer on the substrate, and forming the first plate electrode on the insulating layer. A first dielectric layer is then formed on the plate electrode, and a first common storage electrode is formed on the first dielectric layer. A contact hole is then formed through the insulating layer, the first plate electrode, the first dielectric layer, and the first common storage electrode, thereby exposing a predetermined portion of the substrate. A first spacer is formed on a sidewall of the contact hole, and a conductive plug is formed in the contact hole extending from the substrate to the first common storage electrode.

Abstract: Disclosed is a monolithic ceramic capacitor comprising dielectric ceramic layers made from a material which comprises an essential component of (1-.alpha.-.beta.){BaO}.sub.m.TiO.sub.2 +.alpha.Re.sub.2 O.sub.3 +.beta.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)O (0.0025.ltoreq..alpha..ltoreq.0.025; 0.0025.ltoreq..beta..ltoreq.0.05; .beta./.alpha..ltoreq.4; 0.ltoreq.x<1.0; 0.ltoreq.y<1.0; 0.ltoreq.x+y<1.0; 1.000<m.ltoreq.1.035) and from about 0.5 to 5.0 mols, relative to 100 mols of the essential component, of a side component MgO, and containing from about 0.2 to 3.0 parts by weight, relative to 100 parts by weight of said components, of an oxide of the type of SiO.sub.2 --TiO.sub.2 --MO. The capacitor is low-priced and can be small-sized, while having large-capacity. It has a dielectric constant of 3000 or more, and has a high insulation resistance of 6000 M.OMEGA...mu.F or more and 2000 M.OMEGA...mu.F or more at room temperature and 125.degree. C., respectively.

Abstract: Sheet capacitive materials for use in forming a thin-film capacitor comprise an electrically nonconductive substrate, a layer of electrically conductive material disposed a surface of the substrate, and a layer of electrically nonconductive material disposed onto a surface of the conductive material layer. The conductive material layer includes a contact area along a first lengthwise edge of the substrate that is thicker than remaining portions of the material layer. A portion of the substrate adjacent a second lengthwise edge remains exposed. The electrically nonconductive material includes an anti-stick component, and covers the exposed substrate surface and a major portion of the material layer except for the contact area. A first and second sheet is constructed having contact areas along opposite lengthwise edges. The sheets are placed together so that the contact areas are oriented at opposite lengthwise edges, and are staggered so that the contact areas remain exposed.

Abstract: A ferroelectric capacitor structure variously having ceramic lower and upper electrodes, lower and upper insert layers, metal lower and upper electrodes, and a ferroelectric. The ceramic electrode(s) are variously connected with a writing terminal, and the metal electrodes are variously connected with a reading terminal. The use of a combination of metal and ceramic electrodes avoids both fatigue and leakage current.

Abstract: Disclosed is a monolithic ceramic capacitor comprising dielectric ceramic layers made from a material which comprises an essential component of (1-.alpha.-.beta.){BaO}.sub.m .cndot.TiO.sub.2 +.alpha.Re.sub.2 O.sub.3 30 .beta.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)O (0.0025.ltoreq..alpha..ltoreq.0.025; 0.0025.ltoreq..beta..ltoreq.0.05; .beta./.alpha..ltoreq.4; 0.ltoreq.x<1.0; 0.ltoreq.y<1.0; 0.ltoreq.x+y<1.0; 1.000<m.ltoreq.1.035) and from about 0.1 to 3.0 mols, relative to 100 mols of the essential component, of a side component MgO, and contains from about 0.2 to 3.0 parts by weight, relative to 100 parts by weight of said components, of an oxide of the type of Li.sub.2 O-B.sub.2 O.sub.3 -(Si,Ti)O.sub.2. The capacitor is low-priced and can be small-sized, while having large-capacity. It has a dielectric constant of 3000 or more, and has a high insulating resistance of 6000 M.OMEGA..cndot..mu.F or more and 2000 M.OMEGA..cndot..mu.F or more at 2 KV/mm and at room temperature and 125.degree. C.

Abstract: A high energy density, high power density capacitor having an energy density of at least about 0.5 J/cm.sup.3 is provided. The capacitor comprises a plurality of interleaved metal electrode layers separated by a polymer layer. The interleaved metal electrode layers terminate at opposite ends in a solder termination strip. The high energy density aspect of the capacitors of the invention is achieved by at least one of the following features: (a) the dielectric thickness between the interleaved metal electrode layers is a maximum of about 5 .mu.m; (b) the polymer is designed with a high dielectric constant .kappa. of at least about 3.5; (c) the metal electrode layers within the polymer layer are recessed along edges orthogonal to the solder termination strips to prevent arcing between the metal electrode layers at the edges; and (d) the resistivity of the metal electrode layers is within the range of about 10 to 500 ohms per square, or a corresponding thickness of about 200 to 30 .ANG..

Abstract: Disclosed is a monolithic ceramic capacitor comprising dielectric ceramic layers made from a ceramic composition, which comprises an essential component of (1-.alpha.-.beta.) {BaO}.sub.m .multidot.TiO.sub.2 +.alpha.{(1-x)M.sub.2 O.sub.3 +xRe.sub.2 O.sub.3 }+.beta.(Mn.sub.1-y-z Ni.sub.y Co.sub.z)O (0.0025.ltoreq..alpha..ltoreq.0.025; 0.0025.ltoreq..beta..ltoreq.0.05; .beta./.alpha..ltoreq.4; 0<x.ltoreq.0.50; 0.ltoreq.y<1.0; 0.ltoreq.z<1.0; 0.ltoreq.y+z<1.0; 1.000<m.ltoreq.1.035) and from 0.5 to mols, relative to 100 mols of the essential component, of a side component MgO, and contains from 0.2 to 3.0 parts by weight, relative to 100 parts by weight of said components, of an oxide of the type of Li.sub.2 O--(Si,Ti)O.sub.2 --Al.sub.2 O.sub.3 --ZrO.sub.2. The capacitor can be small-sized while having large capacity. It can be produced even through baking in atmospheres having a low oxygen partial pressure without producing semiconductors.

Abstract: A capacitor includes a substrate having a first trench, and a second trench, a first storage node having a first body and a first flange, the first body being on the first trench and having a first height and the first flange being extended at a top portion of the first body to a first length from the first body, a second storage node having a second body and a second flange, the second body being in the second trench and having a second height different from the first height of the first body, and the second flange being extended in a direction opposite to the first flange to a second length from the second length from the second body, a dielectric film on the surfaces of the first and second storage nodes, and a plate electrode on the dielectric film.

Abstract: A cardiac defibrillator includes a multilayer capacitor with a plurality of conductive electrodes and interspersed dielectric layers, each dielectric layer composed of constituents which cause it to exhibit an antiferroelectric phase. The constituents of each dielectric layer are such as to cause each layer to exhibit plural ferroelectric phases. The defibrillator includes a charging circuit for applying to the capacitor an electric field across each dielectric layer which causes a transition thereof through the plural ferroelectric phases. PLZT is the preferred dielectric material, at constituent values which cause the material to lie within the antiferroelectric phase and to exhibit plural ferroelectric phases.

Abstract: When forming a zinc-deposited base material for metallized capacitors, a primer layer for zinc-deposition made from at least one compound selected from the group comprised of an oxide of silicon, titanium and zirconium is formed on at feast one side surface of a base body comprised of a film or a thin condenser paper. Next, a zinc-deposited layer is formed on top of the primer layer. Then, a protective layer made from at least one compound selected from the group comprised of silicon-based oil, fluoro-based oil, alkylnaphthalene, polydiphenylether, fatty acids, fatty acid salts and paraffin wax is formed on top of the zinc-deposited layer. In this way, it becomes possible to form a zinc-deposited base material having excellent moisture resistance when used for metallized capacitors.