Plural Dielectrics Patents (Class 361/312)
  • Patent number: 10147546
    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the pair external electrodes, a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, being within ±20% of an average of the concentrations of the base metal in the five regions, an average grain number in the dielectric layer being three or less in the stacking direction between the first and second internal electrodes.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 4, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Katsuya Taniguchi, Minoru Ryu, Yoshiki Iwazaki
  • Patent number: 10141113
    Abstract: A ceramic electronic component includes an interior part and an exterior part. The interior part includes an interior part dielectric layer and an internal electrode layer. The exterior part includes an exterior part dielectric layer. The exterior part is positioned outside the interior part along a laminating direction thereof. The interior part dielectric layer and the exterior part dielectric layer respectively contain barium titanate as a main component. ????0.20 and ?/??0.88 are satisfied, where ? mol part and ? mol part are respectively an amount of a rare earth element contained in the interior and exterior part dielectric layers, provided that an amount of barium titanate contained in the interior and exterior part dielectric layers is respectively 100 mol parts in terms of BaTiO3.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: November 27, 2018
    Assignee: TDK Corporation
    Inventors: Masayuki Sato, Yosuke Konno, Shunichi Yuri, Takashi Morita, Tsutomu Odashima, Yushi Kanou, Kenta Yamashita
  • Patent number: 9947476
    Abstract: A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: April 17, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Kitano, Takanobu Katsuyama, Hiroaki Sugita
  • Patent number: 9911542
    Abstract: An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of ?55 degrees C.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: March 6, 2018
    Assignee: GranBlueTech, L.L.C.
    Inventor: John P. Snyder
  • Patent number: 9881739
    Abstract: A multilayer ceramic capacitor provided in a multilayer printed wiring board includes a ceramic body with a plurality of ceramic layers and internal electrodes stacked, and an external electrode including a base layer that includes a sintered metal containing a metal and glass and a plated layer provided on the surface of the base layer, which is provided on an end surface of the ceramic body to be connected to the internal electrodes. The external electrode includes a principal surface portion disposed on a principal surface of the ceramic body. The outermost layer of the plated layer includes a Cu plated layer. The ratio of arithmetic mean roughness (Ra) at the surface of the ceramic body/arithmetic mean roughness (Ra) at the surface of the external electrode satisfies a condition: about 0.06?the arithmetic mean roughness (Ra) at the surface of the ceramic body/the arithmetic mean roughness (Ra) at the surface of the external electrode?about 0.97.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 30, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takehisa Sasabayashi
  • Patent number: 9728336
    Abstract: A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 8, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shota Kitano, Takanobu Katsuyama, Hiroaki Sugita
  • Patent number: 9570235
    Abstract: A multilayer ceramic capacitor that is highly resistant to insulation degradation under high-temperature load includes an inner ceramic layer that has a composition mainly composed of a perovskite-type compound containing Ba and Ti, at least one of Nb and Ta, contains Mn and Al, and optionally contains Mg and a rare-earth element that is at least one of Y, Gd, Tb, Dy, Ho, and Er, with a content of Ti being 100 parts by mole, and (a) a total of Nb and Ta is from about 0.2 to about 1.5 part by mole, (b) Mg is not more than about 0.2 part by mole including 0 part by mole, (c) Mn is from about 1.0 to about 3.5 parts by mole, (d) Al is from about 1.0 to about 4.0 parts by mole, and (e) the rare-earth element is not more than about 0.05 part by mole including 0 part by mole. Furthermore, an average number of particles per one layer of the inner ceramic layer is not more than 3.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 14, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takafumi Okamoto
  • Patent number: 9466426
    Abstract: Provided is a laminated ceramic capacitor which can suppress degradation of the insulation resistance due to the addition of vanadium. Second insulating layers are stacked on both sides in the stacking direction of a first insulating layer group, which has first insulating layers stacked over one another, and internal electrodes are placed on principal surfaces of the first insulating layers. At least one internal electrode is placed between the first and second insulating layers. Both contain, as their main constituent, a perovskite-type compound represented by the formula “ABO3” wherein “A” denotes at least one of Ba, Sr, and Ca, “B” denotes at least one of Ti, Zr, and Hf. V is added to only the first insulating layers.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 11, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kohei Shimada, Hiroyuki Wada, Keisuke Araki, Hiroyuki Yoshioka, Masato Ishibashi
  • Patent number: 9431176
    Abstract: A multilayer ceramic electronic component including: a ceramic body having a plurality of dielectric layers stacked therein; active layers including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layers interposed therebetween; and first and second external electrodes formed on the both end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. The active layers may include a first active layer including a ferroelectric layer and a second active layer including a paraelectric layer, the first and second active layers being alternately stacked.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Doo Young Kim, Young Ghyu Ahn
  • Patent number: 9418792
    Abstract: A multilayer ceramic capacitor includes ceramic grains forming a dielectric layer of the multilayer ceramic capacitor, which ceramic grains contain a coarse ceramic grain SPr having a coarse grain size Dcoa that satisfies the condition of Tmin ?Dcoa ?Tmax where Tmax is the maximum thickness of the dielectric layer and Tmin is the minimum thickness of the dielectric layer. The multilayer ceramic capacitor is capable of inhibiting deterioration of capacitance and capacity-temperature characteristics even when the internal electrode layer is made thin.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: August 16, 2016
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yukihiro Konishi, Yuichi Kasuya, Jun Nishikawa, Katsuya Taniguchi, Kotaro Mizuno, Yusuke Kowase, Shohei Kitamura
  • Patent number: 9373445
    Abstract: A multilayer ceramic capacitor includes a multilayer body including a plurality of stacked dielectric layers including a dielectric ceramic that includes a plurality of crystal grains and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric layers, and external electrodes. The multilayer body includes a Ba and Ti containing perovskite compound, La, Mg, Mn and Al, and satisfies conditions such that in a case in which a content of Ti is set to 100 molar parts, a fraction of each content of La, Mg, Mn and Al relative to the content of Ti is such that La is about 0.2 to about 1.2 molar parts, Mg is about 0.1 molar part or less, Mn is about 1.0 to about 3.0 molar parts and Al is about 0.5 to about 2.5 molar parts, and an average number of crystal grains included in each of the dielectric layers in the stacking direction is one or more to three or less.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takafumi Okamoto
  • Patent number: 9362053
    Abstract: A multilayer ceramic capacitor includes a multilayer body including a plurality of stacked dielectric layers including a dielectric ceramic that includes a plurality of crystal grains and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric layers, and external electrodes. The multilayer body includes a Ba and Ti containing perovskite compound, La, Mg and Mn, and satisfies conditions such that in a case in which a content of Ti is set to 100 molar parts, a fraction of each content of La, Mg and Mn relative to the content of Ti is such that La is about 1.2 to about 6.0 molar parts, Mg is about 0.5 to about 5.0 molar parts and Mn is about 1.0 to about 3.0 molar parts, and an average number of crystal grains included in each of the dielectric layers in the stacking direction is one or more to three or less.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: June 7, 2016
    Assignee: Murata Manufacturing Co. Ltd.
    Inventor: Takafumi Okamoto
  • Patent number: 9355781
    Abstract: Provide is a laminated ceramic capacitor which can suppress the decrease in dielectric constant even when ceramic layers are further reduced in thickness. The laminated ceramic capacitor includes a laminate having a plurality of stacked ceramic layers stacked and a plurality of internal electrodes formed along interfaces between the ceramic layers; and a plurality of external electrodes formed on the outer surface of the laminate and electrically connected to the internal electrodes ceramic grains in contact with both of adjacent internal electrodes adjacent with a ceramic layer interposed therebetween are present in the ceramic layers and the internal electrodes are 0.60 ?m or less in thickness.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 31, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takayuki Yao
  • Patent number: 9252204
    Abstract: A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: February 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: James W. Adkisson, Panglijen Candra, Kevin N. Ogg, Anthony K. Stamper
  • Patent number: 9178007
    Abstract: A high breakdown voltage metal-insulator-metal capacitor for compound semiconductor integrated circuit comprises a substrate, an isolation layer, a first metal layer, a dielectric layer, an adhesion layer and a second metal layer. The dielectric layer is formed by alternately stacking plural HfO2 layers and plural SiO2 layers. The thickness of each layer of the plural HfO2 layers is between 30 ? to 100 ? so as to reduce the leakage current, enhance the breakdown voltage and increase the capacitance density of each layer of the plural HfO2 layers. And the total thickness of the dielectric layer is thicker than 500 ? such that the breakdown voltage of the capacitor is higher than 50 V.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: November 3, 2015
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Winson Shao, Ben Hsu, Wen Chu
  • Patent number: 9161447
    Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: October 13, 2015
    Assignee: Sanmina-SCI Corporation
    Inventor: George Dudnikov
  • Patent number: 9030800
    Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 12, 2015
    Assignee: TDK Corporation
    Inventors: Tatsuo Namikawa, Yoshihiko Yano, Yasunobu Oikawa
  • Patent number: 8950057
    Abstract: A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: February 10, 2015
    Assignee: Valtion Teknillinen Tutkimuskeskus
    Inventors: Tommi Riekkinen, Tomi Mattila
  • Patent number: 8934215
    Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: January 13, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Hang Kyu Cho, Young Ghyu Ahn, Jae Yeol Choi, Doo Young Kim, Seok Hyun Yoon, Ji Young Park
  • Patent number: 8830655
    Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Trench Limited
    Inventors: Paolo Diamanti, Lorin Bratu, Ross McTaggart, Jorge Ribeiro, Keith Lobban
  • Patent number: 8760846
    Abstract: An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of ?55 degrees C.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: June 24, 2014
    Assignee: GranBlueTech, L.L.C.
    Inventor: John P. Snyder
  • Patent number: 8755547
    Abstract: A method of enhancing the intelligibility of sounds including the steps of: detecting primary sounds emanating from a first direction and producing a primary signal; detecting secondary sounds emanating from the left and right of the first direction and producing secondary signals; delaying the primary signal with respect to the secondary signals; and presenting combinations of the signals to the left and right sides of the auditory system of a listener.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 17, 2014
    Assignee: Hear IP Pty Ltd.
    Inventors: Jorge Patricio Mejia, Simon Carlille, Harvey Albert Dillon
  • Patent number: 8749949
    Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: June 10, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: George J. Caporaso, Stephen E. Sampayan, David M. Sanders
  • Patent number: 8743529
    Abstract: A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: June 3, 2014
    Assignee: Clemson University Research Foundation
    Inventors: Todd Hubing, Hocheol Kwak, Haixin Ke
  • Patent number: 8730648
    Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: May 20, 2014
    Assignee: Epcos AG
    Inventors: Uwe Wozniak, Thomas Feichtinger, Hermann Gruenbichler, Pavol Dudesek, Thomas Puerstinger
  • Patent number: 8721820
    Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: May 13, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Sato, Yukio Sanada, Yasuhiro Nishisaka
  • Patent number: 8724290
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Rahul Panat
  • Patent number: 8699204
    Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: April 15, 2014
    Assignee: AVX Corporation
    Inventors: Ronald S. Demcko, Jeff Cheng, Michael Kirk
  • Patent number: 8693162
    Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 8, 2014
    Assignee: BlackBerry Limited
    Inventors: Mircea Capanu, Andrew Cervin-Lawry, Marina Zelner
  • Patent number: 8605410
    Abstract: To provide a thin-film capacitor capable of improving the stability of electric connection between an internal electrode layer and a connection electrode. The thin-film capacitor comprises: two or more dielectric layers deposited above a base electrode; an internal electrode layer being deposited between the dielectric layers and having a projecting portion which projects from the dielectric layer when seen from a laminating direction; and a connection electrode electrically connected to the internal electrode layer via at least a part of a surface and an end face of the internal electrode layer included in the projecting portion, wherein a ratio L/t between a projection amount L of the projecting portion of the internal electrode layer with respect to the dielectric layer and a thickness t of the internal electrode layer is 0.5 to 120.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: December 10, 2013
    Assignee: TDK Corporation
    Inventors: Yasunobu Oikawa, Yoshihiko Yano
  • Patent number: 8570711
    Abstract: There is provided a multilayered ceramic electronic component including: a ceramic main body having a dielectric layer, the ceramic main body having a length of 1.79 mm or less and a width of 1.09 mm or less; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic main body; and a first external electrode electrically connected to the first internal electrode and a second external electrode electrically connected to the second internal electrode, wherein, when it is defined that the shortest length of at least one of the first and second external electrodes, formed in the lengthwise direction from both end portions of the ceramic main body is A, and the longest length thereof is BW, a relational expression of 0.5?A/BW<1.0 may be satisfied.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 29, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Byung Kil Seo, Byung Sung Kang
  • Patent number: 8531816
    Abstract: A capacitor forming unit includes a dielectric plate, a first conductor film formed on a plate upper surface region other than front and rear end portions, a first insulator film formed on the upper surface front end portion, a second insulator film formed on the upper surface rear end portion, a second conductor film formed on a plate lower surface region other than front and rear end portion, a third insulator film formed on the front end portion lower surface, and a fourth insulator film formed on the lower surface rear end portion. One or more first electrode rods are disposed in through holes, and electrically connected to the first conductor film and electrically insulated from the second conductor film. One or more second electrode rods are disposed in other through holes, and electrically connected to the second conductor film and electrically insulated from the first conductor film.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 10, 2013
    Assignee: Taiyo Yuden Co., Ltd
    Inventors: Yoshinari Take, Hidetoshi Masuda, Kenichi Ota
  • Patent number: 8508914
    Abstract: A ceramic electronic component includes a first dielectric layer, a second dielectric layer, and an intermediate layer. The first dielectric layer is a layer containing BaO, Nd2O3, and TiO2, the second dielectric layer is a layer containing a different material from the material of the first dielectric layer, and the intermediate layer is a layer formed between the first dielectric layer and the second dielectric layer and containing main components that are not contained in the first dielectric layer and the second dielectric layer in common as the main components.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: August 13, 2013
    Assignee: TDK Corporation
    Inventors: Toshio Sakurai, Hisashi Kobuke, Tomohiro Arashi, Takahiro Nakano, Yasuharu Miyauchi
  • Patent number: 8508912
    Abstract: A capacitor includes a capacitor body made of a dielectric, a first internal electrode, a second internal electrode, a first signal terminal, a second signal terminal, and a grounding terminal. The first and second signal terminals are connected to the first internal electrode. The grounding terminal is disposed on the outer surface of the capacitor body so as to be connected to the second internal electrode. The grounding terminal is connected to the ground potential. The grounding terminal includes a plating layer which is disposed on the capacitor body and which is connected to the second internal electrode.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigekatsu Yamamoto, Takao Hosokawa
  • Patent number: 8498095
    Abstract: A thin-film capacitor that is less prone to generation of internal cracking or peeling is provided. In a thin-film capacitor according to the present embodiment, because through holes H are formed in internal electrodes containing Ni as a principal component in a lamination direction, a surface area of at least some of the through holes H is in the range of 0.19 ?m2 to 7.0 ?m2, and a ratio of a surface area of the through holes H to a surface area of an entire main surface of the internal electrodes is in the range of 0.05% to 5%, peeling or cracking is suppressed from occurring at the boundaries between the internal electrodes and dielectric layers, and as a result, the yield is enhanced.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 30, 2013
    Assignee: TDK Corporation
    Inventors: Yoshihiko Yano, Yasunobu Oikawa, Kenji Horino, Hitoshi Saita
  • Patent number: 8462482
    Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: June 11, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K) Ltd.
    Inventors: Yoshitaka Sasaki, Atsushi Iijima, Hiroshi Ikejima
  • Patent number: 8440299
    Abstract: A composite dielectric material having a plurality of particle cores, each surrounded by polymer strands that are chemically bonded to the surface of the particle core. Each polymer strand includes a linker, through which the polymer strand is attached to the surface, an interfacial core-shielding (ICS) group bound to the linker, and a polymer molecule bound to the ICS group. The ICS groups are designed to inhibit electrical breakdown of the composite dielectric material by (i) deflecting or scattering free electrons away from the particle cores and/or (ii) capturing free electrons by being transformed into relatively stable radical anions. Representative examples of the particle core material, linker, ICS group, and polymer molecule are titanium dioxide, a phosphonate group, a halogenated aromatic ring, and a polystyrene molecule, respectively.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: May 14, 2013
    Assignee: LGS Innovations LLC
    Inventor: Ashok J. Maliakal
  • Patent number: 8432662
    Abstract: In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 30, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Atsushi Iijima, Hiroshi Ikejima
  • Patent number: 8416556
    Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: April 9, 2013
    Assignees: Conti Temic Microelectronic GmbH, EPCOS AG
    Inventors: Wilhelm Grimm, Wilhelm Hübscher, Harald Vetter, Gerhard Hiemer, Edmund Schirmer, Hermann Kilian, Hermann Bäumel, George Dietrich
  • Patent number: 8412495
    Abstract: The method for adjusting a hearing device (11) to the hearing preferences of a user of the hearing device comprises a) adjusting at least one of N parameters (P1, P2), preferably with 2?N?4; b) obtaining a gain model (G), which is identical with the output of a fitting rationale (F) applied to a model audiogram (A), wherein the model audiogram depends on the N parameters and is independent of possibly existing audiogram values measured for the user; and c) using the gain model (G) or a gain model derived therefrom in said hearing device (11). Preferably, the model audiogram (A) is an approximation to an audiogram occurring in a pre-defined empirical sample of individual audiograms. The user preferably carries out the method by himself and without external equipment. A corresponding arrangement (1) is disclosed, too. A simple and efficient hearing device fitting can be achieved.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: April 2, 2013
    Assignee: Phonak AG
    Inventor: Michael Boretzki
  • Patent number: 8395880
    Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Medtronic, Inc.
    Inventor: James R. Wasson
  • Patent number: 8390984
    Abstract: The disclosed is a capacitor substrate structure to reduce the high leakage current and low insulation resistance issue of organic/inorganic hybrid materials with ultra-high dielectric constant. The insulation layer, disposed between two conductive layers, includes multi-layered dielectric layers. At least one of the dielectric layers has high dielectric constant, including high dielectric constant ceramic powder and conductive powder evenly dispersed in organic resin. The other dielectric layers can be organic resin, or further include high dielectric constant ceramic powder dispersed in the organic resin. The substrate has an insulation resistance of about 50K? and leakage current of below 100 ?Amp under operational voltage.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Shur-Fen Liu, Meng-Huei Chen, Bih-Yih Chen, Yun-Tien Chen
  • Patent number: 8385047
    Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: February 26, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Huikai Xie, Khai D. T. Ngo
  • Patent number: 8373966
    Abstract: A structural body which includes a first dielectric layer formed on a first substrate and including first conductive particles, each surface of the first conductive particles being entirely covered with a first dielectric film; and a second dielectric layer formed on the first dielectric layer wherein a volume ratio of a dielectric in the second dielectric layer is higher than a volume ratio of a dielectric in the first dielectric layer.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: February 12, 2013
    Assignee: Fujitsu Limited
    Inventor: Yoshihiko Imanaka
  • Patent number: 8355240
    Abstract: A multilayer capacitor operable to allow adjustment of its equivalent series resistance substantially independent of its equivalent series inductance is disclosed. The multilayer capacitor can be used in decoupling circuits such as power supply decoupling circuits. The equivalent series resistance of the multilayer capacitor can be increased while suppressing an increase in the equivalent series inductance resulting in improved noise grounding.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: January 15, 2013
    Assignee: KYOCERA Corporation
    Inventor: Hisashi Satou
  • Patent number: 8339765
    Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon-Sang Choi, Ki-Vin Im, Se-Hoon Oh, Sang-Yeol Kang, Cha-Young Yoo
  • Patent number: 8331076
    Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: December 11, 2012
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8315032
    Abstract: A ductile preform for making a drawn capacitor includes a plurality of electrically insulating, ductile insulator plates and a plurality of electrically conductive, ductile capacitor plates. Each insulator plate is stacked vertically on a respective capacitor plate and each capacitor plate is stacked on a corresponding insulator plate in alignment with only one edge so that other edges are not in alignment and so that each insulator plate extends beyond the other edges. One or more electrically insulating, ductile spacers are disposed in horizontal alignment with each capacitor plate along the other edges and the pattern is repeated so that alternating capacitor plates are stacked on alternating opposite edges of the insulator plates. A final insulator plate is positioned at an extremity of the preform. The preform may then be drawn to fuse the components and decrease the dimensions of the preform that are perpendicular to the direction of the draw.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 20, 2012
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8305730
    Abstract: A method for manufacturing a capacitor includes the steps of: sequentially laminating, on a substrate, a lower electrode layer, a dielectric layer and an upper electrode layer; forming a patterned mask layer on the upper electrode layer; patterning at least the upper electrode layer and the ferroelectric layer using the mask layer as a mask; removing the mask layer; and conducting a plasma treatment to contact plasma with an exposed surface of the dielectric layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 6, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Masao Nakayama
  • Patent number: RE43868
    Abstract: This invention provides navel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 25, 2012
    Assignee: Nanosys, Inc.
    Inventors: Calvin Y. H. Chow, Robert Dubrow