Abstract: A glass core multilayer wiring board includes a glass substrate, a through electrode, a first layer structure, and a second layer structure. A through hole has a diameter decreasing from a first surface toward a second surface. The through electrode is along a side wall of the through hole. The first layer structure is on the first surface and the second layer structure is on the second surface. The second layer structure closes an opening in the second surface defining a bottom section. The through electrode has: a first layer on part of the side wall and on part or all of the bottom section of the through hole closing the opening of the through hole, a second layer covering the first layer, the side wall of the through hole exposed, and the bottom section, and a third layer is located on the second layer.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b).

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

Abstract: Provided is a metal-air battery including a cathode having a space which may be filled with a metal oxide formed during a discharge of the metal-air battery and thus having improved energy density and lifespan. The cathode for the metal-air battery includes a plurality of cathode materials, a plurality of electrolyte films disposed on surfaces of the plurality of cathode materials, and a plurality of spaces which are not occupied by the plurality of cathode materials and the plurality of electrolyte films. A volume of the plurality of spaces may be greater than or equal to a maximum space of a metal oxide formed during a discharge of the metal-air battery.

Abstract: A multilayer ceramic capacitor includes a body including a first dielectric layer on which a first internal electrode, a first coupling portion, and a second internal electrode are disposed, a second dielectric layer on which a third internal electrode, a second coupling portion, and a fourth internal electrode are disposed, and a third dielectric layer on which a fifth internal electrode or a sixth internal electrode is disposed, and first and second external electrodes connected to the first to sixth internal electrodes, and disposed on both surfaces of the body in the first direction. The first to third dielectric layers are sequentially stacked.

Abstract: A method of preparing a sample for physical analysis is disclosed, which is characterized by forming a low-temperature atomic layer deposition (ALD) metal nitride film or a low-temperature atomic layer deposition (ALD) metal oxynitride film by plasma-less enhanced atomic layer deposition (PLALD) at a temperature below 40° C. on a specimen to generate a sample for physical analysis to prevent the surface of sample for physical analysis from being damaged during physical analysis.

Abstract: A multilayer electronic component includes a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers between adjacent dielectric layers of the plurality of stacked dielectric layers. The plurality of stacked dielectric layers each have a plurality of crystal grains including a first phase. The multilayer body defines an electrode facing portion where the plurality of internal electrode layers and the plurality of stacked dielectric layers face each other, and defines an external peripheral portion surrounding the electrode facing portion. A portion of the plurality of stacked dielectric layers in the external peripheral portion include, in at least some of grain boundaries of the plurality of crystal grains, a second phase including at least one of Sn, Cu, Fe, Ni, Cr, Mn, V, Al, and P, and the second phase is a different compound from the first phase.

Abstract: An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of ?55 degrees C.

Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and first and second external electrodes disposed outside of the ceramic body and connected to the first and second internal electrodes, respectively. The ceramic body includes an active portion including of the first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween to form capacitance, and a cover portion disposed in upper and lower portions of the active portion. The cover portion has a larger number of pores than the dielectric layer of the active portion, and the cover portion includes a ceramic-polymer composite filled with a polymer in the pores of the cover portion.

Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and first and second internal electrodes; first and second external electrodes; and an insulator disposed on a first surface of the capacitor body. The capacitor body includes an active region in which first and second internal electrodes overlap each other in a first direction, and upper and lower covers disposed above and below the active region in the first direction. A length of the active region in the second direction is defined as ‘La’, a length of one margin of the capacitor body in the second direction is defined as ‘Lm’, a height of the active region in the first direction is defined as ‘Ta’, a thickness of the lower cover of the capacitor body is defined as ‘Tc’, and a thickness of the insulator is defined as ‘Te’. A relative displacement index, ((La/Lm)?(Ta/Tc))/Te)2, ranges from 0.003 to 0.055.

Abstract: A capacitor that includes a substrate, a dielectric portion, and a conductor layer. The dielectric portion includes a thick film portion and a thin film portion. The thick film portion has a thickness larger than the average thickness of the dielectric portion in a direction perpendicular to the first main surface. The thin film portion has a thickness smaller than the average thickness of the dielectric portion in the direction perpendicular to the first main surface. The thick film portion has a larger relative permittivity than the thin film portion.

Abstract: An electronic device includes a first electric element a second electric element, and a circuit board. The circuit board is configured to deliver a signal between the first electric element and the second electric element. The circuit board includes a first portion, a second portion, and a third portion. The second and third portions extend from the first portion with the first portion therebetween. The circuit board also includes at least one signal line extending from the second portion to the third portion, a plurality of ground patterns extending from the second portion to the third portion, a plurality of first conductive vias positioned at the second portion and electrically connecting the plurality of ground patterns, and a plurality of second conductive vias positioned at the third portion and electrically connecting the plurality of ground patterns. The plurality of ground patterns include a meander form at the first portion.

Abstract: A multilayer ceramic capacitor includes a body including a first dielectric layer on which a first internal electrode, a first coupling portion, and a second internal electrode are disposed, a second dielectric layer on which a third internal electrode, a second coupling portion, and a fourth internal electrode are disposed, and a third dielectric layer on which a fifth internal electrode or a sixth internal electrode is disposed, and first and second external electrodes connected to the first to sixth internal electrodes, and disposed on both surfaces of the body in the first direction. The first to third dielectric layers are sequentially stacked.

Abstract: The present invention is directed to a surface mount coupling capacitor and a circuit board containing a surface mount coupling capacitor. The coupling capacitor includes a main body containing at least two sets of alternating dielectric layers and internal electrode layers. The coupling capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposing the top surface of the coupling capacitor.

Abstract: A multilayer ceramic capacitor includes: a ceramic multilayer structure designated to have ceramic dielectric layers and internal electrode layers alternately stacked, the internal electrode layers being mainly composed of a transition metal other than an iron group, end edges of the internal electrode layers being alternately exposed to a first end face and a second end face; and a pair of external electrodes provided on the first end face and the second end face, wherein: the external electrodes have a base conductive layer and a first plated layer; the base conductive layer directly contacts the ceramic multilayer structure; a main component of the base conductive layer is a noble metal or a transition metal other than an iron group; and a total concentration of Si and B in a second-phase not contacting the ceramic multilayer structure is 0.3 wt % or less, in the base conductive layer.

Abstract: A multicomponent dielectric film includes discrete overlapping dielectric layers of at least a first polymer material, a second polymer material, and a third polymer material. Adjoining dielectric layers define a generally planar interface therebetween which lies generally in an x-y plane of an x-y-z coordinate system. The interfaces between the layers delocalizing the charge build up in the layers. At least one dielectric layer including a stack of discrete polymer layers with polymer layer interfaces extending transverse to the x-y plane and optionally at least one filler having a higher dielectric constant than the first polymer material, the second polymer material, and/or the third polymer material.

Abstract: A multilayer polymer dielectric film includes a stack of coextruded, alternating first dielectric layers and second dielectric layers that receive electrical charge. The first dielectric layers include a first polymer material and the second dielectric layers include a second polymer material different from the first polymer material. The first polymer material has a permittivity greater than the second polymer material. The second polymer material has a breakdown strength greater than the first polymer material. Adjoining first dielectric layers and second dielectric layers define an interface between the layers that delocalizes electrical charge build-up in the layers. The stack has substantially the crystallographic symmetry before and during receiving electrical charge.

Abstract: A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.

Abstract: A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces thereof; and external electrodes formed on the two edge faces; wherein: the external electrodes have a structure in which a plated layer is formed on a ground layer whose main component is a metal or an alloy, a thermal expansion coefficient of the metal being larger than that of a main ceramic component of the dielectric layer, the ground layer including a ceramic additive; outermost layers of the multilayer chip are cover layers whose main component is a main component of the dielectric layer; and thermal expansion coefficients satisfy a relationship of, the main component of the ground layer>the main component of the cover layers>the ceramic additive.

Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the pair external electrodes, a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, being within ±20% of an average of the concentrations of the base metal in the five regions, an average grain number in the dielectric layer being three or less in the stacking direction between the first and second internal electrodes.

Abstract: A ceramic electronic component includes an interior part and an exterior part. The interior part includes an interior part dielectric layer and an internal electrode layer. The exterior part includes an exterior part dielectric layer. The exterior part is positioned outside the interior part along a laminating direction thereof. The interior part dielectric layer and the exterior part dielectric layer respectively contain barium titanate as a main component. ????0.20 and ?/??0.88 are satisfied, where ? mol part and ? mol part are respectively an amount of a rare earth element contained in the interior and exterior part dielectric layers, provided that an amount of barium titanate contained in the interior and exterior part dielectric layers is respectively 100 mol parts in terms of BaTiO3.

Abstract: A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.

Abstract: An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of ?55 degrees C.

Abstract: A multilayer ceramic capacitor provided in a multilayer printed wiring board includes a ceramic body with a plurality of ceramic layers and internal electrodes stacked, and an external electrode including a base layer that includes a sintered metal containing a metal and glass and a plated layer provided on the surface of the base layer, which is provided on an end surface of the ceramic body to be connected to the internal electrodes. The external electrode includes a principal surface portion disposed on a principal surface of the ceramic body. The outermost layer of the plated layer includes a Cu plated layer. The ratio of arithmetic mean roughness (Ra) at the surface of the ceramic body/arithmetic mean roughness (Ra) at the surface of the external electrode satisfies a condition: about 0.06?the arithmetic mean roughness (Ra) at the surface of the ceramic body/the arithmetic mean roughness (Ra) at the surface of the external electrode?about 0.97.

Abstract: A body of a multilayer ceramic capacitor includes an inner layer portion and first and second outer layer portions sandwiching the inner layer portion therebetween. The inner layer portion includes an area extending from a conductive layer positioned closest to a first main surface to a conductive layer positioned closest to a second main surface in the stacking direction. The height of the body is smaller than the width of the body. The height of the inner layer portion is smaller than the width of the inner layer portion. The first outer layer portion includes a dielectric layer positioned closest to the first main surface. The second outer layer portion includes a dielectric layer positioned closest to the second main surface, and is thicker than the first outer layer portion. The total height of the first and second outer layer portions is smaller than the height of the inner layer portion.

Abstract: A multilayer ceramic capacitor that is highly resistant to insulation degradation under high-temperature load includes an inner ceramic layer that has a composition mainly composed of a perovskite-type compound containing Ba and Ti, at least one of Nb and Ta, contains Mn and Al, and optionally contains Mg and a rare-earth element that is at least one of Y, Gd, Tb, Dy, Ho, and Er, with a content of Ti being 100 parts by mole, and (a) a total of Nb and Ta is from about 0.2 to about 1.5 part by mole, (b) Mg is not more than about 0.2 part by mole including 0 part by mole, (c) Mn is from about 1.0 to about 3.5 parts by mole, (d) Al is from about 1.0 to about 4.0 parts by mole, and (e) the rare-earth element is not more than about 0.05 part by mole including 0 part by mole. Furthermore, an average number of particles per one layer of the inner ceramic layer is not more than 3.

Abstract: Provided is a laminated ceramic capacitor which can suppress degradation of the insulation resistance due to the addition of vanadium. Second insulating layers are stacked on both sides in the stacking direction of a first insulating layer group, which has first insulating layers stacked over one another, and internal electrodes are placed on principal surfaces of the first insulating layers. At least one internal electrode is placed between the first and second insulating layers. Both contain, as their main constituent, a perovskite-type compound represented by the formula “ABO3” wherein “A” denotes at least one of Ba, Sr, and Ca, “B” denotes at least one of Ti, Zr, and Hf. V is added to only the first insulating layers.

Abstract: A multilayer ceramic electronic component including: a ceramic body having a plurality of dielectric layers stacked therein; active layers including a plurality of first and second internal electrodes formed to be alternately exposed to both end surfaces of the ceramic body with the dielectric layers interposed therebetween; and first and second external electrodes formed on the both end surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. The active layers may include a first active layer including a ferroelectric layer and a second active layer including a paraelectric layer, the first and second active layers being alternately stacked.

Abstract: A multilayer ceramic capacitor includes ceramic grains forming a dielectric layer of the multilayer ceramic capacitor, which ceramic grains contain a coarse ceramic grain SPr having a coarse grain size Dcoa that satisfies the condition of Tmin ?Dcoa ?Tmax where Tmax is the maximum thickness of the dielectric layer and Tmin is the minimum thickness of the dielectric layer. The multilayer ceramic capacitor is capable of inhibiting deterioration of capacitance and capacity-temperature characteristics even when the internal electrode layer is made thin.

Abstract: A multilayer ceramic capacitor includes a multilayer body including a plurality of stacked dielectric layers including a dielectric ceramic that includes a plurality of crystal grains and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric layers, and external electrodes. The multilayer body includes a Ba and Ti containing perovskite compound, La, Mg, Mn and Al, and satisfies conditions such that in a case in which a content of Ti is set to 100 molar parts, a fraction of each content of La, Mg, Mn and Al relative to the content of Ti is such that La is about 0.2 to about 1.2 molar parts, Mg is about 0.1 molar part or less, Mn is about 1.0 to about 3.0 molar parts and Al is about 0.5 to about 2.5 molar parts, and an average number of crystal grains included in each of the dielectric layers in the stacking direction is one or more to three or less.

Abstract: A multilayer ceramic capacitor includes a multilayer body including a plurality of stacked dielectric layers including a dielectric ceramic that includes a plurality of crystal grains and a plurality of internal electrodes disposed at a plurality of interfaces between the dielectric layers, and external electrodes. The multilayer body includes a Ba and Ti containing perovskite compound, La, Mg and Mn, and satisfies conditions such that in a case in which a content of Ti is set to 100 molar parts, a fraction of each content of La, Mg and Mn relative to the content of Ti is such that La is about 1.2 to about 6.0 molar parts, Mg is about 0.5 to about 5.0 molar parts and Mn is about 1.0 to about 3.0 molar parts, and an average number of crystal grains included in each of the dielectric layers in the stacking direction is one or more to three or less.

Abstract: Provide is a laminated ceramic capacitor which can suppress the decrease in dielectric constant even when ceramic layers are further reduced in thickness. The laminated ceramic capacitor includes a laminate having a plurality of stacked ceramic layers stacked and a plurality of internal electrodes formed along interfaces between the ceramic layers; and a plurality of external electrodes formed on the outer surface of the laminate and electrically connected to the internal electrodes ceramic grains in contact with both of adjacent internal electrodes adjacent with a ceramic layer interposed therebetween are present in the ceramic layers and the internal electrodes are 0.60 ?m or less in thickness.

Abstract: A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.

Abstract: A high breakdown voltage metal-insulator-metal capacitor for compound semiconductor integrated circuit comprises a substrate, an isolation layer, a first metal layer, a dielectric layer, an adhesion layer and a second metal layer. The dielectric layer is formed by alternately stacking plural HfO2 layers and plural SiO2 layers. The thickness of each layer of the plural HfO2 layers is between 30 ? to 100 ? so as to reduce the leakage current, enhance the breakdown voltage and increase the capacitance density of each layer of the plural HfO2 layers. And the total thickness of the dielectric layer is thicker than 500 ? such that the breakdown voltage of the capacitor is higher than 50 V.

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Abstract: A thin film capacitor includes an under electrode, a plurality of dielectric body layers and a plurality of internal electrode layers that are alternately laminated on the under electrode, the internal electrode layers respectively including protrusion parts that each protrude from the dielectric body layers viewed in the lamination direction, and connection electrodes to which at least a portion of each of the protrusion parts contacts. Assuming that protrusion amounts of the protrusion parts of the internal electrode layers that are connected to the same connection electrode are regarded as L, a protrusion amount Ln of a protrusion part of nth (n?2) internal electrode layer from the under electrode side is smaller than another protrusion amount Ln-1 of another protrusion part of (n?1)th internal electrode layer.

Abstract: A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes covering end portions of the ceramic body in length direction; an active layer in which the internal electrodes are disposed in opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in thickness direction, the lower cover layer thicker than the upper cover layer.

Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.

Abstract: An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of ?55 degrees C.

Abstract: A method of enhancing the intelligibility of sounds including the steps of: detecting primary sounds emanating from a first direction and producing a primary signal; detecting secondary sounds emanating from the left and right of the first direction and producing secondary signals; delaying the primary signal with respect to the secondary signals; and presenting combinations of the signals to the left and right sides of the auditory system of a listener.

Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.

Abstract: A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors.

Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.

Abstract: A method for manufacturing a multilayer ceramic electronic component significantly reduces and prevents swelling or distortion when a conductive paste is applied to a green ceramic element body. A ceramic green sheet used in the method satisfies 180.56?A/B wherein A is a polymerization degree of an organic binder contained in the ceramic green sheet, and B is a volume content of a plasticizer contained in the ceramic green sheet.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.

Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.

Abstract: To provide a thin-film capacitor capable of improving the stability of electric connection between an internal electrode layer and a connection electrode. The thin-film capacitor comprises: two or more dielectric layers deposited above a base electrode; an internal electrode layer being deposited between the dielectric layers and having a projecting portion which projects from the dielectric layer when seen from a laminating direction; and a connection electrode electrically connected to the internal electrode layer via at least a part of a surface and an end face of the internal electrode layer included in the projecting portion, wherein a ratio L/t between a projection amount L of the projecting portion of the internal electrode layer with respect to the dielectric layer and a thickness t of the internal electrode layer is 0.5 to 120.

Abstract: There is provided a multilayered ceramic electronic component including: a ceramic main body having a dielectric layer, the ceramic main body having a length of 1.79 mm or less and a width of 1.09 mm or less; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic main body; and a first external electrode electrically connected to the first internal electrode and a second external electrode electrically connected to the second internal electrode, wherein, when it is defined that the shortest length of at least one of the first and second external electrodes, formed in the lengthwise direction from both end portions of the ceramic main body is A, and the longest length thereof is BW, a relational expression of 0.5?A/BW<1.0 may be satisfied.