Abstract: A bushing for a high electric voltage has a casing through which a central conductor is passed so that it is electrically insulated. Conducting liners spaced a distance apart are arranged concentrically around the central conductor, a combination which functions as a dielectric and is composed of one layer of film and one layer of a nonwoven being provided between the liners. The film and the nonwoven material are each made of plastic, so their water content is very low, and therefore the drying time in manufacturing of the bushing is shortened.

Abstract: The invention relates to a thin film circuit with component. The thin film circuit comprises a network of capacitors, or a network of capacitors and resistors, or a network of capacitors, resistors and inductances, or a network of capacitors and inductances. Current supply contacts such as, for example, SMD end contacts or bump end contacts render it possible for the thin film circuit to be connected to further components of a circuit or, for example, to be combined with active components through the use of contact surfaces.

Abstract: A capacitive moisture sensor is made from an SOI, i.e., silicon-on-insulator, substrate. Two electrodes, between which moisture-sensitive material is interposed, are formed from a thick silicon layer of the SOI substrate by separating the layer with a trench vertically reaching an insulator layer of the SOI substrate. Two substantially vertical sidewalls defining the trench make up a capacitor for moisture sensing. Therefore, by using deep trench, i.e., thick silicon layer, capacitance sensitivity to moisture is readily increased without horizontally widening the electrode or using horizontal surface of the electrode, that is, without enlarging sensor size or complicating fabrication process. In addition, the electrodes are made of silicon, so that corrosion resistivity against moisture is significantly.

Abstract: A multilayer electronic device comprised of a capacitor body in which a plurality of internal electrodes are separately arranged in a plurality of blocks via ceramic layers. At least one lead is led out from each internal electrode. The terminal electrodes connected to each lead is arranged at the side faces of the capacitor body. The polarities of the voltages supplied to the nearby terminal electrodes in the same side face differ.

Abstract: An oxide dielectric film (7) is formed of barium strontium titanate to have a thickness of 300 to 600 Å, and a first platinum layer (81) is deposited thereon by, e.g., sputtering at a temperature not higher than 250° C. to have a thickness of 250 to 500 Å. Further, a second platinum layer (82) is deposited on the first platinum layer (81) by, e.g., sputtering at a temperature of 250 to 500° C. to have a thickness of 250 to 500 Å. Since the first platinum layer (81) has less grain boundary and is hard to connect to that of the second platinum layer (82), with less grain boundary diffusion caused, even if a hydrogen sintering of an aluminum interconnection layer (11) is performed, reduction species are unlikely to reach the oxide dielectric film (7) through the grain boundary. That suppresses deterioration of the oxide dielectric film (7) to avoid an increase of leak current therein.

Abstract: According to a disclosed embodiment, an interconnect metal layer is deposited. The interconnect metal layer can be, for example, aluminum, copper, or an aluminum-copper alloy. Then a first dielectric is fabricated over the interconnect metal layer. The first dielectric can be, for example, silicon nitride. A top metal layer is then formed over the first dielectric. The top metal layer can be, for example, titanium nitride. Next, the top metal layer and the first dielectric are patterned and etched to form a capacitor first electrode and a capacitor dielectric. Thereafter a layer of a second dielectric is deposited over the capacitor first electrode and the capacitor dielectric. The second dielectric can be, for example, silicon oxide. Then the second dielectric is etched back, as a result of which spacers covering common sidewalls of the capacitor first electrode and the capacitor dielectric are formed. The spacers protect the capacitor dielectric from being etched during subsequent Processing steps.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.

Abstract: Invention refers to an electric component, preferably a component buried in a Printed Circuit Board (PCB) including at least two conductive layers (13,21, 36; 15, 35) and an intermediate layer (14, 37). The intermediate layer (14, 37) further consists of at least two layers (16, 17, 22, 23, 38, 39, 40): at least a first layer (17, 23, 39) and a second layer (16, 22, 38, 40), which at least first layer has more elastic characteristic than the second layer (16, 22, 38, 40) at a certain temperature and/or pressure.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1−xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: Graphitic nanofibers, which include tubular fullerenes (commonly called “buckytubes”), nanotubes and fibrils, which are functionalized by chemical substitution, are used as electrodes in electrochemical capacitors. The graphitic nanofiber based electrode increases the performance of the electrochemical capacitors.

Abstract: A multi-layer distributed capacitor structure comprises a bottom electrode layer overlying a monolithic substrate, intermediate pairs of layers of film electrode and dielectric material overlying the bottom electrode, and a top pair of layers of a film electrode and dielectric material overlying the intermediate pairs. The structure contains multiple openings, each opening extending from the top pair of layers through the intermediate layers and optionally through said bottom electrode. Each electrode layer also extends laterally beyond and around the entire periphery of the layers positioned above such that the electrode layers bordering on each opening has edges running along the perimeter of the opening which are left exposed for electrical connection to a circuit using wire interconnects.

Abstract: A capacitor electrode includes a film base member having connection means located thereon so that the capacitor electrode may be connected to an external component, and a segmented metallized layer connected to the connection means, the metallized layer being made of metallized segments interconnected by current gates. The segmented,metallized layer has a thickness which varies or differs continuously along a length thereof, and the current gates have a width which increases as the thickness of the segmented metallized layer decreases.

Abstract: A multi-layer ceramic electronic device having a device body including alternately arranged dielectric layers and internal electrode layers and external electrodes formed on an outer surface of the device body, wherein the external electrodes have an undercoat layer directly formed on the outer surface of the device body so as to be electrically connected with at least part of the internal electrode layers, an intermediate layer formed on the outer surface of the undercoat layer, and an outer layer formed on the outer surface of the intermediate layer; the undercoat layer includes a first conductive material mainly made of copper and a first glass ingredient; the intermediate layer includes a second conductive material mainly made of a copper-palladium-based alloy; and the outer layer includes a third conductive material mainly made of silver and further containing palladium and a second glass ingredient.

Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor includes a capacitor dielectric layer including Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode includes a conductive metal oxide. A more preferred second capacitor electrode includes a conductive silicon including layer, over a conductive titanium including layer, over a conductive metal oxide layer. A preferred first capacitor electrode includes a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.

Abstract: A nonreducing dielectric contains a main-component having a perovskite crystal phase and satisfying the formula (Ca1-a-b-cSraBabMgc)m(Zr1-w-x-y-zTiwMnxNiyHfz)O3 and a compound oxide represented by the formulae (Si, T)O2—MO—XO and (Si, T)O2—(Mn, M′)O—Al2O3. The ratio of the intensity of the maximum peak of a crystal phase not of the perovskite crystal phase to the intensity of the maximum peak assigned to the perovskite crystal phase appearing at 2&thgr;=25 to 35° is about 5% or less in a CuK&agr; X-ray diffraction pattern.

Abstract: A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.

Abstract: An electronic part enabling a further efficient attenuation of high-frequency noises is provided. The first dielectric paste is applied onto a PET film (30) to form a ceramic sheet (31) having a dielectric constant ∈1 thereupon; and ceramic films (22—3, 22—4) are formed by applying the second dielectric paste on the ceramic sheet (31). Next, the pattern of the signal line (22—2) is printed by applying the conductive paste to the center of ceramic sheet (31) such that the right side (22—3a) of ceramic film (22—3) in the lengthwise direction and the left side (22—4a) of ceramic film (22—4) in the lengthwise direction are covered with the conductive paste; after that, further ceramic films (22—5, 22—6) are formed such that the lateral ends (22—2d, 22—2e) of the signal line (22—2) are sandwiched between the ceramic films (22—5, 22—6; and 22—3, 22—4).

Abstract: A ceramic substrate having two side surfaces in a lengthwise direction and two side surfaces in a widthwise direction intersecting each other. The ceramic substrate also includes at least one flat surface in a thicknesswise direction. Internal electrode films are embedded in the ceramic substrate with film surfaces thereof extending roughly parallel to the flat surface of the ceramic substrate. External electrodes are each provided on the flat surface of the ceramic substrate toward one of the two ends of the ceramic substrate in the lengthwise direction, are electrically continuous with the internal electrode films and are formed over distances and from the two side surfaces in the widthwise direction.

Abstract: The invention provides an electronic thin-film material suitable for composing a diffusion preventive layer for use in a ferroelectric capacitor, a ferroelectric capacitor using such diffusion preventive layer composed of the electronic thin-film material, and a non-volatile memory using such ferroelectric capacitor. The ferroelectric capacitor 10 is composed of a diffusion preventive layer made of a CrTa film 2, a lower electrode made of a Pt film 3, a ferroelectric film 4 made of PZT, and an upper electrode made of a Pt film 5, which are sequentially laminated on a surface of a silicon substrate. The CrTa film 2 itself is an alloy film comprising 90-atomic % of Cr and 10-atomic % of Ta, which can be formed via a sputtering process. Inasmuch as the ferroelectric capacitor 10 is composed of the CrTa film 2, it is possible to utilize PZT requiring high-temperature thermal treatment to form the ferroelectric film material.

Abstract: First and second external terminal electrodes are formed on the same principal surface of a capacitor main body. The connection between first internal electrodes in the capacitor main body, the first external terminal electrode and the mutual connection between the plurality of first internal electrodes is achieved by a first connection portion. The connection between second internal electrodes, the second external terminal electrode and the mutual connection between the plurality of second internal electrodes is achieved by a second connection portion. The first and second connection portions are arranged alternately. Currents flow through the connection portions in opposite directions with the result that components of magnetic flux generated by such currents are cancelled and the ESL is reduced.

Abstract: A ceramic capacitor typically 10 mils to 340 mils square by typically 4-20 mils thickness with areas of metallization, or pads, to which electrical connections may be made on, typically, each of two opposite exterior surfaces, has embedded at least one, and normally two or more, metallization planes at close, typically 0.5 mil, separation. Each interior metallization plane connects through multiple redundant vias, as are preferably made by (ii) punching, (ii) drilling, (iii) laser drilling, or (iv) radiation patterning of a green ceramic sheet having a photosensitive binder, to an associated surface pad or trace. The vias are both numerous and redundant, typically being of 2 mil diameter on 10 mil centers in a pin grid array pattern over and through entire ceramic layers of the capacitor, permitting both (i) easy fabrication without exacting alignment or registration between layers, and (ii) low Equivalent Series Resistance (ESR) in the finished capacitor.

Abstract: A multi-layer capacitor achieves significant reduction in equivalent series inductance (ESL) and includes first inner electrodes and second inner electrodes opposing each other, first feed-through conductors and second feed-through conductors, and first outer terminal electrodes and second outer terminal electrodes. The first feed-through conductors electrically connect the first inner electrodes and the first outer terminal electrodes, and the second feed-through conductors electrically connect the second inner electrodes and the second outer terminal electrodes. The first and second feed-through conductors are arranged such that the feed-through conductors mutually cancel magnetic fields induced by current flowing through the first and second inner electrodes. Furthermore, when an alignment pitch of the first and second feed-through conductors is indicated by P and the total number of the first and second feed-through conductors is indicated by N, an arrangement is set such that a ratio of P/N is about 0.

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed.

Abstract: An improved integrated circuit device that has an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then, a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A capacitor structure includes a bottom plate, a top plate, and a dielectric layer between the bottom and top plates. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer.

Abstract: In an electroconductive paste comprising a nickel powder for use in forming internal electrodes of a laminated ceramic capacitor, particles of nickel powder contained in the electroconductive paste have an average particle size D of about 0.5 &mgr;m or less, and the crystal particle size dc of a nickel crystal contained in each particle of the nickel powder is made to be less than about 20% of the average particle size D.

Abstract: A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

Abstract: A capacitor has a pair of plates separated by a capacitor dielectric material which is formed of multiple separate layers of different dielectric materials having different electrical characteristics. The different electrical characteristics are represented by linearity curves that curve relatively oppositely with respect to one another. Combining the different dielectric materials and separate layers achieves selected electrical characteristics from the overall capacitor dielectric material. The capacitor dielectric material may be formed with a top layer, a middle layer and a bottom layer. The middle layer may be formed of relatively high leakage dielectric and/or relatively high dielectric constant material, and the top and bottom layers may be formed of barrier material which is substantially resistant to leakage current and which exhibits a relatively lower dielectric constant.

Abstract: The electronic device (10) of the invention has a first inductor (12) and a first capacitor (11). The capacitor (11) comprises a first capacitor electrode (21) in a first electrically conducting layer (3), a dielectric (26), and a second capacitor electrode (25) in a second electrically conducting layer (7). The second conductive layer (7) also comprises the first inductor (12) and a via (13). In order to get a resonance frequency with a low tolerance, which can be used at high frequencies in RF equipment, the second capacitor electrode (25) has a contour whose projection onto the first conductive layer (3) lies within the first capacitor electrode (21). In this way the decrease in capacitance of the first capacitor (11) due to etching can be leveled out against the increase in inductance of the first inductor (12) due to the same etching. Preferably, the dielectric (26) has a middle zone (24) and edge zones (22, 23). The dielectric consists of a layer of dielectric material (5) in the middle zone (24).

Abstract: There is provided a thin film capacitor including (a) a semiconductor substrate, (b) an interlayer insulating film formed on the semiconductor substrate, (c) a contact formed throughout the interlayer insulating film such that the contact has an upper surface upwardly projecting, (d) a lower electrode formed on the interlayer insulating film such that the lower electrode at least partially covers the upper surface of the contact therewith, (e) a capacity insulating film covering the lower electrode and the interlayer insulating film therewith, and (f) an upper electrode formed on the capacity insulating film. The thin film capacitor prevents peeling between the contact and the lower electrode even in an annealing step.

Abstract: A monolithic ceramic capacitor includes a sintered ceramic compact having a core-shell structure, a plurality of internal electrodes arranged in and separated by the ceramic sintered compact so as to overlap in the thickness direction, and a plurality of external electrodes formed on the outermost faces of the ceramic sintered compact. In the core-shell structure, cores are composed of a particulate dielectric ceramic, and shells are formed on the cores and are composed of a material having a dielectric constant lower than that of the dielectric ceramic. The area ratio of the cores to the shells lies in a range of 7:3 to 3:7 in a cross-section of the sintered ceramic compact in an arbitrary direction. The core-shell structure can achieve further miniaturization and higher capacitance of the monolithic ceramic capacitor, in addition to superior temperature characteristics.

Abstract: There is provided a thin film capacitor including (a) a semiconductor substrate, (b) an interlayer insulating film formed on the semiconductor substrate, (c) a contact formed throughout the interlayer insulating film such that the contact has an upper surface upwardly projecting, (d) a lower electrode formed on the interlayer insulating film such that the lower electrode covers the upper surface of the contact therewith, (e) a capacitor insulating film covering the lower electrode and the interlayer insulating film therewith, and (f) an upper electrode formed on the capacitor insulating film. The thin film capacitor prevents peeling between the contact and the lower electrode even in an annealing step.

Abstract: A low-leakage-current layer, made of BST in which the content of Ti deviates from its stoichiometric composition, is interposed between a high-dielectric-constant layer, made of BST with the stoichiometric composition, and an upper electrode. And a charge-storable dielectric film is made up of the high-dielectric-constant layer and the low-leakagecurrent layer. Such a BST film containing a larger number of Ti atoms than that defined by stoichiometry can suppress the leakage current to a larger degree. Also, if such a film is used, then the relative dielectric constant does not decrease so much as a BST film with the stoichiometric composition. Accordingly, the leakage current can be suppressed while minimizing the decrease in relative dielectric constant of the entire charge-storable dielectric film, which is a serial connection of capacitors, thus contributing to the downsizing of a semiconductor memory device.

Abstract: The invention pertains to semiconductor circuit components and capacitors. In another aspect, the invention includes a capacitor including: a) a first capacitor plate; b) a first tantalum-comprising layer over the first capacitor plate; c) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen; and d) a second capacitor plate over the second tantalum-comprising layer. In another aspect, the invention includes a component having: a) a first tantalum-comprising layer; and b) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: A monolithic ceramic component has inner electrodes which are thin having a thickness of from about 0.2 &mgr;m to 0.7 min, and thereby, delamination is inhibited even though ceramic layers are thin, having a thickness up to about 3 &mgr;m. The mean particle size of the ceramic grains of the ceramic layers is up to 0.5 &mgr;m, so that the concavities and convexities at the interfaces between the inner electrodes and the ceramic layers can be reduced. Preferably, metal powder in a paste used to form the inner electrodes has a mean particle size of from about 10 to 200 nm, and thereby, the metal filling ratio and the smoothness of the inner electrodes can be enhanced, and the coverage can be improved.

Abstract: There is provided a capacitor employed in a MMIC and having a structure which is capable of increasing a capacitance of occupied areas of capacitor patterns and also reducing variation of a capacitance value in mass production. A substantial comb-type lower electrode 11 is formed on a substrate 14, then a dielectric layer 13 is formed on the lower electrode 11, and then a substantial comb-type upper electrode 12 is formed on the dielectric layer 13. Respective element electrodes 16 (15) of one of the lower electrode 11 and the upper electrode 12 are arranged in blank areas between respective element electrodes 15 (16) of the other of the lower electrode 11 and the upper electrode 12.

Abstract: The present invention is a dielectric film, and method for making the film, suitable for use in the construction of capacitor devices, including wound capacitors. In order to overcome strength limitations associated with polymers having desirable dielectric properties, the invention includes a dielectric film featuring a polymer impregnated upon a strengthening substrate. The polymer is deposited directly upon the substrate, which substrate provides required physical strength for film processing and capacitor fabrication, without compromising dielectric performance. The inventive film is based on siloxane polymers modified with polar pendant groups to provide a significant increase in dielectric constant and dielectric strength. During film production, the polymer infiltrates the porous paper to provide an interfacial composite layer between the two materials, the interfacial layer consisting of polymer and paper.

Abstract: A contact sleeve passing through a central region of a capacitor provides a low-inductance connection between a lower contact surface of a capacitor and a first outer port. The sleeve is separated from the windings of the capacitor by an insulative layer. A second outer port is formed in close proximity to and insulated from the first outer port so that arcing between the outer ports is prevented. The resulting capacitor has a low inductance and is useful in, for example, the intermediate circuit design of converters, resulting in a compact and reliable configuration.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: A dielectric ceramic composition containing a primary component represented by the following formula: {BaO}mTiO2+&agr;M2O3+&bgr;R2O3+&ggr;BaZrO3+gMgO+hMnO wherein M2O3 is at least one of Sc2O3 or Y2O3; R2O3 is at least one member selected from the group consisting of Eu2O3, Gd2O3, Tb2O3. Dy2O3, Ho2O3, Er2O3, Tm2O3 and Yb2O3; &agr;, &bgr;, &ggr;, g or h represent a mole ratio and satisfy specified relations; and silicon oxide as an auxiliary component in an amount of 0.2-5.0 mol as SiO2, with respect to 100 mol of the primary component.

Abstract: A multilayer ceramic device suitable for use in surface mount decoupling applications may have a single capacitor or a capacitor array. The device has a capacitor body defining a plurality of electrical terminals on an outer surface thereof. The terminals are interdigitated such that a respective first polarity terminal will be adjacent to a respective second polarity terminal (and vice versa). The capacitor body contains a plurality of interleaved capacitor plates in opposed and spaced apart relation. Capacitor plates of the first polarity are electrically connected to respective first polarity terminals via a plurality of lead structures. Likewise, a plurality of lead structures electrically connect capacitor plates of the second polarity to respective second polarity terminals.

Abstract: Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.

Abstract: A thin-film capacitor comprises an electrically insulating substrate which is provided with at least two inner electrodes which are separated from each other by means of the dielectric layer. The capacitor also includes two end contacts which each electroconductively contact one of the inner electrodes. The electroconductive contact takes place via a through-connection which communicates exclusively with the main surface of the inner electrode. By virtue of this measure, it is achieved that the contact resistance between the end contacts and the inner electrodes is relatively low and reproducible. As a result, also the value of the ESR of the thin-film capacitor is low, so that the capacitor can very suitably be used for high-frequency applications.

Abstract: An electric double layer capacitor comprises a first electrode 31 comprising a belt-like electricity collecting material 31a having both surfaces on which electrode layers 31b, 31c are formed leaving belt-like portions in a side of the belt-like electricity collecting material 31a along its longitudinal direction, a second electrode 32 having the same structure as the first electrode 31, belt-like separators 33a, 33b to electrically insulate the first and second electrodes 31, 32, a post-like winding core 40 on which the first and second electrodes 31, 32 and the separators 33a, 33b are wound to thereby form a cylindrically wound element 50, a first electricity collecting plate 72 in contact with the belt-like portion 31ax, a second electricity collecting plate 62 in contact with the belt-like portion 31ax, wherein the belt-like portions 31ax, 32ax are located at opposing positions in the wound element 50, both ends of the winding core 40 are respectively in contact with the first and second electricity colle

Abstract: This invention provides a capacitor including a metal lower electrode having an undulated shape and an improved electrode area, and a method of manufacturing the same. A capacitor for data storage is formed on a semiconductor substrate (not shown) via an insulating interlayer having a contact plug. The capacitor has a lower electrode whose inner and outer surfaces are rough or undulated such that one surface has a shape conforming to the shape of the other surface, a dielectric film formed to cover the surfaces of the lower electrode, and an upper electrode formed to cover the lower electrode via the dielectric film. The lower electrode has a cylindrical shape with an open upper end. The lower electrode is connected to a cell transistor through the contact plug. The lower electrode is formed from a metal or a metal oxide.

Abstract: A preferred embodiment of this invention includes an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: A multi-capacitor device having a plurality of capacitors in a single circuit package is formed of a plurality of layers of dielectric material, preferably the same type of material that is commonly used to fabricate circuit boards. The plurality of layers are disposed in a vertically stacked relationship. Each capacitor is formed of first and second pluralities of planar electrodes formed on alternating layers of the stack. The first plurality of electrodes is disposed in a first vertically stacked array, and the second plurality of electrodes is disposed in a second vertically stacked array. Each vertical electrode array is provided with a via hole extending through all of its layers to connect all of the respective electrode array in parallel. At the upper surface of the assembly, each via hole is connected to a solder pad and disposed to be soldered to a connection point on a printed circuit board or the like.

Abstract: According to a flexible thin film capacitor of the present invention, an adhesive film is formed on a substrate composed of at least one selected from the group consisting of an organic polymer and a metal foil, and an inorganic high dielectric film and metal electrode films are formed thereon. A metal oxide adhesive film can be used as the adhesive film. The adhesive film is formed in contact with the inorganic high dielectric film and at least one of the metal electrode films.