Abstract: A ferroelectric capacitor including a silicon oxidation layer, a lower electrode, a ferroelectric layer and an upper electrode formed on a silicon substrate. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx and ReOx.

Abstract: According to the present invention, a method of manufacturing a ferroelectric capacitor using a ferroelectric thin film, includes steps of: forming a lower conductive layer on a semiconductor substrate; coating solution of ferroelectric coking including organic solvent and organometallic complex on the lower conductive layer; performing a heating process for coated solution at temperature, to decompose said organometallic complex in solution of ferroelectric coking, or more and ferroelectric crystallization temperature or below to form said metal compound thin film; forming an upper conductive layer on said metal compound thin film; and performing a heating process for said metal compound thin film at ferroelectric crystallization temperature or more to form said ferroelectric thin film.

Abstract: A dielectric ceramic includes, in composition, a perovskite-type compound having the general formula ABO3 containing Ba, Ca and Ti, and an additive component containing Si, R(La or the like), and M (Mn or the like), the additive component not being solid-dissolved and, moreover, the major component existing in at least 90% of the cross-section of each of the crystal grains of which the number is equal to at least 85% of that of all of the crystal grains contained in the dielectric ceramic, at least the Ba, the Ca, the Ti, the Si, the R, and the M being contained at at least 85% of the analytical points in the crystal grain boundaries of the dielectric ceramic.

Abstract: The present invention relates to an IC package substrate provided with over voltage protection function and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install multiple protection devices on a printed circuit board. Therefore, the costs to design circuits are reduced, the limited space is effectively utilized, and unit costs to install respective protection devices are lowered down.

Abstract: A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.

Abstract: There is disclosed herein a high voltage and high temperature power electronics capacitor which comprises one or more insulator layers of mica paper, and one or more metal conductor layers, all dispersed in a pressurized environment of a nonreactive and high voltage strength gas maintained at near ambient to about 405.2 kPa of pressure. The insulator and conductor layers are isolated and separated from one another by the alternating placement of conductor layers between said insulator layers. These capacitors are readily packaged for commercial use in containers or housings of almost any geometric form and any material of construction. Moreover, low inductance ceramic bushings can be employed on these containers for establishing external electrical contacts. These capacitors can be economically manufactured and used in large commercial volumes with currently available materials and production methods.

Abstract: A high-voltage stacked capacitor includes a first capacitor and a second capacitor. Each capacitor includes a first plate comprising a first semiconductive body and a second plate comprising a floating electrode. The first and second semiconductor bodies are electrically isolated from each other. The floating electrode includes an intercapacitor node configured to self-adjust to a value less than a working voltage impressed on the stacked capacitor.

Abstract: The mean grain size (D2) of the main crystal phase 11 in the external cover dielectric layers 3 is made larger than the mean grain size (D1) of the main crystal phase 11 in the dielectric ceramic layers 7, and the amount of the secondary phase (M2) in the external cover dielectric layer 3 is made more than the amount of the secondary phase (M1) in the dielectric ceramic layer 7, or the volume proportion of the secondary phase 16 to the main crystal phase 11 in the external cover dielectric layer 3 is made lower than the volume proportion of the secondary phase 16 to the main crystal phase 11 in the dielectric ceramic layer 7.

Abstract: Provided are thin-laminate panels (i.e., thin-laminate panels having dielectric layers of about 0.006 inches or less and conductive layers on either side of the dielectric layer), wherein the edges of the dielectric layers of the panels are free of conductive material, such as copper. The thin-laminate panel is designed to provide necessary capacitance for all or a substantial number of the integrated circuits to be formed thereon. Finishing methods for treating unfinished thin-laminate panels into finished thin-laminate panels assure that the edges of the dielectric layer of the panel are substantially free of conductive material.

Abstract: The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

Abstract: A method for fabrication of ceramic tantalum nitride and improved structures based thereon is disclosed. According to the disclosed method, an ionized metal plasma (“IMP”) tool is used to create a plasma containing tantalum ions where the plasma is sustained by a mixture of nitrogen and argon gases. The percentage of nitrogen partial flow in the mixture of gases is adjusted so as to result in a layer of tantalum nitride with a nitrogen content of at least 30%. With a nitrogen content of at least 30%, the tantalum nitride becomes ceramic. The ceramic tantalum nitride presents a number of advantages. For example, the fabrication of ceramic tantalum nitride can be easily incorporated into fabrication of semiconductor chips using copper as the interconnect metal. Also, ceramic tantalum nitride can be used as an effective etch stop layer.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A fully surface mountable vertical multi-layer capacitor having low insertion loss at high frequency and low inductance, and providing sufficiently high capacitance for use in broadband and other applications. The capacitor includes a first section and a second section, each directly mountable to a surface trace on a printed circuit board, and each providing an electron flow path to a respective set of internal electrode plates. By the present invention, the need for wire bonding of vertical multi-layer capacitors is eliminated.

Abstract: A highly reliable monolithic ceramic capacitor which has no structural defect, e.g. peeling, and which is not susceptible to water from the outside and a method for manufacturing the same are provided. A lead portion of an internal electrode is configured to have a shape provided with a taper-shaped portion in which the width gradually decreases with increasing proximity to the end surface of a ceramic element, and the shape of the end portion opposite to the lead portion of the internal electrode is adjusted to be substantially rectangular. Regarding a pair of internal electrodes facing each other with the ceramic layer therebetween, the internal electrodes are laminated while the positions thereof are displaced with respect to each other in order that a corner portion in the substantially rectangular portion of one internal electrode are located in the vicinity of, but outside the taper-shaped portion of the other internal electrode.

Abstract: Resin thin films (12) and metal thin films (11a, 11b) are layered in alternation. The metal thin films are set back from the peripheral edges of the resin thin films (12). Via holes (13a, 13b) penetrating the layered product in the layering direction are formed and filled with conductive material (14a, 14b). The conductive material (14a, 14b) electrically connects the metal thin films (11a, 11b) among one another. The metal thin films are not exposed at the periphery, so that corrosion of the metal thin films is not likely to occur. Furthermore, cutting of the metal thin films during the manufacturing process is avoided.

Abstract: Dielectric structures particularly suitable for use in capacitors and having a textured surface are provided, together with methods of forming these structures. Such dielectric structures show increased adhesion of subsequently applied conductive layers.

Abstract: A single layer capacitive device and a method of making the same are provided. Such method allows for perfect registration between the capacitive plates thus eliminating any significant amount of fringe capacitance and assuring a uniform fringe border around the device. Such a border ensures ease of handling and such method allows for a controlled border in a range of from about 0.5 mils to about 2.0 mils wide. Further, such a method allows for the manufacture of single layer capacitive arrays comprising numerous individual capacitive devices with similar perfect registration and uniform fringe borders. Such devices allow for improved volumetric efficiencies and reduced fringe capacitance, thus offering higher capacitor values in a smaller package size due to greater control during finishing processes.

Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A multiple-layer diffusion junction capacitor structure includes multiple layers of inter-digitated P-type dopant and N-type dopant formed in a semiconductor substrate. An opening in a hard mask is formed taking care to control the angle of the sidewall using a dry, anisotropic etching process. P-type and N-type dopant are then implanted at positive and negative shallow angles, respectively, each with a different energy and dose. By utilizing the properly determined implant angles, implant energies and implant doses for each of the dopant types, a high capacitance and high density diode junction capacitor, with inter-digitated N-type and P-type regions in the vertical direction is provided.

Abstract: A laminated capacitor has an end surface pitch Pe, which defines an interval between adjacent first and second external terminal electrodes disposed on end surfaces having shorter sides in a body of a laminated capacitor, which is equal to or less than about 0.9 times of a side-surface pitch Ps, which defines an interval between adjacent first and second external terminal electrodes disposed on side surfaces having longer sides, in order to enhance the effect of magnetic-flux cancellation at the end surfaces and to reduce the equivalent series inductance of the whole laminated capacitor.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: An electrode of an electronic device includes plural nickel layers adjacent to each other, and an outer nickel layer contains less phosphorus than an inner nickel layer. The electrode has an increased solder joining strength without having a flexural strength decreased.

Abstract: A capacitor which includes a lower electrode 12 formed on a substrate 10; an insulation film 16 having an opening 24 on the lower electrode 12; a capacitor dielectric film 30 formed on the lower electrode 12 in the opening 24 and having a larger thickness at a peripheral part of the opening 24 than at a central part of the opening; and an upper electrode 32 formed on the capacitor dielectric film 30. Thus, degradation of the breakdown voltage and stress resistance of the peripheral part of the opening 24, which is due to the coverage of the capacitor dielectric film, can be suppressed.

Abstract: An electronic component includes: a dielectric element formed by layering dielectric layers; two types of internal conductors, which have a plurality of extended portions, respectively, that are extended toward a plurality of side surfaces of the dielectric element, respectively; two types of terminal electrodes, of which one of the two types of terminal electrodes is connected to a plurality of extended portions of one of the two types of internal conductors, and the other of the two types of terminal electrodes is connected to the remaining plurality of extended portions; and a pair of metallic terminals, of which one of the metallic terminals is connected to one of the two types of terminal electrodes, and the other of the metallic terminals is connected to the remaining terminal electrodes. Accordingly, ESR can be reduced while allowing for sufficient absorption of stress.

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode having a barrier layer interposed between a conductive plug and an oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. The barrier layer is then formed in the recess. The process is continued with a formation of a second insulative layer, a potion of which is removed to form an opening exposing a portion of the barrier layer. An oxidation resistant conductive layer is deposited in the recess and forms at least a portion the storage node electrode of the capacitor.

Abstract: Multi-layer and cascade capacitors for use in high frequency applications and other environments are disclosed. The subject capacitor may have multiple capacitor components or aspects thereof in an integrated package. Such components may include, for example, thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, surface mount tantalum products, multilayer capacitors, single layer capacitors, and others. Exemplary embodiments of the present subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESR and decoupling performance over a broad band of operational frequencies.

Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.

Abstract: A mounting structure for a two-terminal capacitor or a three-terminal capacitor includes a hot conductor pattern, to which first external terminals of two-terminal capacitors are electrically connected, and grounding conductor patterns, to which second external terminals are electrically connected, which are provided on the surface of a circuit board. The two-terminal capacitors are mounted so that the capacitors may be positioned to be symmetrical with respect to the hot conductor pattern. A grounding conductor pattern is also provided inside the circuit board and electrically connected to the grounding conductor patterns by the through-holes provided in the circuit board. A common through-hole is disposed in the grounding conductor pattern G so as to be substantially the same distance from the through-holes.

Abstract: A capacitor including at least one interior metallization plane or plate and a multiplicity of vias for forming multiple redundant electrical connections within the capacitor. Series capacitors are provided having at least two interior plates redundantly electrically connected to at least two respective exterior plates. R-C devices are provided having multiple redundant vias filled with resistor material and/or conductor material to provide a resistor either in series with or parallel to a capacitor. Capacitors and R-C devices are provided having end terminations for applying voltage differential. Further, a method for making single capacitors, multiple parallel array capacitors, series capacitors and R-C devices is provided in which the chips are formed from the bottom up.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: The present invention provides a conductive pattern that has low electric resistivity, is superior in adhesion to a substrate and does not cause substrate cracking during plating, a multilayered substrate incorporating such a conductive pattern, and a fabricating method for a multilayered substrate. At first, a conductive composition including a metal powder containing not less than 95 mass % of Ag, a sintering restrainer containing Cr and/or Cr compound, a dielectric loss conditioner containing Mn and/or Mn compound, and a vehicle is prepared. Next, electrodes made of the conductive composition are formed on a plurality of green sheets. The plurality of green sheets formed with the electrodes are then laminated to form a laminated product, whereafter the laminated product is sintered.

Abstract: A decoupling capacitor suitable for use with 0.11 micron or less, for example 0.09 micron, CMOS technology is provided herein. The decoupling capacitor includes a decoupling structure that minimizes leakage current associated with the decoupling capacitor.

Abstract: A capacitor includes first and second electrodes and a quasi 1D dielectric material disposed between the electrodes. The dielectric material has a charge or spin density wave state.

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film containing an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film containing an electrically conductive polymer located on the pentoxide layer.

Abstract: An electrostatic chuck which allows sufficiently rapid temperature rising/dropping thereof, in case that the diameter of a ceramic substrate is 190 mm or more or especially in case that the diameter of the ceramic substrate is quite large, exceeding 300 mm. The electrostatic chuck includes a ceramic substrate equipped with a temperature controlling means, an electrostatic electrode formed on the ceramic substrate, and a ceramic dielectric film provided on the electrostatic electrode. The ceramic substrate has a diameter exceeding 190 mm and a thickness of 20 mm or less, and the ceramic dielectric film contains oxygen in an amount of 0.1 to 20 weight %.

Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.

Abstract: A titanium oxide powder holding a barium compound on the surface of the particles thereof is used for manufacturing a highly crystalline fine barium titanate powder by solid-phase reaction. When the titanium oxide powder and a barium-containing powder material are mixed and calcined to prepare the barium titanate powder, the barium compound on the surfaces of the titanium oxide powder particles inhibits the sintering, or the growth, of the titanium oxide during the calcination. Consequently, the resulting barium titanate powder is highly crystalline and fine.

Abstract: A capacitor element for a power capacitor having a two foils (3, 5) of metal forming a pair of electrodes, and also films (2a, 2b, 4a, 4b) of dielectric material forming the dielectric medium of the capacitor element. The capacitor element is produced by the foils and films being arranged one on top of the other and wound to a roll, so that the capacitor element displays a first end surface where one of the foils (5) has a long edge (10) indented between two of the films (2a, 4b), and also a second end surface where the other foil (3) has a long edge (9) indented between two of the films (2b, 4a), each of which indented long edges has an edge portion (15; 16) surrounded by an elongate field equalizer (18; 19) of dielectric material surrounding the edge portion.

Abstract: A multilayer ceramic capacitor includes sintered laminated bodies having a plurality of dielectric layers alternately stacked with a multiplicity of internal electrodes, and a pair of external electrodes electrically coupled to the internal electrodes. The dielectric layer is of sintered ceramic grains. The ceramic grains include a core portion surrounded by a shell portion or a solid solution. The ceramic grains contain additive elements such as acceptor elements and/or rare earth elements. The additive elements are non-uniformly distributed in the core and/or shell portion of the ceramic grain or in the solid solution. Such non-uniform distribution of the additive elements in ceramic grains promotes or facilitates the re-oxidation process of the ceramic grains and also increases electrical resistance thereof. Accordingly, the operating life characteristics of the multilayer ceramic capacitors, especially those incorporating therein thin dielectric layers, can be improved.

Abstract: The invention describes an electronic component, in particular a multiplayer component, with a dielectric and at least one electrode. The dielectric is a composite made of a dielectric ceramic material and an organic polymer. To manufacture the electronic component, the dielectric ceramic material is mixed with a suitable monomer, the mass id formed, and the monomer is polymerized. Ceramic bodies of stable shape are obtained which can be processed further into capacitors, antennas, or other passive components in that electrodes are provided. Sintering of the electronic components is no longer necessary.

Abstract: Reduced degradation to capacitor properties is disclosed. A hydrogen storage layer is provided over at least a portion a top capacitor electrode. The hydrogen storage layer absorbs and stores hydrogen, preventing hydrogen from diffusing to the capacitor. The hydrogen storage layer comprises, for example, lanthium nitride, titanium zirconium nitride, amorphous sm—co, nanostructured carbon, or a combination thereof.

Abstract: A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure.

Abstract: A multi-layer capacitor includes a plurality of dielectric layers, a pair of external electrodes and a multiplicity of internal electrode layers, each internal electrode layer being interposed between every two neighboring dielectric layers. Said two neighboring internal electrode layers and the dielectric layer disposed therebetween form a unit capacitor so that the multiplicity of internal electrode layers and the dielectric layers therebetween constitute a stack of three or more vertically stacked unit capacitors. The electrostatic capacitance of the unit capacitor located at a center of the stack is greater than those of the unit capacitors located at an is upper end and a lower end of the stack.

Abstract: A first signal path is connected to a first plane via a plated hole. A first metal flood is connected to the plated hole to form a first plate. A second signal path is on a second plane. A second metal flood connected to the second signal path to form a second plate above the first plate.

Abstract: A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-containing substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-containing gas to desposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen-containing gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-containing substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.

Abstract: An IPD has a varistor of electrodes and a ZnO dielectric. A capacitor includes electrodes and a dielectric that has oxides of bismuth, magnesium, and niobium having a pyrochlore structure of type A2B2O7. The materials are applied as wet layers and are sintered for integrated production.

Abstract: A ferroelectric capacitor including a silicon oxidation layer, a lower electrode, a ferroelectric layer and an upper electrode formed on a silicon substrate. The lower electrode having columnar crystals is made of palladium oxide. Also, the upper electrode is made of palladium oxide, thereby preventing leakage of oxygen contained in the ferroelectric layer.

Abstract: A high power resistor device and method for making a high power resistor device. A resistor is formed on a first end of a fired, ceramic chip with multiple internal conductor electrodes, and end terminations are then applied to both ends of the chip. A power resistor device having a high power rating is thus provided having buried conductor electrodes electrically connected to end terminations, where the connection at the first end is through the resistor to form a power resistor structured to dissipate heat efficiently. In an alternative method of the present invention, both ends of the chip may be dipped in resistor paste to form resistors on both ends of the chip. In yet another alternative method of the present invention, a conductor under-layer is formed under the resistor, such as by first dipping the end of the chip in a conductor paste and firing the chip.

Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.