Ceramic And Glass Patents (Class 361/320)
  • Patent number: 10304836
    Abstract: Printed electronic devices are provided.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 28, 2019
    Assignee: XEROX CORPORATION
    Inventors: Kyle B. Tallman, Jonathan H. Herko, Michael S. Roetker, Amy Catherine Porter, Lin Ma, David M. Skinner, Eric Robert Dudek, Scott J. Griffin
  • Patent number: 10306765
    Abstract: There is provided a multilayer ceramic electronic component embedded in a board including: a ceramic body including dielectric layers; first and second internal electrodes; and first and second external electrodes formed on first and second side surfaces of the ceramic body, respectively, wherein the first external electrode includes a first electrode layer and a first metal layer formed on the first electrode layer, the second external electrode includes a second electrode layer and a second metal layer formed on the second electrode layer, the first and second external electrodes are formed to be extended to first main surface of the ceramic body, and when a maximum width and a minimum width of at least one of the first and second external electrodes formed on the first main surface are defined as BWmax and BWmin, respectively, 0?BWmax?BWmin?100 ?m is satisfied.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Lee, Jin Man Jung
  • Patent number: 10269494
    Abstract: A multilayer ceramic capacitor includes a laminated body including ceramic layers and internal electrodes, and a pair of external electrodes on both end surfaces of the laminated body to be electrically connected to the internal electrodes, and each external electrode includes a base electrode layer containing Cu and provided on the surface of the laminated body, a metallic interlayer containing a Cu3Sn alloy and provided on the surface of the base electrode layer, and a conductive resin layer provided on the surface of the metallic interlayer.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shinji Otani
  • Patent number: 10249625
    Abstract: A coated, printed electronic device may comprise a plurality of contact pads arranged in a pattern, a plurality of electrode traces arranged in another pattern, the plurality of electrode traces comprising a set of bottom electrode traces and a set of top electrode traces, each electrode trace in electrical communication with an associated contact pad of the plurality of contact pads, a plurality of memory cells, each memory cell located at an intersection of a pair of electrode traces of the plurality of electrode traces and comprising a bottom electrode layer formed from a region of one of the bottom electrode traces, a top electrode layer formed from a region of one of the top electrode traces, and a ferroelectric layer between the bottom and top electrode layers, and a protective layer covering the plurality of electrode traces and extending laterally beyond each edge of each electrode trace to provide a buffer zone surrounding each electrode trace, the buffer zone extending from an end of each electrode
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 2, 2019
    Assignee: XEROX CORPORATION
    Inventors: Jonathan H. Herko, Michael S. Roetker, Kyle B. Tallman, Eric Robert Dudek, Amy Catherine Porter, David M. Skinner, Lin Ma, Markus R. Silvestri
  • Patent number: 10236854
    Abstract: A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the cer
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: March 19, 2019
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 10062516
    Abstract: A thin-film ceramic capacitor includes: a body in which a plurality of dielectric layers and first and second electrode layers are alternately disposed on a substrate; and first and second electrode pads disposed on an external surface of the body. The dielectric layer contains a mixed phase of a perovskite phase having ferroelectric properties and a pyrochlore phase having paraelectric properties, the pyrochlore phase being disposed on interfaces between the dielectric layers and the first and second electrode layers in lower portions of the dielectric layers.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 28, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Sung Kang, Hai Joon Lee, Tae Joon Park, Dong Joon Oh, Yun Hee Kim, Kyo Yeol Lee, Seung Mo Lim, In Young Kang
  • Patent number: 10014843
    Abstract: A composite electronic structure comprising at least one feature layer and at least one adjacent via layer, said layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or parallel to at least one inductor to provide at least one filter; the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: July 3, 2018
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 9754720
    Abstract: A multilayer ceramic capacitor that has alternately stacked dielectric layers containing, as their main constituent, a barium titanate based compound that has a perovskite-type crystal structure; and internal electrode layers with electrode defects. The internal electrode layers are 0.6 ?m or less in thickness. The electrode defects have electrode defects containing an Al—Si based oxide mainly containing Al and Si. The number of the electrode defects containing the Al—Si based oxide is 30% or more in number ratio to the total number of electrode defects in the internal electrodes.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: September 5, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takayuki Yao
  • Patent number: 9745481
    Abstract: The present invention is a dielectric ink and means for printing using said ink. Approximately 10-20% of the ink is a custom organic vehicle made of a polar solvent and a binder. Approximately 30-70% of the ink is a dielectric powder having an average particle diameter of approximately 10-750 nm. Approximately 5-15% of the ink is a dielectric constant glass. Approximately 10-35% of the ink is an additional amount of solvent. The ink is deposited on a printing substrate to form at least one printed product, which is then dried and cured to remove the solvent and binder, respectively. The printed product then undergoes sintering in an inert gas atmosphere.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 29, 2017
    Assignee: The United States of America as Represented by the Administrator of NASA
    Inventors: Terry D. Rolin, Curtis W. Hill
  • Patent number: 9648740
    Abstract: A ceramic substrate comprises a plurality of ceramic sheets, a plurality of inner conductive layers, a plurality of vias, and an upper conductive layer. The ceramic sheets are stacked one on top of another and include a top ceramic sheet. The inner conductive layers include electrically conductive material that forms electrically conductive features on an upper surface of each ceramic sheet excluding the top ceramic sheet. The vias are formed in each of the ceramic sheets with each via being filled with electrically conductive material. The upper conductive layer includes electrically conductive material that forms electrically conductive features on an upper surface of the top ceramic sheet. The upper conductive layer is constructed from a stack of four sublayers. A first sublayer is formed from titanium. A second sublayer is formed from copper. A third sublayer is formed from platinum. A fourth sublayer is formed from gold.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 9, 2017
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Joseph Ambrose Wolf, Kenneth A. Peterson
  • Patent number: 9615460
    Abstract: A circuit board device for reducing acoustic noise is provided. The circuit board device includes a substrate, a first capacitor packaging area, a second capacitor packaging area, a first pad, a second pad, a third pad and a fourth pad. The first and second capacitor packaging areas are respectively disposed on a first side and a second side of the substrate in a back-to-back manner. The first and second pads are disposed in the first capacitor packaging area for mounting a first capacitor. The third and fourth pads are disposed in the second capacitor packaging area for mounting a second capacitor, wherein the first and third pads are set back-to-back and electrically connected to each other, and the second and fourth pads are set back-to-back and electrically connected to each other.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: April 4, 2017
    Assignee: Wistron NeWeb Corp.
    Inventor: Chia-Hsin Wu
  • Patent number: 9390857
    Abstract: A capacitor comprises a substrate layer, a first electrode layer disposed on the substrate layer, and a first dielectric layer disposed on the electrode layer. The dielectric layer comprises inorganic ferroelectric or antiferroelectric particles, and a polymeric material having an elongation less than or equal to about 5 percent.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: July 12, 2016
    Assignee: General Electric Company
    Inventors: Daniel Qi Tan, Patricia Chapman Irwin, Yang Cao, Qin Chen
  • Patent number: 9236185
    Abstract: A multilayer ceramic capacitor includes a ceramic laminated body including dielectric ceramic layers and internal electrodes stacked with the dielectric ceramic layers disposed therebetween. The dielectric ceramic layers contain a perovskite compound containing Ba and Ti, Zr, and a rare earth element, and ratios of Zr and the rare earth element to 100 molar parts of Ti are about 0.4 to 2.0 molar parts and about 0.05 to 0.5 molar parts, respectively. The molar ratio of Zr to the rare earth element is about 3.3 to about 8.0, and Al-containing segregated substances are present in about 80% or more of defective portions where continuity of the internal electrodes is interrupted. Dielectric ceramic constituting the dielectric ceramic layers has an average grain diameter of about 230 nm to about 350 nm.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: January 12, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Toshimi Oguni
  • Patent number: 8929560
    Abstract: A method and apparatus for introducing a time-varying time delay randomly into the individual reproduction channels of a sound recording, two in the case of binaural presentation. This emulates the temporal aspect of microphone and/or listener motion. The present invention may be applied as a unidirectional process. No preparation of the source material is required. It can be applied to any multichannel audio signal set. It can process analog or digital signals. The process may be used with headphones, loudspeakers, hearing aids or similar assistive hearing devices.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 6, 2015
    Inventors: J. Craig Oxford, D. Michael Shields
  • Patent number: 8730648
    Abstract: An electrical component includes a ceramic base body. The ceramic base body includes several ceramic layers including a function layer and a composite layer bordering the function layer. The composite layer can include a zirconium oxide-glass filler mixture.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: May 20, 2014
    Assignee: Epcos AG
    Inventors: Uwe Wozniak, Thomas Feichtinger, Hermann Gruenbichler, Pavol Dudesek, Thomas Puerstinger
  • Patent number: 8599539
    Abstract: Provided is a ceramic chip assembly configured to economically and reliably insulate an exposed portion of a metal lead wire from an environmental change. The ceramic chip assembly includes a ceramic base having electrical characteristics, a pair of external electrodes that are disposed on a pair of surfaces of the ceramic base, respectively, the surfaces of the ceramic base being opposed to each other, a pair of metal lead wires as single cores having first ends that are electrically and mechanically connected to the external electrodes, respectively, by an electrical conductive adhesive member, an insulation sealant sealing the ceramic base, the external electrodes, and the first ends of the metal lead wires to expose second ends of the metal lead wires, and an insulation polymer coating layer continuously formed on both the insulation sealant and portions of the metal lead wires exposed out of the insulation sealant.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: December 3, 2013
    Assignees: Joinset Co., Ltd.
    Inventors: Sun-Ki Kim, Seong-Jin Lee, Ki-Han Park
  • Patent number: 8542475
    Abstract: A self healing high energy glass capacitor is provided. The capacitor can have a glass layer with a top surface and a bottom surface. A top sacrificial layer can extend across the top surface and a bottom sacrificial layer can extend across the bottom surface. In addition, a top electrode can extend across the top sacrificial layer and a bottom electrode can extend across the bottom sacrificial layer. In some instances the glass capacitor has an energy breakdown of at least 6 joules per cubic centimeter.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: September 24, 2013
    Assignee: The Penn State Research Foundation
    Inventors: Michael Lanagan, Carlo Pantano, Hoi Kwan Lee, Ramakrishnan Rajagopalan, Nicholas Smith
  • Patent number: 8390984
    Abstract: The disclosed is a capacitor substrate structure to reduce the high leakage current and low insulation resistance issue of organic/inorganic hybrid materials with ultra-high dielectric constant. The insulation layer, disposed between two conductive layers, includes multi-layered dielectric layers. At least one of the dielectric layers has high dielectric constant, including high dielectric constant ceramic powder and conductive powder evenly dispersed in organic resin. The other dielectric layers can be organic resin, or further include high dielectric constant ceramic powder dispersed in the organic resin. The substrate has an insulation resistance of about 50K? and leakage current of below 100 ?Amp under operational voltage.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: March 5, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Shur-Fen Liu, Meng-Huei Chen, Bih-Yih Chen, Yun-Tien Chen
  • Patent number: 8315036
    Abstract: A ceramic electronic component includes a ceramic body and a plurality of external electrodes disposed at a surface of the ceramic body. The external electrodes include a plating layer containing glass particles each coated with a metal film. The plating layer is formed by co-deposition of a plating metal and the metal-coated glass particles.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: November 20, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Ogawa, Akihiro Motoki, Junichi Saito, Shunsuke Takeuchi, Kenichi Kawasaki
  • Patent number: 8270144
    Abstract: The present invention relates to borosilicate glass compositions for a sintering agent, dielectric compositions containing the borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions. Borosilicate glass compositions for a sintering agent according to an aspect of the invention include an alkali oxide, an alkaline earth oxide and a rare earth oxide, can sinter ceramic dielectrics at low temperatures and improve the hot insulation resistance of a multilayer ceramic capacitor. Correspondingly, dielectric compositions including these borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions can be sintered at a low temperature of 1100° C. or less and have high hot insulation resistance, thereby ensuring high levels of reliability.
    Type: Grant
    Filed: July 16, 2009
    Date of Patent: September 18, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Bum Sohn, Young Tae Kim, Kang Heon Hur, Min Hee Hong, Hew Young Kim, Doo Young Kim
  • Patent number: 8248753
    Abstract: A dielectric ceramic for use in dielectric ceramic layers has a main component represented by a composition formula of (Sr1-x-ySnxBay)TiO3, wherein x is 0.005?x?0.24, y is 0?y?0.25 in the composition formula. Preferably, the dielectric ceramic includes 0.01 mol to 5 mol of M (M is at least one of Mn and V) calculated as MO and/or 0.2 mol to 5 mol of Si calculated as SiO2, with respect to 100 mols of the main component, and more preferably, further includes 0.1 mol to 25 mol of Ca calculated as CaO with respect to 100 mols of the main component. The dielectric ceramic has an increased dielectric constant permitting size reduction when used in a laminated ceramic capacitor.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 21, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shoichiro Suzuki, Toshikazu Takeda
  • Patent number: 8194391
    Abstract: A multilayer ceramic electronic component including thin external terminal electrodes each having a superior bonding force to a ceramic base body is provided. In order to form the external terminal electrodes, after Cu plating films are deposited on exposed portions of internal electrodes by direct plating on a ceramic base body, a Cu liquid phase, an O2-containing liquid phase, and a Cu solid phase are generated between the Cu plating film and the ceramic base body by a heat treatment, so that Cu oxides are dispersed in the Cu plating film, at least near an interface with the ceramic base body. Since the Cu oxides function as an adhesive, a bonding force of the Cu plating film to the ceramic base body can be increased, and hence the external terminal electrode having a superior bonding force to the ceramic base body can be obtained.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 5, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shunsuke Takeuchi, Kenichi Kawasaki, Akihiro Motoki, Makoto Ogawa, Shuji Matsumoto, Seiichi Nishihara
  • Patent number: 8134823
    Abstract: In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 13, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen, Su-Tsai Lu
  • Patent number: 7847371
    Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion with a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component of the present invention is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 14 has such constitution that a first electrode layer connected with the internal electrode 14, a second electrode layer (electroconductive resin layer) including a hardened product of epoxy resin containing an epoxy compound having a molecular weight of 2000 or more and plural epoxy groups as the base compound, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: December 7, 2010
    Assignee: TDK Corporation
    Inventors: Takashi Komatsu, Kouji Tanabe
  • Patent number: 7813104
    Abstract: A ceramic element, including: a ceramic body having an internal electrode layer and a ceramic layer; an external electrode having a base electrode which is provided on the outside of the ceramic body so as to be electrically connected with the internal electrode layer, and a plating layer covering the outer surface of the base electrode; and a protective layer for covering at least a portion of the outer surface of the ceramic layer other than the portion covered by the external electrode, wherein the protective layer includes a first layer that is an insulating layer containing an insulating oxide, and a second layer that is an insulating layer containing the same insulating oxide as the first layer and an element that is the same as at least one of elements forming the ceramic layer, and the first layer and second layer are formed in that order from the inside.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: October 12, 2010
    Assignee: TDK Corporation
    Inventors: Mutsuko Nakano, Kyoji Koseki, Hisashi Aiba, Yukihiro Murakami, Kazuto Takeya
  • Patent number: 7799409
    Abstract: A ceramic green sheet structure has a ceramic green sheet including at least a ceramic material and a resin and a conductive layer formed on the ceramic green sheet. An electrode non-formed area has a porosity equal to or greater than 17%, and preferably, equal to or less than 25%. Moreover, an electrode formed area where the conductive layer is formed may have a smaller porosity than the electrode non-formed area where no conductive layer is formed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 21, 2010
    Assignee: TDK Corporation
    Inventors: Toshihiro Iguchi, Akitoshi Yoshii, Akira Goshima, Kazuyuki Hasebe, Takaki Shinkawa, Hiroki Saitoh, Makoto Takahashi
  • Publication number: 20100157508
    Abstract: A method of manufacturing complex oxide nano particles includes preparing a mixed solution including at least one metal salt selected from the group consisting of aluminum salt, manganese salt and barium salt, impregnating an organic polymer having nano-sized pores with the mixed solution, and calcining the organic polymer impregnated with the mixed solution. Accordingly, complex oxides with particle sizes on the nanoscale can be prepared, and the kind and composition ratio of metal elements contained in the complex oxides can be facilitated. Also, a multilayer ceramic capacitor including the complex metal oxides manufactured by this method can ensure a super slim profile and high capacity.
    Type: Application
    Filed: June 29, 2009
    Publication date: June 24, 2010
    Inventors: Chul Tack Lim, Chang Hwan Choi, Byoung Jin Chun, Jin Hyuck Yang
  • Patent number: 7735206
    Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Patent number: 7719818
    Abstract: An object of the present invention is to provide a material for forming a capacitor layer comprising a dielectric layer formed by any one of a sol-gel method, an MOCVD method, and a sputtering deposition method. The material can reduce a leakage current of a capacitor circuit. In order to achieve the object, a material for forming a capacitor layer comprising a dielectric layer between a first conductive layer to be used for forming a top electrode and a second conductive layer to be used for forming a bottom electrode, characterized in that the dielectric layer is a dielectric oxide film formed by any one of a sol-gel method, an MOCVD method, and a sputtering deposition method; and particles constituting the dielectric oxide film are impregnated with a resin component is employed.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Naohiko Abe, Akiko Sugioka, Akihiro Kanno, Hirotake Nakashima
  • Patent number: 7685703
    Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance, a printed circuit board having the capacitor mounted thereon, and a method of making. Sheets of green-state ceramic dielectric material and glass/metal composite material are laminated together, diced into individual chips, and fired to sinter the glass and the ceramic together. The composite material contains an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the printed circuit board. Vertically-oriented surface mountable capacitors and hybrid capacitors are provided.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: March 30, 2010
    Assignee: Presidio Components, Inc.
    Inventors: Alan Devoe, Lambert Devoe, Hung Trinh
  • Patent number: 7569452
    Abstract: A filter capacitor comprising a pre-sintered substrate supporting alternating active and ground electrode layers segregated by a dielectric layer is described. The substrate is of a ceramic material that maintains its shape and structure dimensions even after undergoing numerous sintering steps. Consequently, relatively thin active and ground electrode layers along with the intermediate dielectric layer can be laid down or deposited by a screen-printing technique. Using a relatively thin over-glaze in comparison to a thick upper dielectric layer finishes the capacitor. Consequently, a significant amount of space is saved in comparison to a comparably rated capacitor or, a capacitor of a higher rating can be provided in the same size as a conventional prior art capacitor. The pre-sintered ceramic substrate is used instead of conventional tape cast technology for the base dielectric.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: August 4, 2009
    Assignee: Greatbatch Ltd.
    Inventors: Richard Fu, Christine Frysz, Mingguang Zhu, Kenneth Billings
  • Patent number: 7531112
    Abstract: Disclosed is a composition for forming a dielectric, which is applied to an embedded capacitor with a high dielectric constant, a capacitor produced using the composition, and a PCB provided with the capacitor. The composition includes 40 to 99 vol % of thermoplastic or thermosetting resin, and 1 to 60 vol % of semiconductive filler. Alternatively, the composition includes 40 to 95 vol % of thermoplastic or thermosetting resin, and 5 to 60 vol % of semiconductive ferroelectric substance. Furthermore, the present invention provides the capacitor, produced using the composition, and the PCB provided with the capacitor. Therefore, the dielectric, which is produced using the composition including the semiconductive filler or semiconductive ferroelectric substance, is advantageous in that the dielectric constant is high and a dielectric loss is low. The dielectric is usefully applied to produce an embedded capacitor with the high dielectric constant and the PCB provided with the embedded capacitor.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: May 12, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyo Soon Shin, Jin Ho Kim, Jeong Joo Kim, Min Ji Ko
  • Publication number: 20090103236
    Abstract: A paste composition containing (a) a resin, (b) high dielectric constant inorganic particles having a perovskite crystal structure, and (c) an organic solvent, wherein the average particle diameter of the high dielectric constant inorganic particles is 0.002 ?m to 0.06 ?m, and the amount of all organic solvents is 35 wt % to 85 wt % based on the total amount of the paste composition. Further, a dielectric composition containing (a) a resin and (b) high dielectric constant inorganic particles having a perovskite crystal structure, wherein the average particle diameter of the high dielectric constant inorganic particles (b) is 0.002 ?m to 0.06 ?m.
    Type: Application
    Filed: September 1, 2006
    Publication date: April 23, 2009
    Inventors: Toshihisa Nonaka, Yoshitake Hara, Masahiro Yoshioka
  • Patent number: 7310216
    Abstract: An electro-magnetic interference filter terminal assembly for active implantable medical devices includes a structural pad in the form of a substrate or attached wire bond pad, for convenient attachment of wires from the circuitry inside the implantable medical device to the capacitor structure via thermal or ultrasonic bonding, soldering or the like while shielding the capacitor from forces applied to the assembly during attachment of the wires.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: December 18, 2007
    Assignee: Greatbatch-Sierra, Inc.
    Inventors: Robert A. Stevenson, Richard L. Brendel, Christine Frysz, Haytham Hussein, Scott Knappen, Ryan A. Stevenson
  • Patent number: 7251120
    Abstract: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The first coil and the second coil are electrically connected in series to form a spiral coil. The coil portion composed of a ferrite ceramic having a small number of pores has a high permeability and a high dielectric constant, and the coil portion composed of a ferrite ceramic having a large number of pores has a low permeability and a low dielectric constant.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: July 31, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoo Takazawa
  • Patent number: 7190568
    Abstract: A multilayer contact approach for use in a planar solid oxide fuel cell stack includes at least 3 layers of an electrically conductive perovskite which has a coefficient of thermal expansion closely matching the fuel cell material. The perovskite material may comprise La1-xEx Co0.6Ni0.4O3 where E is a alkaline earth metal and x is greater than or equal to zero. The middle layer is a stress relief layer which may fracture during thermal cycling to relieve stress, but remains conductive and prevents mechanical damage of more critical interfaces.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: March 13, 2007
    Assignee: Versa Power Systems Ltd.
    Inventors: Anthony Wood, Zheng Tang, Tahir Joia
  • Patent number: 7123464
    Abstract: A high pressure condenser for a magnetron, in which a pair of dielectric ceramics having an arch shape are separated from each other, central conductors are connected to internal peripheries of the dielectric ceramics, and a ground metal is connected to external peripheries of the dielectric ceramics, thereby not requiring any additional structure for connecting the dielectric ceramics and the central conductors, simplifying the structures of the central conductors, and reducing the quantity of the dielectric ceramics needed in proportion to the separation interval between the dielectric ceramics.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: October 17, 2006
    Assignee: LG Electronics Inc.
    Inventors: Seung Won Baek, Yong Soo Lee, Jong Soo Lee
  • Patent number: 7048993
    Abstract: A method to produce a distortion-free asymmetrical low-temperature co-fired ceramic structure comprising at least one layer of glass-containing internal constraining tape and at least one layer of glass-containing primary tape wherein the internal constraining tape and the primary tape are laminated to form an asymmetrical laminate and wherein a release layer is deposited on at least one surface of the laminate forming an assembly, wherein the surface is opposite the position of greatest asymmetry of the laminated layers and wherein the assembly is thermally processed producing a structure exhibiting an interactive suppression of x,y shrinkage.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: May 23, 2006
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Carl B. Wang, Kenneth Warren Hang, Christopher R. Needes
  • Patent number: 7035079
    Abstract: The present invention provides an MLCC and an MLCC array. The MLCC has desirably low ESL properties by forming the first and second internal electrodes to be spaced apart from each other on the same dielectric layer while overlapping with other first and second internal electrodes on the neighboring dielectric layers, and connecting the first and second internal electrodes to the external terminals provided on the top surface or the bottom surface of the capacitor body through conductive via holes formed in the capacitor body in a stacking direction of the capacitor body.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: April 25, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Soo Park, Dong Seok Park, Byoung Hwa Lee, Min Cheol Park, Hyun Ju Yi, Min Kyoung Kwon, Hae Suk Chung, Chang Hoon Shim, Seung Heon Han
  • Patent number: 7029962
    Abstract: Embodiments of methods of forming capacitors are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventor: Larry Eugene Mosley
  • Patent number: 6985349
    Abstract: A method for making an electronic module includes forming a low temperature co-fired ceramic (LTCC) substrate with at least one capacitive structure embedded therein. Forming the LTCC substrate may include arranging first and second unsintered ceramic layers and the at least one capacitive structure therebetween. The at least one capacitive structure may include a pair of electrode layers, an inner dielectric layer between the pair of electrode layers, and at least one outer dielectric layer adjacent at least one of the electrode layers and opposite the inner dielectric layer. The at least one outer dielectric layer preferably has a dielectric constant less than a dielectric constant of the inner dielectric layer. The unsintered ceramic layers and the at least one capacitive structure may also be heated, and at least one electronic device may be mounted on the LTCC substrate and electrically connected to the at least one embedded capacitive structure.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: January 10, 2006
    Assignee: Harris Corporation
    Inventors: Thomas Patrick Smyth, Michelle Kay Nelson, Sarah K. Mobley, Charles Michael Newton
  • Patent number: 6961231
    Abstract: Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: November 1, 2005
    Assignee: Xilinx, Inc.
    Inventors: Mark A. Alexander, Robert O. Conn, Steven J. Carey
  • Patent number: 6898068
    Abstract: An embodiment of the invention is a capacitor comprising a bottom electrode 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, sidewalls 105, and a top electrode 110 coupled to a second interconnect 30b of the top metal level 10. Another embodiment of the invention is a method of manufacturing a capacitor using a first mask 140 to form a material stack that includes a bottom electrodes 70 coupled to a first interconnect 30a of the top metal level 10, a capacitor dielectric 90, and a partial top electrode 100. The method further includes using a second mask 150 to form a complete top electrode coupled to a second interconnect 30b of the top metal level 10.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: May 24, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy A. Rost, Edmund Burke, Satyavolu S. Papa Rao, Rose Alyssa Keagy
  • Patent number: 6885541
    Abstract: A capacitor comprising: a thin film laminate including a plurality of dielectric thin films and a plurality of electrode conductor thin films laminated alternately; and first kind terminals and second kind terminals formed over a first main surface of said thin film laminate and isolated from each other in a DC current, wherein a first kind electrode conductor thin films electrically connecting with said first kind terminals and a second kind electrode conductor thin films electrically connecting with said second kind terminals are so alternately laminated in a laminate direction as are separated by said dielectric thin films, and a first dielectric thin film, an other kind electrode conductor thin film and a second dielectric thin film are laminated in this order between one same kind electrode conductor thin film and other same kind electrode conductor thin film adjoining in said laminate direction, and first through holes, second through holes and the like are defined herein.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: April 26, 2005
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Jun Otsuka, Manabu Sato
  • Patent number: 6885543
    Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 26, 2005
    Assignee: Marvell International, Ltd.
    Inventors: Farbod Aram, Sehat Sutardja
  • Patent number: 6856501
    Abstract: A capacitor has a couple of electrodes with a dielectric placed therebetween. At least one of the electrodes is made of copper, and barriers for preventing the diffusion of copper into the dielectric are provided between the dielectric and the copper electrode, respectively.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: February 15, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hideaki Matsuhashi
  • Patent number: 6822848
    Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: November 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Martin Ceredig Roberts, Christophe Pierrat
  • Patent number: 6808813
    Abstract: A ceramic electronic device is protected at the surface from retention of water, thus having improved operation reliability, and a method of manufacturing the device is provided. A protective layer is formed on the ceramic element and external electrodes by dehydrating condensation of organic silicon compound.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: October 26, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Kimura, Emiko Igaki, Hiroshi Ito, Osamu Yamashita, Masakazu Tanahashi
  • Publication number: 20040179326
    Abstract: A monolithic ceramic capacitor includes a plurality of stacked ceramic dielectric layers, thin internal conductors that are each placed between the ceramic dielectric layers and arranged in parallel, and external conductors each electrically connected to ends of the corresponding internal conductors. The ceramic dielectric layers have a thickness of about 0.5 &mgr;m to less than about 1.5 &mgr;m. The internal conductors have a thickness of about 0.1 &mgr;m to about 0.4 &mgr;m. The internal conductors each have spaces therein and the total area percentage of the spaces in each internal conductor is more than about 10% to less than about 40% of the area of the internal conductor. The ceramic dielectric layers contain a sintering additive containing Si, and the sintering additive is placed in the spaces in a segregated manner.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 16, 2004
    Inventor: Koji Hattori
  • Patent number: 6739027
    Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: John M. Lauffer, Konstantinos Papathomas