Ceramic And Glass Patents (Class 361/320)
  • Publication number: 20040179326
    Abstract: A monolithic ceramic capacitor includes a plurality of stacked ceramic dielectric layers, thin internal conductors that are each placed between the ceramic dielectric layers and arranged in parallel, and external conductors each electrically connected to ends of the corresponding internal conductors. The ceramic dielectric layers have a thickness of about 0.5 &mgr;m to less than about 1.5 &mgr;m. The internal conductors have a thickness of about 0.1 &mgr;m to about 0.4 &mgr;m. The internal conductors each have spaces therein and the total area percentage of the spaces in each internal conductor is more than about 10% to less than about 40% of the area of the internal conductor. The ceramic dielectric layers contain a sintering additive containing Si, and the sintering additive is placed in the spaces in a segregated manner.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 16, 2004
    Inventor: Koji Hattori
  • Patent number: 6739027
    Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: John M. Lauffer, Konstantinos Papathomas
  • Patent number: 6738251
    Abstract: The present invention provides a conductive pattern that has low electric resistivity, is superior in adhesion to a substrate and does not cause substrate cracking during plating, a multilayered substrate incorporating such a conductive pattern, and a fabricating method for a multilayered substrate. At first, a conductive composition including a metal powder containing not less than 95 mass % of Ag, a sintering restrainer containing Cr and/or Cr compound, a dielectric loss conditioner containing Mn and/or Mn compound, and a vehicle is prepared. Next, electrodes made of the conductive composition are formed on a plurality of green sheets. The plurality of green sheets formed with the electrodes are then laminated to form a laminated product, whereafter the laminated product is sintered.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 18, 2004
    Assignee: TDK Corporation
    Inventors: Hiroshi Tsuyuki, Osamu Hirose
  • Publication number: 20040090733
    Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance that may be easily and inexpensively manufactured. To this end, sheets of green-state ceramic dielectric material and ceramic/metal composite material are laminated together, diced into individual chips, and fired to sinter the ceramic together. The composite material may comprise an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the pc board. Alternatively, the composite material may comprise an amount of metal insufficient to render the composite conductive but sufficient to act as seed points for an electroplating process wherein the composite is preferentially coated with conductive metal, and the coated composite is mounted to the pc board and the coating provides an electrical connection to an internal electrode.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 13, 2004
    Applicant: Presidio Components, Inc.
    Inventors: Alan Devoe, Lambert Devoe, Hung Trinh
  • Patent number: 6731494
    Abstract: A capacitor 19 comprises a lower electrode 14 formed on a substrate 10, an upper electrode 18 opposed to the lower electrode, and a capacitor dielectric film 16 formed between the lower electrode and the upper electrode, in which at least one of the lower electrode and the upper electrodes is an electrode of a metal substituted layer. The lower electrodes of polysilicon are formed, and then after the high-temperature heat processing for improving film quality of the capacitor dielectric film has been performed, the lower electrodes of polysilicon is substituted with aluminum to form the lower electrodes of aluminum, whereby aluminum, which cannot withstand the heat processing for improving film quality of the capacitor dielectric film can be used as a material of the lower electrodes. Thus, capacitors having good high-speed response can be formed.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: May 4, 2004
    Assignee: Fujitsu Limited
    Inventor: Shunji Nakamura
  • Patent number: 6673461
    Abstract: A multilayer ceramic capacitor is formed by alternately stacking a plurality of dielectric layers and a multiplicity of internal electrodes, which are connected to a pair of external electrodes. Each of the dielectric layers is obtained from a dielectric ceramic compound composed of ceramic grains and a glass component connecting the ceramic grains, and the glass component contains one or more additive elements in a form of a solid solution. The additive elements are selected from the group consisting of Mn, V, Cr, Mo, Fe, Ni, Cu and Co.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 6, 2004
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Hirokazu Chazono, Hisamitsu Shizuno, Hiroshi Kishi
  • Patent number: 6625006
    Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: September 23, 2003
    Assignee: Marvell International, Ltd.
    Inventors: Farbod Aram, Sehat Sutardja
  • Patent number: 6611421
    Abstract: Non-polar tantalum capacitors and non-polar tantalum capacitor arrays with compact designs are provided. The reduced volume and footprint of the capacitors and arrays in turn reduces the amount of space required in any device in which they are used. In addition, the cost of materials is reduced, and the manufacturing is simplified. Some embodiments of the present invention provide an electromechanical connector between the anode rods of each pair of polar tantalum capacitors, and insulation between the remainder of the capacitor bodies, thus providing a non-polar tantalum capacitor. These non-polar capacitors are mechanically connected to make a non-polar tantalum capacitor array. Other embodiments of the present invention provide for physically connecting the anode rods of the polar capacitors. An insulating encapsulant around the connected rods and between the polar capacitor bodies also holds the capacitors and capacitor arrays together.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 26, 2003
    Assignees: AVX Corporation, Advanced Bionics Corporation
    Inventors: Paul M. Meadows, James A. McAllister, David H. Payne, Douglas M. Edson
  • Patent number: 6556422
    Abstract: A dielectric ceramic composition, a multi-layer ceramic capacitor and a manufacturing method characterized by superior dielectric properties. The ceramic capacitor includes a chip having a plurality of dielectric layers, a plurality of internal electrodes stacked alternately with the dielectric layers, and a pair of outer electrodes formed on both sides of the chip, with the composition of the dielectric layers including: 100 moles of barium calcium titanate BaCaxTiO3 (0.001≦x≦0.02), 0.5-4 moles of MgO, 0.01-0.5 moles of MnO, 0.1—2 moles of BaO, 0.1-2 moles of CaO, 1-4 moles of SiO2, and 0.1-3 moles of at least one or more compounds selected from the group consisting of Y2O3, Dy2O3, Ho203 and Er2O3. The capacitor thus manufactured satisfies the X7R standard and has superior dielectric properties, and the deviations of the dielectric properties are extremely low, thereby ensuring a high reliability.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: April 29, 2003
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Gyun Kim, Seong Won Cho, Seong Un Ma, Kang Heon Her, Jong Yeon Lee
  • Publication number: 20030016484
    Abstract: A method of producing ceramic laminates comprising the steps of forming a ceramic green sheet by applying a ceramic slurry onto a carrier film; forming, maintaining a predetermined gap, a plurality of electrically conducting patterns having inclined surfaces at the ends thereof by printing an electrically conducting paste onto the main surface of said ceramic green sheet; forming ceramic patterns having inclined surfaces at the ends thereof among said electrically conducting patterns by printing a ceramic paste maintaining a distance of not smaller than 10 &mgr;m from said electrically conducting patterns; and laminating ceramic green sheets on which are formed said electrically conducting patterns and said ceramic patterns.
    Type: Application
    Filed: May 24, 2002
    Publication date: January 23, 2003
    Applicant: KYOCERA CORPORATION
    Inventors: Toshihiro Iwaida, Seiichi Koizumi
  • Patent number: 6470545
    Abstract: Embedded green multi-layer ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates are provided. A first set of electrodes is printed on a ceramic tape. A first dielectric layer is placed over the first set of electrodes and the ceramic tape. A second set of electrodes is printed on the first dielectric layer. A second dielectric layer is placed over the second set of electrodes and the first dielectric layer. A third set of electrodes is printed on the second dielectric layer. The sheet is then cut to form separate green multi-layer ceramic capacitor chips. The green multi-layer ceramic capacitor chips are then placed in a cavity formed by ceramic tape.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 29, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Shaul Branchevsky
  • Patent number: 6452780
    Abstract: A capacitor including a ceramic body, a glass layer formed on each of opposite surfaces of the ceramic body, and a first metallic layer formed on the glass layer. Preferably, a lead terminal is connected to the first metallic layer or to a second metallic layer which is provided on the first metallic layer, by use of solder containing Pb in an amount of 2.5 wt. % or less. Preferably, a lead terminal which is plated with a substance containing Pb in an amount of 5 wt. % or less is soldered onto the first metallic layer or the second metallic layer.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: September 17, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinichi Kobayashi, Shuji Watanabe, Yoshitaka Kageyama, Akira Nagai, Osamu Yamaoka, Mitsuru Nagashima, Yuko Ihara
  • Patent number: 6430030
    Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventors: Mukta S. Farooq, Harvey C. Hamel, Robert A. Rita, Herbert I. Stoller
  • Publication number: 20020075632
    Abstract: A multilayer ceramic capacitor comprises internal electrode layers and dielectric layers. An average particle diameter (R), in a direction parallel with said internal electrode layer, in dielectric particles constituting said dielectric layers is larger than a thickness (d) of said dielectric layer. A ratio (R/d) between the average particle diameter (R) and the thickness (d) of the dielectric layer is 1<R/d<3.
    Type: Application
    Filed: May 29, 2001
    Publication date: June 20, 2002
    Applicant: TDK CORPORATION
    Inventors: Yukie Nakano, Shunichi Yuri, Mari Miyauchi, Daisuke Iwanaga
  • Patent number: 6407905
    Abstract: A capacitor electrode includes a film base member having connection means located thereon so that the capacitor electrode may be connected to an external component, and a segmented metallized layer connected to the connection means, the metallized layer being made of metallized segments interconnected by current gates. The segmented,metallized layer has a thickness which varies or differs continuously along a length thereof, and the current gates have a width which increases as the thickness of the segmented metallized layer decreases.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: June 18, 2002
    Assignee: ABB Corporate Research Ltd.
    Inventors: Joseph Connolly, Tommy Holmgren, Martin Carlen, Dennis Young-Cannon
  • Patent number: 6396680
    Abstract: A monolithic capacitor including a sintered body formed from a TiO2-containing reduction-resistant dielectric ceramic material; a plurality of internal electrodes which are formed inside the sintered body, the electrodes being formed of a base metal; and first and second external electrodes which are formed on the sintered body, the internal electrodes being electrically connected to the external electrodes; wherein the amount of Ti contained in a secondary phase of the sintered body is about 2 wt. % or less as TiO2. A process for producing the monolithic capacitor of the present invention is also disclosed.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 28, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshiki Nishiyama, Takayuki Nishino, Yasunobu Yoneda
  • Patent number: 6396681
    Abstract: A nonreducing dielectric contains a main-component having a perovskite crystal phase and satisfying the formula (Ca1-a-b-cSraBabMgc)m(Zr1-w-x-y-zTiwMnxNiyHfz)O3 and a compound oxide represented by the formulae (Si, T)O2—MO—XO and (Si, T)O2—(Mn, M′)O—Al2O3. The ratio of the intensity of the maximum peak of a crystal phase not of the perovskite crystal phase to the intensity of the maximum peak assigned to the perovskite crystal phase appearing at 2&thgr;=25 to 35° is about 5% or less in a CuK&agr; X-ray diffraction pattern.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: May 28, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Naito, Tomoo Motoki, Harunobu Sano
  • Patent number: 6381117
    Abstract: A ceramic electronic component includes at least one component body having two end faces opposing each other and side faces connecting the two end faces, and terminal electrodes formed on the component body. Each of the terminal electrodes extends from each end face to edge portions of each side face of the component body. Each of the terminal electrodes includes a metal layer formed on at least each end face of the component body, a conductive resin layer for covering at least portions of the side faces of the component body, and a metal plating film covering the outer surface of the terminal electrode. The conductive resin layer extends from the metal layer including the edge of the metal layer to the portions of the side faces, and includes a conductive resin containing metal powder and resin. The thickness of the conductive resin layer above the side faces is at least about 10 &mgr;m.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: April 30, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takuji Nakagawa, Yoshikazu Takagi, Yasunobu Yoneda, Toru Watanabe
  • Patent number: 6362949
    Abstract: A laminated ceramic electronic component using a ceramic sintered body mainly comprising CaZrO3, which can be fired in a neutral or reducing atmosphere at a low temperature and in which inner electrodes are formed using cheap base metals. The inner electrodes Ni are disposed so as to be stacked via a ceramic layer in the ceramic sintered body having a principal component of CaZrO3 and containing a MnO2 phase and a glass phase, and forming outer electrodes on the outer surfaces of the ceramic sintered body.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: March 26, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Takashima, Yasunobu Yoneda
  • Patent number: 6356037
    Abstract: An inexpensive capacitor for pulse generation whose characteristics do not deteriorate even when the capacitor is used in a high temperature, high vacuum, reducing atmosphere, and which enables generation of high-voltage pulses over a wide temperature range. The dielectric body 1 of the capacitor is constructed of a non-linear dielectric ceramic which exhibits resistance to reduction. The non-linear dielectric ceramic comprises a polycrystalline substance containing barium titanate as a primary component, and when the polycrystalline substance is represented by (1−a−b)ABO3+aM+bR wherein ABO3 is a barium titanate component and represents a perovskite structure, M is an oxide of at least one element selected from the group consisting of Mn, Ni and Co, R is an oxide of at least one element selected from the group consisting of La, Ce, Nd, Pr, Sm, Eu, Gd, Tb, Dy, Ho, Er and Yb, and a and b represent mole fractions; A, B, a, and b satisfy the following relationships: 1.000≦A/B≦1.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: March 12, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harunobu Sano, Kazuhiro Harada, Osamu Yamaoka, Shinichi Kobayashi, Toshiya Esumi, Yoshitaka Kageyama
  • Patent number: 6304425
    Abstract: A circuit board having coupled multilayered ceramic capacitors mounted thereon considerably reduces the generation of sounds developed by piezoelectric effects in the capacitors. A method for mounting the capacitors on the circuit board includes the step of forming lands for mounting the capacitors thereon at substantially plane-symmetrical positions on the front surface and the back surface of the circuit board, two lands at their substantially plane-symmetrical positions being connected each other. The capacitors, which are substantially identical each other, are then mounted on the lands of the front and the back surfaces such that the capacitors are disposed at substantially plane-symmetrical positions and electrically coupled to the lands.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: October 16, 2001
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Nobuo Mamada
  • Patent number: 6274899
    Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: August 14, 2001
    Assignee: Motorola, Inc.
    Inventors: Bradley M. Melnick, Bruce E. White, Jr., Douglas R. Roberts, Bo Jiang
  • Patent number: 6266227
    Abstract: A thin-film capacitor in which a plurality of capacitor elements are arranged side by side, each capacitor element being constituted by a dielectric layer, a first electrode layer formed on the lower surface of said dielectric layer, and a second electrode layer formed on the upper surface of said dielectric layer, wherein among the neighboring capacitor elements, there are provided first terminal electrode layers for connecting the neighboring first electrode layers together, and second terminal electrode layers for connecting the neighboring second electrode layers together; said first terminal electrode layers and said second terminal electrode layers are so arranged as will not be overlapped one upon the other; and said first and second terminal electrode layers are provided with an external terminal, respectively. The capacitor can be easily mounted on an external board and has a low-inductance structure.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: July 24, 2001
    Assignee: Kyocera Corporation
    Inventors: Shigeo Konushi, Tsuneo Mishima
  • Patent number: 6266226
    Abstract: There is provided a capacitor employed in a MMIC and having a structure which is capable of increasing a capacitance of occupied areas of capacitor patterns and also reducing variation of a capacitance value in mass production. A substantial comb-type lower electrode 11 is formed on a substrate 14, then a dielectric layer 13 is formed on the lower electrode 11, and then a substantial comb-type upper electrode 12 is formed on the dielectric layer 13. Respective element electrodes 16 (15) of one of the lower electrode 11 and the upper electrode 12 are arranged in blank areas between respective element electrodes 15 (16) of the other of the lower electrode 11 and the upper electrode 12.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: July 24, 2001
    Assignee: TDK Corporation
    Inventor: Katsuhiko Hayashi
  • Patent number: 6256850
    Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: John M. Lauffer, Konstantinos Papathomas
  • Patent number: 6245433
    Abstract: A dielectric ceramic composition containing a primary component represented by the following formula: {BaO}mTiO2+&agr;M2O3+&bgr;R2O3+&ggr;BaZrO3+gMgO+hMnO wherein M2O3 is at least one of Sc2O3 or Y2O3; R2O3 is at least one member selected from the group consisting of Eu2O3, Gd2O3, Tb2O3. Dy2O3, Ho2O3, Er2O3, Tm2O3 and Yb2O3; &agr;, &bgr;, &ggr;, g or h represent a mole ratio and satisfy specified relations; and silicon oxide as an auxiliary component in an amount of 0.2-5.0 mol as SiO2, with respect to 100 mol of the primary component.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: June 12, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tomoyuki Nakamura, Shinobu Mizuno, Harunobu Sano
  • Patent number: 6205015
    Abstract: A dielectric ceramic which exhibits an excellent electrostatic capacity-temperature characteristic; which allows use of a base metal such as nickel; which can be fired in a reducing atmosphere; and which is suitable for constituting a dielectric ceramic layer of a laminated ceramic electronic element such as a laminated ceramic capacitor; is obtained by firing barium titanate powder in which the c-axis/a-axis ratio in the perovskite structure is in the range of about 1.003 to 1.010 and the amount of OH groups in the crystal lattice is about 1 wt. % or less. The barium titanate powder a starting material preferably has a maximum particle size of about 0.5 &mgr;m or less and an average particle size of about 0.1-0.3 &mgr;m, and individual particles of the barium titanate powder comprise a low-crystallinity portion 21 and a high-crystallinity portion 23, with the diameter of the low-crystallinity portion being less than about 0.65 times the particle size of the powder.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: March 20, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Nobuyuki Wada, Jun Ikeda, Takashi Hiramatsu, Yukio Hamaji
  • Patent number: 6195250
    Abstract: Laminated ceramic parts such as a laminated ceramic condenser and a laminated LC filter are formed by using a temperature compensating dielectric ceramic composition having a high relative dielectric constant and a high Q value, and which can be sintered at a relatively low temperature during the manufacturing processes, without causing any undesired variations in ceramic properties during the sintering treatment. The composition includes 100 parts by weight of a main component having a mole composition ratio (BaO, TiO2, Re2O3) shown in a ternary composition diagram indicated by an area surrounded by point A (39.5. 59.5, 1), point B (1, 59.5, 39.5), point C (1, 85, 14) and point D (14, 85, 1); about 25 parts by weight or less of a lead free B2O3—SiO2 glass; at least one of V oxide (the content as V2O5 being about 10 parts by weight or less) and W oxide (the content as WO3 being about 20 parts by weight or less).
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: February 27, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Matoba, Harunobu Sano
  • Patent number: 6191934
    Abstract: High dielectric constant capacitors are made from a dielectric ink of lead-magnesium-niobate and lead oxide powders. Dielectric inks are made by mixing the dielectric powders with a suitable organic vehicle which can be used to coat one or more glass-based green tapes. Buried capacitors are made by coating an overlying and an underlying green tape with a conductor such as silver. Capacitors can also be made by adjusting the organic vehicle and forming a green tape from the dielectric powders. These dielectric green tapes each can be coated with a conductive layer and stacked, the conductive layers connected in parallel. The resultant multilayer capacitors have a very high dielectric constant, while eliminating the need for very large area capacitors, as compared to single layer capacitors.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: February 20, 2001
    Assignees: Sarnoff Corporation & Co., Ltd., Daewoo Electronics Co., Ltd.
    Inventors: Michael James Liberatore, Attiganal Narayanaswamy Sreeram, Ashok Narayan Prabhu, In-Tae Kim, Je-Do Mun, Sung-Dae Park, Yun-Hwi Park, Joo-Dong Yu, Ellen S. Tormey
  • Patent number: 6147857
    Abstract: An integrated circuit includes main power busses located on the next to the top most level of metal and a top level of metal separated from the main power busses by a thin dielectric. The top most level metal is connected to one of the power buses either through bond wires or through contacts. This structure provides a distributed bypass capacitance between the power buses thus stabilizing the power bus voltage within the integrated circuit. Furthermore, this capacitance structure can be optional and can be made with one or two masking steps.
    Type: Grant
    Filed: October 7, 1997
    Date of Patent: November 14, 2000
    Assignee: E. R. W.
    Inventors: Eugene Robert Worley, Richard Arthur Mann
  • Patent number: 6125027
    Abstract: A component includes a substrate layer (1) of glass or Al.sub.2 O.sub.3, an anti-reaction layer (2) or a levelling layer (2), two electrode layers (3, 5) and a dielectric layer (4) as well as such a capacitor. Manufacture a component which provides for cost-effective, surface-mountable (SMD). The anti-reaction layer (2) on the glass substrate (1) or the levelling layer (2) on the Al.sub.2 O.sub.3 -substrate (1) is made of at least one specific material. An anti-reaction layer or a levelling layer (2) of one of the above-mentioned substances or a combination of several substances, enables a dielectric layer (4) to be provided by means of which a high capacitance value is achieved.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: September 26, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Mareike Klee, Wolfgang Brand, Wilhelm Hermann, Mathieu J. E. Ulenaers, Gijsbertus A. C. M. Spierings, Hendrikus J. J. M. Van Haren
  • Patent number: 6118649
    Abstract: Provided is a dielectric paste containing glass powder, lead perovskite compound dielectric powder and organic vehicle, wherein the glass powder has a composition represented by xBi.sub.2 O.sub.3 --yPbO--zSiO.sub.2 where x+y+z is 100 mol parts and the values of x, y and z are on lines or within a region enclosed by lines passing through five points A(25, 5, 70), B(10, 20, 70), C(10, 60, 30), D(35, 60, 5) and E(90, 5, 5) on a ternary diagram. The dielectric paste allows a minute dielectric film to be formed by sintering at a low temperature below 870.degree. C.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: September 12, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiromichi Kawakami, Hiroji Tani
  • Patent number: 6072690
    Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.
    Type: Grant
    Filed: January 15, 1998
    Date of Patent: June 6, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mukta S. Farooq, Harvey C. Hamel, Robert A. Rita, Herbert I. Stoller
  • Patent number: 6072207
    Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: June 6, 2000
    Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.
    Inventors: Hiroyuki Yoshimori, Carlos A. Paz De Araujo, Takeshi Ito, Michael C. Scott, Larry D. McMillan
  • Patent number: 6058005
    Abstract: Disclosed is a dielectric ceramic composition containing an essential component represented by the formula, xBaO-yTiO.sub.2 -zRe.sub.2 O.sub.3, wherein x, y and z are in mol %; x+y+z=100; and (x, y, z) falls within a polygonal region defined by four points of A (39.5, 59.5, 1), B (1, 59.5, 39.5), C (1, 85, 14) and D (14, 85, 1), and further containing V, Cu and Mn as side components in an amount of about 0.1 wt. % to 15 wt. % in terms of V.sub.2 O.sub.5, in an amount not greater than 10 wt. % in terms of CuO, and in an amount not greater than 1 wt. % in terms of MnO, respectively, relative to 100 wt. % of the essential component.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: May 2, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Matoba, Harunobu Sano
  • Patent number: 6055151
    Abstract: Embedded passive components such as capacitors are formed in multilayer ceramic circuit boards by screen printing a component precursor compound ink sandwiched between conductor ink layers onto a green tape stack and covering the component ink layer with one or two green tape layers, aligning and laminating the green tapes and firing. Capacitor inks are made from dielectrics chosen from barium titanate, titanium oxide and lead-magnesium-niobate. The green tapes are made of a mixture of a crystallizing glass, a non-crystallizing glass and an oxide filler which does not shrink in the x and y dimensions during firing mounted on a metal support. Thus the embedded components can be made to close tolerances.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: April 25, 2000
    Assignees: Sarnoff Corp, Sharp K.K.
    Inventors: Ellen Schwartz Tormey, Ashok Narayan Prabhu, Attiganal Narayanaswamy Sreeram, Michael James Liberatore
  • Patent number: 6043973
    Abstract: A ceramic capacitor having an improved electrode soldering performance, little or no diffusion of solder even in the case of being used under a high temperature environment and a reduced characteristic deterioration is provided. The dry plating electrodes have a three-layer structure. First layers of the electrodes are respectively provided on both surfaces of a ceramic element assembly and made of any one or more of Cu, Ni--Cu alloy and Zn. Second layers of the electrodes are respectively provided on the surfaces of the first layers and made of a material different from the material of the first layers and any one or more of Cr, Ni--Cr alloy, Fe--Cr alloy, Co--Cr alloy, Ti, Zn, Al, W, V and Mo. Third layers of the electrodes are respectively provided on the surfaces of the second layers and made of any one or more of Cu, Ni--Cu alloy, Ag and Au.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: March 28, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuru Nagashima, Kazuhiro Yoshida, Masanobu Kishi, Makoto Murata
  • Patent number: 6023407
    Abstract: An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: February 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mukta S. Farooq, Shaji Farooq, Harvey C. Hamel, John U. Knickerbocker, Robert A. Rita, Herbert I. Stoller
  • Patent number: 6002577
    Abstract: A monolithic ceramic capacitor has laminated plural dielectric ceramic layers, internal electrodes disposed between dielectric ceramic layers, and external electrodes formed at edge surfaces of the dielectric ceramic layers such that they are connected to alternate internal electrodes, wherein the dielectric ceramic layers are composed of a material comprising a principal component shown by the formula: (1-.alpha.-.beta.-.gamma.){BaO}.sub.m.TiO.sub.2 +.alpha.M.sub.2 O.sub.3 +.beta.Re.sub.2 O.sub.3 +.gamma.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)O (wherein M.sub.2 O.sub.3 is at least one kind of Sc.sub.2 O.sub.3 and Y.sub.2 O.sub.3 ; Re.sub.2 O.sub.3 is at least one kind of Sm.sub.2 O.sub.3 and Eu.sub.2 O.sub.3 ; 0.0025.ltoreq..alpha.+.beta..ltoreq.0.025, 0<.beta..ltoreq.0.0075, 0.0025.ltoreq..gamma..ltoreq.0.05, .gamma./(.alpha.+.beta.).ltoreq.4, 0.ltoreq.x<1.0, 0.ltoreq.y<1.0, 0.ltoreq.x+y.ltoreq.1.0, and 1.000<m.ltoreq.1,035), and containing definite amounts of MgO and SiO.sub.2 as side components.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: December 14, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroyuki Wada, Harunobu Sano
  • Patent number: 6002576
    Abstract: A trimming capacitor with less drop in Q due to laser trimming, wherein a non-reducing ceramic material which can be sintered either within a neutral atmosphere or a reducing atmosphere is used as the material of the ceramic dielectric. A trimming capacitor electrode is provided on the surface of or within a ceramic dielectric containing internal capacitor electrodes. Part of the trimming capacitor electrode is removed by a laser beam to reduce an area thereof facing the internal capacitor electrode, to adjust the electrostatic capacitance to a desired value. The use of non-reducing ceramic material reduces the amount of dielectric material that is converted to semiconductor material during laser trimming.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: December 14, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kyoshin Asakura, Yasunobu Yoneda
  • Patent number: 5955754
    Abstract: Metal alkoxycarboxylate-based liquid precursor solutions are used form electronic devices (100) that include mixed layered superlattice materials (112) of a type having discrete oxygen octahedral layers (124) and (128) collated with a superlattice-generator layer (116). The precursor solutions include a plurality of metal moieties in effective amounts for yielding the layered superlattice materials. These metal moieties are mixed to include an A/B portion capable of forming an A/B layer (124), a perovskite-like AB layer portion capable of forming a perovskite-like AB octahedral layer (128), and a superlattice-generator portion capable of forming the superlattice-generator layer (116). The precursors are deposited in liquid form upon a substrate and annealed to provide the layered superlattice materials.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: September 21, 1999
    Assignees: Symetrix Corporation, Matsushita Electronics Corporation
    Inventors: Masamichi Azuma, Carlos A. Paz De Araujo, Larry D. McMillan
  • Patent number: 5953203
    Abstract: Embedded capacitors are formed in multilayer ceramic circuit boards by screen printing a capacitor ink sandwiched between conductor ink layers onto a green tape stack and covering the ink layer with one or two green tapes, and aligning the green tape layers, and firing. The green tapes are made of a mixture of a crystallizing glass, a non-crystallizing glass and an oxide filler which do not shrink in the x and y dimensions during firing. Thus the capacitors can be made to close tolerances.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: September 14, 1999
    Assignees: Sarnoff Corporation, Sharp Corporation
    Inventors: Ellen Schwartz Tormey, Ashok Narayan Prabhu, Attiganal Narayanaswamy Sreeram
  • Patent number: 5923524
    Abstract: Applicant has discovered that the dielectric constant of Ta.sub.2 O.sub.5 can be significantly enhanced by the addition of small quantities of TiO.sub.2. Specifically, if Ta.sub.2 O.sub.5 is doped with more than about 3 mole percent of TiO.sub.2 the doped material will have a dielectric constant higher than the undoped material. For example, at a ratio of 0.92 Ta.sub.2 O.sub.5 :0.08TiO.sub.2, the dielectric constant is enhanced by a factor of more than three. Because both Ta and Ti are compatible with current microelectronics processing, the new dielectric can be used to make capacitors of reduced size with but minor modifications of conventional processes.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: July 13, 1999
    Assignee: Lucent Technologies Inc.
    Inventor: Robert Joseph Cava
  • Patent number: 5914851
    Abstract: A capacitor structure is provided, with a first conductor on top of a substrate, a first non-conductor on top of and substantially in register with the first conductor, the first conductor and first non-conductor having a first opening formed therein, a non-conductive sidewall spacer formed in the first opening, the non-conductive sidewall spacer having a second opening formed therein, and a second conductor formed in the second opening.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 22, 1999
    Assignee: International Business Machines Corporation
    Inventors: Katherine Lynn Saenger, James H. Comfort, Alfred Grill, David Edward Kotecki
  • Patent number: 5898562
    Abstract: An integral dual frequency by-pass device is of one or more ceramic dielectric layers, the opposed surfaces of which are formed with electrodes of generally U-shaped configuration. The base portions of the electrodes are exposed at opposite surfaces of the monolith, the leg portions of the U-shaped electrodes extending toward the base portions of electrodes of opposite polarity. The overlap or registration area of one pair of legs differs from the overlap area of the other leg pair with the result that two capacitors of different values are formed, the capacitors being in parallel and accordingly defining low impedance path at two discrete frequencies. By varying the conductive paths as a function of the length of the electrode and/or the base of the U, a desired internal inductance is be developed.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: April 27, 1999
    Assignee: AVX Corporation
    Inventors: Jeffery C. Cain, John E. Barris
  • Patent number: 5877934
    Abstract: A multilayer ceramic capacitor is made of a principal component (100 mol) represented by the compositional formula(1-.alpha.-.beta.) {BaO}.sub.m .multidot.TiO.sub.2 +.alpha.Re.sub.2 O.sub.3 +.beta.(Mn.sub.1-x-y Ni.sub.x CO.sub.y)O(where Re.sub.2 O.sub.3 is at least one of Y.sub.2 O.sub.3, Tb.sub.2 O.sub.3, Dy.sub.2 O.sub.3, Ho.sub.2 O.sub.3, Er.sub.2 O.sub.3 and Yb.sub.2 O.sub.3 ; and .alpha., .beta., m, x, and y are 0.0025 .ltoreq..alpha..ltoreq.0.025, 0.0025 .ltoreq..beta..ltoreq.0.05, .beta./.alpha..ltoreq.4, 0 .ltoreq.x <1.0, 0 .ltoreq.y <1.0, 0 .ltoreq.x +y<1.0, and 1.000<m.ltoreq.1.035.), a secondary component (about 1-3.0 mol) of magnesium oxide (MgO), and Al.sub.2 O.sub.3 -MO-B.sub.2 O.sub.3 oxide glass (where MO is at least one of BaO, CaO, SrO, MgO, ZnO and MnO) in an amount of about 0.2-3.0 parts by weight for 100 parts by weight of the total amount of said principal component and secondary component.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: March 2, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harunobu Sano, Kazuhiro Harada
  • Patent number: 5852542
    Abstract: A monolithic ceramic capacitor has dielectric ceramic layers of a material comprising barium titanate having alkali metal oxides impurities in an amount of not more than about 0.02% by weight, manganese oxide, cobalt oxide, and nickel oxide; from about 0.5 to 5.0 mols MgO to 100 mols of a main constituent shown by the following composition formula;(1-.alpha.-.beta.-.gamma.){BaO}.sub.m.TiO.sub.2 +.alpha.M.sub.2 O.sub.3 +.beta.Re.sub.2 O.sub.3 +.gamma.(Mn.sub.1-x-y Ni.sub.x Co.sub.y)Owherein M.sub.2 O.sub.3 is at least one of Sc.sub.2 O.sub.3 and Y.sub.2 O.sub.3 ; Re.sub.2 O.sub.3 is at least one of Sm.sub.2 O.sub.3 and Eu.sub.2 O.sub.3 and .alpha., .beta., .gamma., m, x, and y are0.0025.ltoreq..alpha.+.beta..ltoreq.0.0250.ltoreq..beta..ltoreq.0.00750.0025.ltoreq..gamma..ltoreq.0.05.gamma./(.alpha.+.beta.).ltoreq.40.ltoreq.x<1.00.ltoreq.y<1.00.ltoreq.x+y<1.01.000<m.ltoreq.1.035;an Li.sub.2 O--B.sub.2 O.sub.3 --(Si, Ti)O.sub.2 oxide glass in an amount of from about 0.2 to 3.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: December 22, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroyuki Wada, Harunobu Sano, Norihiko Sakamoto
  • Patent number: 5841626
    Abstract: A dielectric ceramic composition and a monolithic ceramic capacitor using same are provided. The dielectric ceramic composition includes a main component of barium titanate, scandium oxide, yttrium oxide, manganese oxide and nickel oxide, having the compositional formula:(1-.alpha.-.beta.){BaO}.sub.m.TiO.sub.2 +.alpha.M.sub.2 O.sub.3 +.beta.(Mn.sub.1-x Ni.sub.x)OwhereM.sub.2 O.sub.3 is at least one of Sc.sub.2 O.sub.3 and Y.sub.2 O.sub.3 ; 0.0025.ltoreq..alpha..ltoreq.0.020, 0.0025.ltoreq..beta..ltoreq.0.04, .beta./.alpha..ltoreq.4, 0.ltoreq.x<1.0, 1.000 <m.ltoreq.1.035, andmagnesium oxide in an amount of from about 0.5 to 3.0 mols in terms of MgO, and silicon oxide in an amount of from about 0.2 to 5.0 mols in terms of Si0.sub.2, relative to 100 mols of the main component.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: November 24, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Harunobu Sano, Hiroyuki Wada, Yukio Hamaji
  • Patent number: 5835340
    Abstract: A monolithic ceramic capacitor having a plurality of dielectric ceramic layers, internal electrodes, and external electrodes electrically connected to the internal electrode, wherein the dielectric ceramic layers comprise (a) barium titanate having an alkali metal oxide impurity content of not more than about 0.02% by weight, (b) scandium oxide and/or yttrium oxide, (c) gadolinium oxide, terbium oxide and/or dysprosium oxide, (d) manganese oxide, (e) cobalt oxide, and (f) nickel oxide, and is a material containing (1) 100 mols represented by the compositional formula:(1-.alpha.-.beta.){BaO}.sub.m .cndot.TiO.sub.2 +.alpha.{(1-x)M.sub.2 O.sub.3 +xRe.sub.2 O.sub.3 }+.beta.(Mn.sub.1-y-z Ni.sub.y Co.sub.z)Owherein M.sub.2 O.sub.3 represents the above-mentioned (b); Re.sub.2 O.sub.3 represents the above-mentioned (c); 0.0025.ltoreq..beta..ltoreq.0.05; .beta./.alpha..ltoreq.4; 0<x.ltoreq.0.50; 0.ltoreq.1.0; 0.ltoreq.z1.0; 0.ltoreq.y+z<1.0; and 1.000<m.ltoreq.1.035, (2) about 0.5 to 5.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: November 10, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroyuki Wada, Harunobu Sano, Norihiko Sakamoto
  • Patent number: 5822175
    Abstract: An encapsulated capacitor structure and method for fabricating same. The capacitor structure is created by selectively depositing a lower electrode, a dielectric thin film of BST or other ferrodielectric, and an upper electrode, onto a substrate, and subsequently depositing a conformal layer of a non-reductively deposited dielectric material. Contact windows are then opened through the encapsulating layer for contacting the capacitor electrodes. The underlying structure is protected by the encapsulating layer from metal deposition and post-processing which would otherwise damage the structure.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 13, 1998
    Assignee: Matsushita Electronics Corporation
    Inventor: Masamichi Azuma