Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and method for forming the same, comprising a plurality of divergent capacitors in a parallel circuit connection between first and second ports, the plurality comprising at least one Metal Oxide Silicon Capacitor and at least one capacitor selected from the group comprising a Vertical Native Capacitor and a Metal-Insulator-Metal Capacitor. In one aspect, the assembly has vertical orientation, the Metal Oxide Silicon capacitor located at the bottom and defining the footprint, middle Vertical Native Capacitor comprising a plurality of horizontal metal layers comprising a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, a vertically asymmetric orientation provides a reduced total parasitic capacitance.

Abstract: A capacitor includes two sub capacitors and two connecting portions. The two sub capacitors respectively include a lower electrode provided on a substrate, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film, and the two connecting portions respectively connecting the lower electrode of one of the two sub capacitors and the upper electrode of the other sub capacitor of the two sub capacitors.

Abstract: A capacitor array may include a bottom electrode, a plurality of top electrodes, at least one dielectric medium and a plurality of switching mechanisms. Each switching mechanism may separably electronically connect two or more top electrodes. The at least one dielectric medium may include a plurality of discrete capacitors each in contact with a top electrode and the bottom electrode.

Abstract: A novel multi-capacitor divider network in which two capacitors are fabricated in a single package, using a common dielectric material, is disclosed. In a preferred embodiment of the present invention, the multi-capacitor network comprises a high-voltage capacitor and a low-voltage capacitor fabricated in a single monolithic package, both fabricated from a class one dielectric material having a combined tolerance of plus or minus five percent. The use of the same class one dielectric material for both capacitors assures that the temperature coefficents are similar for both capacitors and, more importantly, that the tolerance of the ratio between the high-voltage capacitor and low-voltage capacitor is within a predetermined range.

Abstract: An orientation-insensitive ultra-wideband coupling capacitor. The orientation-insensitive ultra-wideband coupling capacitor includes a plurality of external surfaces, a low frequency portion, and a high frequency portion. The high frequency portion is so disposed on, and electrically connected to, the low frequency portion so as to allow the orientation-insensitive ultra-wideband coupling capacitor to work identically when mounted on any external longitudinal surface of the plurality of external surfaces thereof and thereby be readily SMT compatible without regard to special orienting procedures.

Abstract: A method of fabricating high resistivity thin film resistors. An isolation region is formed on a substrate to isolate the active regions. A polysilicon layer is formed above the substrate. A diffusion barrier layer is formed above the polysilicon layer. Lightly doped ions are implanted in the polysilicon layer. The substrate is annealed at a high temperature. The diffusion barrier layer and the polysilicon layer are patterned to form a high-resistive thin film resistor. Spacers are formed on the sidewalls of the high-resistive thin film resistor.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.

Abstract: A single layer capacitive device including a portion of pre-fired ceramic material and one or more terminations is formed with manufacturing steps that are easily modified to customize size and other aspects of such devices. The single layer devices may be utilized by themselves or selectively combined with MLCs to form integrated capacitor assemblies yielding many desirable performance characteristics in a monolithic assembly. An exemplary integrated capacitor assembly advantageously provides customized frequency response and capacitance in limited real estate. Predictable and generally constant or “flat” impedance versus frequency is afforded mainly by the properties of the single layer device, while higher capacitance is provided mainly from features of one or more associated MLCs. High structural integrity of exemplary integrated capacitor assemblies is achieved due to the disclosed attachment methods.

Abstract: This invention describes a means by which performance characteristics of capacitors can be improved. This is achieved by reducing the temperature, preferably but not exclusively to cryogenic temperatures below 100 K. This is based on the observation that the dielectric strength, dielectric losses and plate losses in many capacitors, such as film capacitors, improve as the temperature is decreased. A cryogenic capacitor bank is also described, which exhibits energy densities up to four times those of conventional, room-temperature capacitor banks. Cryogenic capacitors can be combined with cryogenically operated semiconductors or with superconductors in such a way as to reduce the size, weight, and losses of a complete system.

Abstract: A high pressure condenser for a magnetron, in which a pair of dielectric ceramics having an arch shape are separated from each other, central conductors are connected to internal peripheries of the dielectric ceramics, and a ground metal is connected to external peripheries of the dielectric ceramics, thereby not requiring any additional structure for connecting the dielectric ceramics and the central conductors, simplifying the structures of the central conductors, and reducing the quantity of the dielectric ceramics needed in proportion to the separation interval between the dielectric ceramics.

Abstract: A capacitor element on a chip, e.g., a MMIC chip, includes a main capacitor in parallel with a series configuration of trimming capacitors. The total capacitance value of the parallel arrangement can be increased from its inherently minimum value by applying one or more laser pulses to one or more of the trimming capacitors, such that in each case a short-circuit is produced between the metallization layer to which the pulses are applied and the other metallization layer making up the trimming capacitor.

Abstract: In a device for removing inverter noise, a pair of bus bars extending in parallel are grounded via a pair of capacitors. The capacitors are connected to the bus bars and to a grounding terminal at positions symmetrical to the pair of bus bars. Therefore, the inductance components are balanced from the source of noise to the grounded point, and impedance components are decreased from the two bus bars to a point grounded through the capacitors, making it possible to effectively remove high-frequency noise on the DC bus line of the inverter without requiring a large amount of space.

Abstract: A set of integrated capacitor arrangements is presented, each of which has a circuitry-effective main capacitor and a connectable correction capacitor. Each capacitor arrangement has an electrically conductive antifuse connection and antifuse interruption between the correction capacitor and the main capacitor, which are produced after the main capacitor has been formed. The connection and interruption enable the capacitance of the capacitor arrangement to be corrected.

Abstract: Integrated passive component assemblies utilize array shell or array frame receiving structures to isolate and protect discrete passive components and provide a modular configuration for mounting to a substrate. Receiving structure embodiments include a base portion, spacer ribs, and optional side walls. Spacer ribs may be connected or provided in opposing spacer rib portions to effectively isolate adjacent component terminations. Standoff features may be incorporated into select embodiments of the disclosed technology to aid in device mounting and to facilitate post-affixment cleaning and visual termination contact. Discrete passive components in accordance with the present subject matter may include select combinations of resistors, capacitors, inductors, and other suitable devices.

Abstract: An ultracapacitor formed on a semiconductor substrate includes a plurality conductive layers with intervening dielectric layers. These layers form a plurality of capacitors which may be connected in parallel to store a charge for powering an electronic circuit or for performing a variety of integrated circuit applications. A plurality of ultracapacitors of this type may be connected in series or may be designed in stacked configuration for attaining a specific charge distribution profile.

Abstract: A high voltage sign ballast capacitor assembly is disclosed. The assembly includes two components for the sign ballast operation, namely a main capacitor element for power factor correction and up to six starting capacitors for aiding in starting under cold weather conditions. The main capacitor element is arranged and configured to divide the necessary capacitance into several capacitors connected in series. By doing so, the voltage is divided across each of the series capacitors resulting in reduced voltage stress and a reduction in the risk of corona arcing. The assembly is preferably constructed as a modular printed circuit board and a sleeve that houses the circuit board. The circuit board allows for the incorporation of multiple lead configurations, multiple start capacitors, and bleed resistors.

Abstract: In the direct current cut structure of the present invention, two capacitors are provided in parallel between signal transmission line patterns facing each other on a substrate, and each of the two capacitors is electrically connected to each surface of each transmission line pattern that is exposed through a hole part provided on the substrate. It is preferable for the two capacitors to have different capacity. If there is no need to cover such a broad band, only one capacitor can also connected to either side of each transmission line pattern exposed through the hole part.

Abstract: A C-shaped combination capacitor assembly has a C-shaped shell, multiple capacitors, two conducting wires, two lead wires and encapsulant. The capacitors are mounted in the C-shaped shell. The conducting wires connect the capacitors in parallel. The two lead wires connect respectively to the conducting wires and protrude from the C-shaped shell. The encapsulant fills the C-shaped shell and covers and seals the capacitors, the conducting wires and the lead wires inside the C-shaped shell.

Abstract: An energy conditioning structure comprised of any combination of multilayer or monolithic energy conditioners with operable conductors, all selectively arranged and shielded for attachment to at least a conductive substrate.

Abstract: The present invention is directed to a high-voltage capacitor, high-voltage capacitor device and magnetron in which, undesirable radiation waves generated in the frequency range of 450 MHz to 1000 MHz in a magnetron are suppressed to such a level that there is no adverse effect on the peripheral devices. The dielectric porcelain comprises a body 210 and through holes 211, 212. The body 210 includes a portion (216, 217) that is narrowed on both sides in the middle of the body in the plan view. The through holes 211, 212 are formed in the body, arranged at a distance from each other over the narrowed portion (216, 217). One individual electrode 213 is provided on the surface of the body 210 at which the through hole 211 opens. The other individual electrode 214 is provided on the surface of the body 210 at which the through hole 212 opens. The common electrode 215 is provided on another surface of the body 210 at which the through holes 211, 212 open.

Abstract: A structure and method for manufacturing multi-electrode capacitor within a PCB is used to form a multi-electrode capacitor with a plurality of metal laminates coupled each other and employing the characteristics of the edge-coupled effect therein. the present invention can provide efficient capacitance from the capacitor with the smallest area. The present invention is applied to promote the capability of noise-restraint of the capacitive substrate in a high-frequency/speed system, and further achieves the purpose of regular circuit design with the smallest area in the future development.

Abstract: A storage capacitor includes at least one first electrode adjacent to at least one second electrode, whereby a lateral capacity is formed between these electrodes. The electrodes include stacks of metal parts and connecting contact elements. The second electrodes can be arranged around the first electrodes, and at least some of the second electrodes can be used jointly with adjacent ones of the first electrodes to form adjacent storage capacitors.

Abstract: A capacitor assembly is formed from one or more capacitive elements placed between a pair of opposing brackets. Each bracket has at least one L-shaped section and an arcuate section. Each L-shaped section has a capacitor seating surface and an assembly connecting surface that is substantially perpendicular to the capacitor seating surface. The arcuate section is adjacent to the capacitor seating surface. The opposing ends of each capacitive element is in electrically contact with the capacitor seating surfaces on the opposing brackets. When secured to a bus bar by fasteners located in the regions formed by the arcuate sections of the opposing brackets the assembly connection surfaces serve as electrical and thermal conducting regions between the capacitor assembly and the bus bars. Alternatively a capacitor assembly may be secured to bus bars by fastening to the capacitor seating surfaces.

Abstract: A system for electronically actuating valves in an engine. The system includes first and second voltage sources, and a plurality of valve actuator subsystems coupled therebetween. Each valve actuator subsystem has a valve actuator and a switch configured to selectively control application of voltage to the valve actuator to thereby selectively control energization of the valve actuator. The system also includes a dissipation switch operatively coupled with the valve actuator subsystems, the dissipation switch being selectively operable to control dissipation of energy from any of the valve actuators.

Abstract: Systems and apparatuses for providing a broadband capacitor assembly. One broadband capacitor assembly includes a first capacitor operable to provide a first end of an operational band of frequencies within an operational band of a broadband capacitor assembly. The broadband capacitor assembly also includes a second capacitor coupled in parallel to the first capacitor, the second capacitor operable to provide a second end of the operational band of frequencies within the operational band of the broadband capacitor assembly. A DC block can be provided including a broadband capacitor assembly.

Abstract: A high density capacitor filter bank for use in connection with printed circuit boards is provided. Capacitive elements are disposed within a conductive shield such that the capacitive elements are substantially orthogonal to the plane of the printed circuit board, and such that they can interconnect with corresponding contacts on the printed circuit board while occupying a minimal amount of surface area on the printed circuit board. The conductive shield may comprise a Faraday shield.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of a material which has conductivity and on which a dielectric material containing a bismuth layer structured compound can be epitaxially grown, at least the surface thereof being oriented in the [001] direction, and a dielectric layer formed by epitaxially growing a dielectric material containing a bismuth layer structured compound on the support substrate and formed of a dielectric material containing a bismuth layer structured compound oriented in the [001] direction.

Abstract: An electromagnetic gun and rotating pulsed network system that includes a gun barrel coupled to a gun mount coupled on a rotating platform on one deck of a naval ship. A pulse forming network which is generally cylindrical in shape provides pulsed energy to the electromagnetic gun and is rotatable within a cylindrical bulkhead located on a lower deck of the ship. The pulse forming network rotates in unison with the gun barrel on the same axis, allowing unbroken cables to couple the pulse forming network to the gun. The pulse forming network includes wedge-shaped capacitor modules that, when juxtaposed, collectively form a substantially annular shape having generally cylindrical inner and outer surfaces.

Abstract: Structures are provided for implementing an integrated conductor and capacitor in a surface mounted device (SMD) package. A first pair and a second pair of contacts contained within the SMD package respectively are provided in mating engagement with a first pair and a second pair of corresponding SMD package contacts. A conductor extends between the first pair of contacts, contained within the SMD package. A capacitor is defined between the second pair of contacts, contained within the SMD package. An additional one or pair of integral capacitors optionally is provided for providing additional capacitance to ground to decouple common mode noise from the power planes.

Abstract: A capacitor mounting structure has four capacitors close-arranged so that the outline of the arrangement is almost rectangular. The capacitors are arranged so that an angle formed by the current vectors of each pair of adjacent capacitors is 90 degrees and that one end face in the length direction of each capacitor is directed in parallel to an inner side face of another adjacent capacitor.

Abstract: A transmission line capacitor includes at least two side-by-side capacitor portions spaced apart between a separating portion all contained in a single monolithic body. Such transmission line capacitors provide specific capacitor functionality for parallel transmission lines in a printed circuit board environment, while also maintaining a desired impedance value between the transmission paths. The transmission line capacitors offer both biasing functionality for blocking undesired DC voltages as well as AC coupling functionality for passing AC voltage signals with preserved data integrity. A first embodiment may be formed with a dielectric material having a relatively low dielectric constant, allowing high capacitor “height” with fixed spacing between distinct capacitive structures. Another embodiment may be formed with a relative high K dielectric and then slotted with an air gap between capacitive structures.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of a silicon single crystal, a barrier layer formed on the support substrate of silicon oxide, an electrode layer formed on the barrier layer of platinum, a buffer layer formed on the electrode layer of a dielectric material containing a bismuth layer structured compound having a composition represented by Bi4Ti3O12, having an excellent orientation characteristic and oriented in the c axis direction, and a dielectric layer formed on the buffer layer of a dielectric material containing a bismuth layer structured compound having a composition represented by Bi4Ti3O12, having an excellent capacitor characteristic and oriented in the c axis direction.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of a silicon single crystal, a barrier layer formed of silicon oxide on the support substrate, an electrode layer, which is formed of BSCCO (bismuth strontium calcium copper oxide) having a stoichiometric composition represented by Bi2Sr2CaCu2O8, having an anisotropic property and conductivity and enabling epitaxial growth of a dielectric material containing a bismuth layer structured compound thereon and is oriented in the c axis direction, and a dielectric layer formed by epitaxially growing a dielectric material containing a bismuth layer structured compound having a composition represented by SrBi4Ti4O15 on the electrode layer and oriented in the c axis direction on the electrode layer.

Abstract: A semiconductor capacitor device has two pairs of first and second MIM capacitors on a semiconductor substrate. The paired first and second MIM capacitors include respective capacitor dielectric films having different compositions. Also, the paired first and second MIM capacitors are connected in inverse parallel fashion, with an upper electrode of the first MIM capacitor being connected with a lower electrode of the second MIM capacitor and with a lower electrode of the first MIM capacitor being connected with an upper electrode of the second MIM capacitor. Furthermore, the two first MIM capacitors are electrically connected in inverse parallel with each other, and the two second MIM capacitors are also electrically connected in inverse parallel with each other. This arrangement facilitates mutual counteraction of the voltage dependences of the two pairs of first and second MIM capacitors so as to make the voltage dependence of the capacitance of the capacitor device small.

Abstract: In a structure of a radio frequency (RF) variable capacitor having a variable range of capacitance between a first minimum value and a first maximum value, and a method of manufacturing the structure, the structure includes a first capacitor, which has a variable range of capacitance between a second minimum value greater than the first minimum value and a second maximum value greater than the first maximum value, and a second capacitor, which is connected in series to the first capacitor and has a capacitance of a fixed value. By the structure and method, a quality factor of a radio frequency (RF) variable capacitor may be increased without adding complex processing steps.

Abstract: A capacitor sheet comprises a plurality of first capacitor blocks connecting signal/power supply electrodes of two circuit boards with through-hole electrodes, and having grounding electrodes sandwiching dielectrics around the through-hole electrodes, and a plurality of second capacitor blocks connecting the grounding electrodes in two circuit boards with the through-hole electrodes, and having the grounding electrodes sandwiching the dielectrics around the through-hole electrodes, wherein the through-hole electrodes and the grounding electrodes are connected with pattern wirings. The capacitor blocks are arranged so that the grounding electrodes in the first capacitor blocks are electrically connected to the grounding electrodes of the second capacitor blocks to be combined to a single piece.

Abstract: Metal-insulator-metal integrated circuit capacitors include a pair of metal-insulator-metal capacitors on an integrated circuit substrate that are electronically connected in antiparallel. The pair of metal-insulator-metal capacitors that are electrically connected in antiparallel has less capacitance variation as a function of voltage than either of the metal-insulator-metal capacitors.

Abstract: The invention may be embodied in an electromagnetic filter for use with a feedthrough conductor. An inductor having a metallized surface is disposed about the conductor, and a capacitor is joined to the inductor. One set of capacitor plates are electrically connected to a first conductive contact to provide a connection to the metallized surface. Another set of capacitor plates are electrically connected to a second conductive contact to provide a connection to the feedthrough conductor. A method of providing such a filter is also disclosed.

Abstract: Systems and apparatuses for providing a broadband capacitor assembly. One broadband capacitor assembly includes a first capacitor operable to provide a first end of an operational band of frequencies within an operational band of a broadband capacitor assembly. The broadband capacitor assembly also includes a second capacitor coupled in parallel to the first capacitor, the second capacitor operable to provide a second end of the operational band of frequencies within the operational band of the broadband capacitor assembly. A DC block can be provided including a broadband capacitor assembly.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region.

Abstract: In a differential pressure sensor, the measurement value is corrected with the help of the nominal pressure NP. In this way, influences on the measurement value because of deformations of the body of the differential pressure sensor and change in the material stiffness of the membrane are decreased.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: Methods of and systems providing high reliability relative humidity sensors having integrated signal conditioning are described, providing a series capacitive circuit including a humidity-sensitive dielectric, a common top plate and first and second bottom plates associated with a first and second capacitor, respectively. Changes in humidity affect the humidity-sensitive dielectric thereby causing changes in the capacitive value of said series capacitive circuit.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: The present invention concerns the field of solid state capacitors and relates particularly to massed production methods for manufacturing solid state capacitors.

Abstract: A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of capacitors without phase conflict when using phase shift masks in an optical lithography fabrication process.

Abstract: A mobile telephone device fitted with a transmitter and a receiver each having a high-frequency component with an integrated decoupling capacitor. The high-frequency component includes a substrate with the decoupling capacitor on one surface thereof, first and second current supply terminals for the capacitor on the same surface of the substrate as the capacitor, one capacitor electrode connected to a high frequency circuit and a DC voltage source, also on the one surface of the substrate, and the other capacitor electrode connected to ground.