Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A packaged integrated circuit device and a circuit board assembly are disclosed that include a semiconductor die and a package substrate that includes a first grid array of contact pads that are electrically coupled to corresponding contact pads on the semiconductor die. The first grid array of contact pads includes a first set of adjacent rows or columns of contact pads that are coupled to a first channel that extends within a ground plane of the package substrate. The first grid array of contact pads includes a second set of adjacent rows or columns of contact pads that are electrically coupled to a second channel that extends within a power plane of the package substrate. The contact pads in the first set of adjacent rows or columns of contact pads directly overlie a portion of the first channel and the contact pads in the second set of adjacent rows or columns of contact pads directly overlie a portion of the second channel.

Abstract: An electric device includes: a first electric element; a second electric element capable of flowing large current therethrough so that heat is generated in the second electric element; a heat sink; and a first wiring board and a second wiring board, which are disposed on one side of the heat sink. The large current in the second electric element is larger than that in the first electric element. The first wiring board and the second wiring board are separated each other. The first electric element is disposed on the first wiring board, and the second electric element is disposed on the second wiring board.

Abstract: Provided herein are devices comprising a printed wiring board that comprise, singulated capacitors fabricated from known good, thin-film, fired-on-foil capacitors. Provided are methods of incorporating the singulated capacitors into the build-up layers of a printed wiring board to minimize impedance. The singulated capacitors have a pitch that allows each power and ground terminal of an IC to be directly connected to a power and ground electrode, respectively, of its own singulated capacitor. Using a feedstock of known good, fired-on-foil capacitors allows for improved PWB yield.

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

Abstract: The present invention provides a circuit board structure having an embedded capacitor and a method for fabricating the same. The circuit board structure includes a core layer board with at least one surface having non-penetrating first and second grooves, a circuit layer and a first electrode plate formed in the first and second grooves of the core layer board respectively and being flush with the core layer board; a high dielectric material layer formed on the core layer board, the circuit layer and the first electrode plate; a second electrode plate formed on the high dielectric material layer and corresponding to the first electrode plate, thereby forming a capacitor by the first and second electrode plates and the high dielectric material layer. The high dielectric material layer is formed on a plane surface so as to eliminate poor filling and improve reliability.

Abstract: A circuit board structure with an embedded semiconductor element and a fabrication method thereof are disclosed according to the present invention. The circuit board structure comprises: a carrier board having a first surface, a second surface, and at least one through hole penetrating the carrier board from the first surface to the second surface; a first semiconductor element received in the through hole and having an active surface and an inactive surface, the active surface having a plurality of electrode pads; at least one second semiconductor element mounted on the carrier board; a first encapsulation layer formed on the first surface of the carrier board to block one end of the through hole; and a second encapsulation layer formed on the second surface of the carrier board.

Abstract: In a multilayer ceramic electronic component, a ceramic laminate is defined by a ceramic base layer and ceramic auxiliary layers arranged on both main surfaces of the ceramic base layer, the ceramic base layer and the ceramic auxiliary layers being co-fired. The ceramic base layer and the ceramic auxiliary layers are made of ferrite materials having substantially the same compositional system and have substantially the same crystal structure. The linear expansion coefficient of the ceramic auxiliary layers is less than the linear expansion coefficient of the ceramic base layer.

Abstract: An interconnect module and a method of manufacturing the same. The method of making an interconnect module on a substrate comprises forming an interconnect section on the substrate. The interconnect section comprises at least two metal interconnect layers separated by a dielectric layer. The method further comprises forming a passive device on the substrate at a location laterally adjacent to the interconnect section. The passive device comprises at least one moveable element comprising a metal layer. The method further comprises forming the metal layer and one of the at least two metal interconnect layers from substantially the same material.

Abstract: A multilayered substrate includes a plurality of circuit boards including a plurality of wiring layers including a grounding layer and a power layer, a solid electrolytic capacitor having an insulative oxide film layer, an electrolytic layer, and a conductor layer sequentially formed on one surface or both surfaces of a foil-like metal substrate, and a conductive substance passing through the circuit board across a thickness thereof. The solid electrolytic capacitor is disposed to be held between the plurality of circuit boards. The conductor layer is connected to a grounding electrode formed on the grounding layer, the foil-like metal substrate being connected to a power electrode formed on the power layer.

Abstract: Systems, methods and apparatuses for low noise power distribution networks for use with semiconductor devices are disclosed. Embodiments of these systems and methods provide a power distribution network comprising a set of individual power distribution networks, each of the individual power distribution networks operable to provide power to a corresponding functional block of the semiconductor device. These individual power distribution networks may be coupled through capacitors between the power supplies or grounds of each individual power distribution network, such that the individual power distribution networks are coupled in a manner operable to pass AC current between them.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode; a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0.

Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.

Abstract: A wiring board having an excellent electrical property and reliability or the like. The wiring board includes a core board, a capacitor and a resin filler. The core board includes an accommodation hole therein and a core board main surface side conductor disposed on the core main surface thereof. A capacitor main surface side electrode is disposed on a capacitor main surface of the capacitor. A gap between the capacitor accommodated in the accommodation hole and the core board is filled with the resin filler so that the capacitor is fixed to the core board. Further, the resin filler has a main surface side wiring forming portion on which a main surface side connecting conductor, which is connected to an end portion of a via conductor, is disposed so as to connect the core board main surface side conductor to the capacitor main surface side electrode.

Abstract: A microelectronic substrate, a method of forming the same, and a system including the same. The microelectronic substrate comprises: a conductive layer; a spacer layer disposed onto the conductive dielectric layer; a dielectric build-up layer disposed onto the spacer layer, the spacer layer being made of a material that has a lower shrinkage than a material of the embedding dielectric-build-up layer during curing, and a higher viscosity than a material of the embedding dielectric build-up layer in its pre-cure form and during curing; and active or passive microelectronic components embedded within the dielectric build-up layer.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: A method and system for placing multiple loads in a high-speed system are disclosed. In one embodiment, the first load and the second load are placed on the first side and the second side of the printed circuit board, respectively. In addition, the first signal pin of the first load is vertically aligned with the second signal pin of the second load with an offset; the terminating end of a trace, which is connected to a driver on the printed circuit board, the first signal pin, and the second signal pin are connected at a T-point. The printed circuit also includes the first decoupling capacitor on the second side and the second decoupling capacitor on the first side. The first decoupling capacitor is connected to the first power pin of the first load. Similarly, the second decoupling capacitor is connected to a second power pin of the second load.

Abstract: There is provided a memory module that facilitates meeting the needs of high-speed performance and large capacity. It comprises first module substrates (101 through 108), each with multiple DRAM devices (11), and a second module substrate whereon the first modules (101 through 108) are mounted, signal line groups connected to the multiple first modules respectively are provided in parallel, and a controller LSI (50), connected to the multiple first modules respectively via the signal line groups provided in parallel, that converts the signal lines into fewer signal lines than the total number of the signal line groups and outputs the result is provided, and the second module substrate (20) is mounted on a motherboard (40).

Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.

Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Abstract: A pre-drilled hole, providing a passageway between an upper and a lower surface of a printed circuit board layer, receives a passive component, for example a resistor or a capacitor. In one embodiment the component is cylindrical, with an electrically conductive contact point at each end. The hole diameter is approximately the same as the diameter of the cylindrical component. The hole is similar to a via in a printed circuit board, except that the hole is not plated through (such would cause an electrical short). Electrically conductive lines are provided to the openings of the hole on the upper and the lower surfaces of the PCB. The area of the exposed end of the cylindrical component and the termination of the conducting line is less than the area of a surface mounted component equivalent to the cylindrical component.

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 ?m to about 20 ?m. The insulative layer has a substantially constant thickness.

Abstract: A printed circuit board assembly includes: a substrate; a main signal line formed on the substrate to transmit a signal; an SMD mounted on the substrate; a pad interposed between the SMD and the substrate; and a sub signal line provided on the substrate to electrically connect the main signal line with the pad, and having a width different from that of the main signal line. Thus, the printed circuit board assembly transmits a signal at a high speed and enhancing reliability and an economical efficiency of a product using the printed circuit board assembly.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: The present invention relates to a power core comprising: at least one embedded surface mount technology (SMT) discrete chip capacitor layer comprising at least one embedded SMT discrete chip capacitor; and at least one planar capacitor laminate; wherein at least one planar capacitor laminate serves as a low inductance path to supply a charge to at least one embedded SMT discrete chip capacitor; and wherein said embedded SMT discrete chip capacitor is connected in parallel to said planar capacitor laminate.

Abstract: A front end module includes a multilayered structure. The multilayered structure includes a transmitter, a receiver, and a duplex unit. The multilayered structure further includes a ground layer. The ground layer includes a ground pattern having at least one block on a surface of a substrate of the front end module.

Abstract: Electronic circuit device (100) is structured so that a substrate module unit that are formed by stacking substrate modules made of a first resin sheet with electronic component (190) embedded thereinto is inserted into housing (150) including connecting terminal (120), control circuit (130), and first wiring pattern (140), where the substrate modules are connected to each other electrically and mechanically. This electronic circuit device (100) dispenses with a mother substrate. Further, with slimming down of a substrate module, a substrate module unit with a large number of substrate modules stacked can be loaded in a limited packaging space, thus mounting greater storage capacity and higher functionality.

Abstract: A motherboard for a portable notebook computer includes a circuit board, and an extension card module connected with the circuit board. The circuit board defines a cutout in one corner thereof and includes a top layer and a bottom layer. The top layer includes a first area, a second area, a third area, and a fourth area. The first area and the third area are located near one edge of the circuit board. The second area and the fourth area are located near an opposite edge of the circuit board. The first area and the second area are near the cutout. A central processing unit, a graphics processing unit (GPU), a peripheral component interconnect (PCI) card, and a memory are located on the first through fourth areas of the circuit board respectively. The extension card module selectively receives a variety of extension cards.

Abstract: A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates.

Abstract: A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.

Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

Abstract: A method of forming a circuit board, the method comprising mounting at least one passive component on a first surface of a first laminate material; interconnecting the passive component to contact traces and vias of the first laminate material; and attaching a second laminate material to the first surface of the first laminate material utilizing a lamination process, the second laminate material sheet having at least one of a recess, a through-hole or both formed therein for accommodating the passive component in the second laminate.

Abstract: This invention provides a small package board integrated with power supply capable of supplying a low level of voltage and high level of current to an IC while achieving a low height of its power supply. It becomes hard to saturate an inductor magnetically when the surface of a copper wire is coated with a magnetic layer, and the inductor can accordingly be provided with a sufficient degree of inductance. A multiplicity of inductors can be provided within a confined space by arranging a multiplicity of inductors in parallel, and by fixing them with resin so as to form an inductor array, thereby making it possible to divide a power supply. The number of power supply lines is increased by dividing the power supply so as to reduce the level of current in an individual power supply line, so that a high level of current can be supplied to an IC chip.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.

Abstract: The embedded capacitor of the present invention contains a power plate, a ground plate, and a dielectric layer vertically sandwiched between the power and ground plates. Both the power and ground plates are divided laterally into a number of smaller plates with appropriate gaps therebetween; and, as such, cracks in the dielectric layers are limited to happen between gaps only. The smaller plates are then electrically connected by connectors in the gaps. The connectors for the power plate and the connectors for the ground plate are not vertically overlapped so that they do not appear simultaneously at the two ends of the cracks simultaneously.

Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.

Abstract: Using die side capacitors and embedded resistors, an advantageous power delivery network may be achieved. In some embodiments, the embedded resistors may be more precisely controllable. The number of die side capacitors may be reduced by combining embedded resistors with these capacitors to reduce costs. The embedded resistors may be provided within the metallization layers either at an upper layer or a lower layer, as two examples.

Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.

Abstract: An assembly integrating commercially available capacitors into filtered feedthroughs. A feedthrough assembly comprises a plurality of Input/Output (I/O) conductors, wherein the I/O conductors pass through a hermetic seal such that a first end of the I/O conductors reside on a non-hermetic side of the hermetic seal and a second end of the I/O conductors reside on a hermetic side of the hermetic seal, a printed circuit interconnect substrate residing on the hermetic side of the hermetic seal, and a plurality of ceramic chip capacitors mounted on the printed circuit interconnect substrate, wherein a first end of each capacitor is connected via the interconnect to the second end of an I/O conductor and a second end of each capacitor is connected via the interconnect to a constant voltage level.

Abstract: An apparatus is disclosed for a module structure of a mobile communication terminal. The module structure comprises a radio frequency portion for processing communicated radio frequency signals, and a base-band portion commonly used by the radio frequency portion for providing modular replacement of a radio frequency multi-chip module connected to the radio frequency portion. The radio frequency multi-chip module is selected in accordance with a corresponding frequency band of the mobile communication terminal.

Abstract: A printed circuit board having embedded electronic components and a manufacturing method thereof are disclosed.

Abstract: A wiring board comprising: a core board including a core body and a ceramic sub-core which is accommodated in a sub-core accommodation space that is a through-hole that communicates with major surfaces of the core body or a recess having an opening in a first major surface of the core body; and wiring laminates each formed by resin insulating layers and conductor layers laminated on each of major surfaces of the core board, wherein: a groove-filling portion which fills a gap between the core body and the ceramic sub-core is integral with a lowest resin insulating layer of the first-major-surface-side wiring laminate; and via conductors that are connected to respective conductor patterns formed on a first major surface of the ceramic sub-core penetrate through the lowest resin insulating layer.

Abstract: A multilayered electronic component that is easy to manufacture and that has excellent electrical characteristics includes end portions of coil wiring patterns that oppose a coil connection electrode that is displaced on the surface of a second ceramic layer due to an increase or decrease in the number of first ceramic layers. A coil connection electrode has a shape in which surface portions of second ceramic layers or opposed second ceramic layers having the first ceramic layers disposed in between are connected to the end portions of the coil wiring patterns that oppose the respective coil connection electrode, which are displaced due to the increase or decrease in the number of the first ceramic layers. A connection wiring pattern has a shape in which one portion of a coil connection electrode is connected to one portion of an external extension electrode connection pattern.

Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract: A method of manufacturing a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board manufactured by the method of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon.

Abstract: A circuit structure is provided. The circuit structure includes a capacitor including a top capacitor electrode; a bottom capacitor electrode parallel to the top capacitor electrode; and an insulating layer between the top and the bottom capacitor electrodes. The insulating layer includes a dielectric rod enclosed by a dielectric material. The dielectric rod has a higher dielectric constant than that of the dielectric material. The circuit structure may be a printed circuit board or packaging substrate, wherein the capacitor is formed between the two layers of the capacitor. Additional dielectric rods may be formed in the insulating layer of the capacitor and spaced apart from the dielectric rods.