Capacitor And Electrical Component Patents (Class 361/763)
  • Patent number: 8184448
    Abstract: A PCB having an embedded bare chip includes an insulated substrate having a penetration hole formed therein; a filler filling up an inside of the penetration hole; a bare chip embedded in the filler such that electrode pads formed on one side thereof are exposed at the surface of the filler; and an electrode bump attached to a surface of the electrode pads and protruded to be exposed to the outside.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: May 22, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung-Jin Han, Hyung-Tae Kim, Moon-Il Kim, Jae-Kul Lee, Doo-Hwan Lee
  • Patent number: 8183465
    Abstract: A component built-in wiring substrate (10) which includes: a core substrate (11); a plate-shaped component (101); a resin filling portion (92); and a wiring stacking portion (31), wherein, when viewed from the core principal surface (12) side, the projected area of the mounting area (32) is larger than the projected area of the plate-shaped component (101) and the resin filling portion, and the plate-shaped component and the resin filling portion are positioned directly below the mounting area (23), and wherein a value of the coefficient of thermal expansion (CTE ?2) for a temperature range that is equal to or higher than the glass transition temperature of the resin filling portion is set to be larger than a value of the coefficient of thermal expansion of the plate-shaped component and smaller than a value of the coefficient of thermal expansion of the core substrate for the subject temperature range.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: May 22, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shinya Suzuki, Kenichi Saita, Shinya Miyamoto, Shinji Yuri
  • Patent number: 8179687
    Abstract: A signal transmission device is installed on a motherboard and is electrically connected to a signal control unit and a display output interface. The signal transmission device includes a signal receiving port, a signal output port, and a printed circuit connecting port. The signal receiving port is used for receiving a signal transmitted from the signal control unit. The signal output port is used for single output of the signal to the display output interface. The printed circuit connecting port is used for transmitting the signal from the signal receiving port to the signal output port. Thus, the signal transmission device may be used for single signal output so as to replace a switch integrated circuit of selective signal output. In such a manner, related circuit redesign and manufacturing cost may be reduced accordingly when the motherboard signal output design is changed from selective signal output to single signal output.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: May 15, 2012
    Assignee: Elitegroup Computer Systems Co., Ltd.
    Inventor: Hsin-Meng Kuo
  • Patent number: 8179689
    Abstract: A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: May 15, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Naohiro Mashino
  • Patent number: 8174840
    Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 8, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Chang-Sheng Chen, Chin-Sun Shyu, Min-Lin Lee, Shinn-Juh Lay, Ying-Jiunn Lai
  • Patent number: 8169791
    Abstract: Electronic module (10), and an electric motor (12) containing one, and also a production method for one, having an electrically conductive first substrate (16) which has a basic body (54) and which has a second electrically conductive substrate (18) mounted on it, and having at least one power component which is arranged on a first substrate (16), and the second substrate (18) is fitted with further components (40) on a side (32) which is remote from the first substrate (16), where the second substrate (18) has a smaller base area (19) than the basic body (54) of the first substrate (16), and the power components (22) are mounted on the first substrate (16) outside the outer perimeter (70) of the second substrate (18)—next to the latter.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: May 1, 2012
    Assignee: Robert Bosch GmbH
    Inventors: Kuno Wolf, Thomas Koester, Stefan Hornung, Wolfgang Feiler
  • Patent number: 8169792
    Abstract: A multilayer printed wiring board includes: a build-up layer that is formed on a core substrate and has a conductor pattern disposed on an upper surface; a low elastic modulus layer that is formed on the build-up layer; lands that are disposed on an upper surface of the low elastic modulus layer and connected via solder bumps to a IC chip; and conductor posts that pass through the low elastic modulus layer and electrically connect lands with conductor patterns. The conductor posts have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts, which are positioned at external portions of the low elastic modulus layer, is greater than or equal to the aspect ratio Rasp of internal conductor posts, which are positioned at internal portions of the low elastic modulus layer.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: May 1, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani
  • Patent number: 8164917
    Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, Nyles Nettleton, Bruce M. Guenin
  • Publication number: 20120092843
    Abstract: In order to keep impedance characteristics to desired values across the entire operating frequency band, an electronic circuit of the present invention includes an integrated circuit, a decoupling capacitor, and a multilayer circuit board on which the integrated circuit and the decoupling capacitor are mounted. In the electronic circuit, a planar land is formed on one or both of a power layer and a ground layer of the multilayer circuit board, the land having densely disposed therein a plurality of via holes that connect a terminal of the integrated circuit and a corresponding terminal of the decoupling capacitor, and the land formed on the power layer or the ground layer is discontinuously disposed at a predetermined interval with a gap having a predetermined width provided therebetween.
    Type: Application
    Filed: October 13, 2011
    Publication date: April 19, 2012
    Applicant: Panasonic Corporation
    Inventors: Naofumi KITANO, Toshiro NISHIMURA
  • Publication number: 20120087097
    Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.
    Type: Application
    Filed: December 17, 2010
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Suk Chang HONG, Bong Kyu CHOI, Je Gwang Yoo, Sang Wuk JUN, Sang Kab PARK, Jung Soo Byun
  • Patent number: 8149589
    Abstract: A holder for mounting multiple capacitors onto a circuit board includes a main structure and a plurality of latching member. The main structure has a top plate and a plurality of side plates. The top plate includes a plurality of holding slots, with the latching members off the side plates. Each latching member has an extension portion and an engaging member. The engaging member is located at the end of the extension under the bottom edge of the side plate. The capacitor includes a main body and a pair of electric leads at one end of the main body. At the opposite end of the electric leads, the main body is bounded on top by the top plate of the main structure, where the main body of each capacitor emerges partially above the upper surface of the top plate.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: April 3, 2012
    Assignee: Lien Chang Electronic Enterprise Co., Ltd.
    Inventors: Chun-Kong Chan, Chi-Ching Chen
  • Patent number: 8148645
    Abstract: A wiring substrate and method of forming a wiring substrate. The wiring substrate includes a base substrate, a first resin insulating layer provided on the base substrate and a laminated capacitor formed within the first resin insulating layer. The laminated capacitor includes a plurality of capacitors laminated to each other by adhesive, each capacitor including a first electrode, a second electrode opposing the first electrode and a dielectric layer interposed between the first and second electrodes. A first via conductor electrically connects the first electrodes of the plurality of capacitors to each other, and a second via conductor electrically connects the second electrodes of the plurality of capacitors to each other. A first external terminal electrically connects to the first via conductor, and a second external terminal electrically connects to the second via conductor.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: April 3, 2012
    Assignee: Ibiden Co., Ltd.
    Inventor: Kazuhiro Yoshikawa
  • Patent number: 8149565
    Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: April 3, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hong Yeon Cho, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Patent number: 8144479
    Abstract: A wireless communication module includes: amounting board including a dielectric frame and a dielectric panel that are stacked together, the frame defining a frame space; at least one electronic component mounted on the mounting board and extending into the frame space; and a plurality of conductive bodies embedded in the dielectric frame and surrounding the frame space so as to prevent electromagnetic interference resulting from the electronic component.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: March 27, 2012
    Assignee: Universal Scientific Industrial Co., Ltd.
    Inventors: Kuo-Hsien Liao, Kuan-Hsing Li
  • Patent number: 8139368
    Abstract: A component-containing module includes a core substrate which includes a lower surface including recessed portions and a raised portion, and an upper surface facing the lower surface and which includes a plurality of in-plane conductors, an integrated circuit element arranged at a location which is above the upper surface and which corresponds to the raised portion, a first passive element and a second passive element disposed in the recessed portions of the lower surface, a composite resin layer which underlies the lower surface and which has a flat or substantially flat surface, and an external terminal electrode which is disposed on the flat or substantially flat surface of the composite resin layer and which is electrically connected to the in-plane conductors of the core substrate. The component-containing module enables electronic components, such as integrated circuit elements and passive elements, to be densely arranged and to be reduced in profile and size.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: March 20, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masato Nomura
  • Patent number: 8134841
    Abstract: According to one embodiment, there is provided a printed-wiring board, includes a first base member including a component mounting face, a first electronic component with a through-electrode mounted on the component mounting face, a second base member stacked on the first base member via an insulating layer covering the first electronic component, a hole part provided in the second base member and communicating with the through-electrode of the first electronic component, and a second electronic component mounted on the second base member and circuit-connected directly to the through-electrode via the hole part.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: March 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daigo Suzuki, Minoru Takizawa, Nobuhiro Yamamoto, Hidenori Tanaka
  • Patent number: 8130507
    Abstract: A component built-in wiring board is provided. The component built-in wiring board 10 includes a core substrate 11, a first component 61, a first built-up layer 31 and a capacitor 101. The core substrate 11 has a housing hole 90 and the first component 61 is housed in the housing hole 90. A component mounting region 20 capable of mounting a second component 21 is provided in a surface 39 of the first built-up layer 31. The capacitor 101 has electrode layers 102 and 103 and a dielectric layer 104. The capacitor 101 is embedded in the first built-up layer 31 such that a first front surface 105 and a second front surface 106 in the electrode layer 102 and a first front surface 107 and a second front surface 108 in the electrode layer 103 are disposed in parallel with the surface 39 of the first built-up layer 31.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: March 6, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Makoto Origuchi, Tsuneaki Takashima
  • Patent number: 8130508
    Abstract: A printed circuit board with an electronic component embedded printed circuit board and a manufacturing method thereof are disclosed. According to an embodiment of the present invention, the method of manufacturing a printed circuit board with an embedded electronic component having a groove formed on one surface thereof and an electrode formed inside the groove includes: forming a first circuit pattern on one surface of a first metal layer; pressing the first metal layer against a first insulator; forming a first conductive protrusion by selectively etching the other surface of the first metal layer; and mounting a first electronic component by disposing a conductive adhesive layer such that an electrode of the first electronic component and the first conductive protrusion are electrically connected to each other. Thus, an electronic component without its electrode protruded outward can be mounted easily and reliably and the manufacturing time can be shortened.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: March 6, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woon-Chun Kim, Soon-Gyu Yim
  • Patent number: 8124883
    Abstract: In a method for manufacturing a ceramic multilayer substrate, when a green ceramic stack prepared by stacking a plurality of ceramic green sheets is fired simultaneously with a ceramic chip electronic component disposed inside the green ceramic stack and including an external terminal electrode to produce a ceramic multilayer substrate having the ceramic chip electronic component inside, a paste layer is disposed in advance between the ceramic chip electronic component and the green ceramic stack, and these three are fired.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: February 28, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Osamu Chikagawa
  • Patent number: 8125761
    Abstract: A capacitive module is provided. The capacitive module may include a first capacitor including a first electrode and a second electrode, one of the first electrode and the second electrode being coupled to at least one first conductive via and the other one of the first electrode and the second electrode being coupled to at least one second conductive via. The capacitive module may also include a second capacitor spaced apart from the first capacitor, the second capacitor including a third electrode and a fourth electrode, one of the third electrode and the fourth electrode being coupled to the at least one first conductive via and the other one of the third electrode and the fourth electrode being coupled to the at least one second conductive via.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: February 28, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Min-Lin Lee, Shinn-Juh Lai, Chen-Hsuan Chiu
  • Patent number: 8125794
    Abstract: The invention provides a multilayer printed wiring board including: a power supply wiring layer and a ground wiring layer provided so as to oppose each other via an insulation layer; mounted integrated circuits; and decoupling capacitors mounted in proximity to the integrated circuits and connected between the power supply wiring layer and the ground wiring layer to absorb noise from the integrated circuits. The power supply wiring layer includes through holes for connecting the decoupling capacitors to the power supply wiring layer and has a polygonal form formed by straight lines which link some of the through holes.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 28, 2012
    Assignee: NEC Infrontia Corporation
    Inventor: Kenji Kouya
  • Patent number: 8119922
    Abstract: Two panel-sized fully populated printed wiring board assemblies formed together, with an anisotropic epoxy that provides electrical connection for RF signals and DC supplies without the need for wirebonds, mechanical interconnects or solder balls.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: February 21, 2012
    Assignee: The Boeing Company
    Inventor: Robert T. Worl
  • Patent number: 8115113
    Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: February 14, 2012
    Assignee: Ibiden Co., Ltd.
    Inventor: Hironori Tanaka
  • Patent number: 8116090
    Abstract: A system is provided for the integration of microwave components in a low temperature co-fired ceramic, the system includes a low temperature co-fired ceramic body having a top surface, into which is disposed a plurality of cavities; a plurality of microwave devices, each device being disposed within a cavity such that the cavities provide radio isolation to the devices; and a coaxial connection disposed within the body configured to connect the devices to external components the coaxial components comprising vias disposed within the co-fired ceramic body.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: February 14, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Blair Coburn, Candice Brittain, Peter Wallace, Thomas O Perkins, III, Michael R Ehlert, Ronald H Schmidt
  • Patent number: 8116091
    Abstract: A printed circuit board has a core substrate including a resin substrate having an opening, a capacitor formed in the opening and having a first electrode structure having a portion facing to the upper surface of the core substrate and a second electrode structure having a portion facing to the lower surface of the core substrate, an upper insulating layer formed over the upper surface of the core substrate and having a conductive circuit formed over the upper insulating layer and a via hole electrically connecting the portion of the first electrode structure and the conductive circuit of the upper insulating layer, and a lower insulating layer formed over the lower surface of the core substrate and having a conductive circuit formed over the lower insulating layer and a via hole electrically connecting the portion of the second electrode structure and the conductive circuit of the lower insulating layer.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 14, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8111520
    Abstract: A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: February 7, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyun-Soo Chung, Dong-Ho Lee, Dong-Han Kim, Seong-Deok Hwang, Ki-Hyuk Kim
  • Patent number: 8111524
    Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: February 7, 2012
    Assignee: Kemet Electronics Corporation
    Inventors: Michael S. Randall, Garry Renner, John D. Prymak, Azizuddin Tajuddin
  • Patent number: 8110896
    Abstract: A capacitor components embedded substrate structure comprises a substrate, capacitor components, a first and second dielectric layers, and a circuit layer. The substrate includes a first surface, a second surface, and a hole penetrating the first and the second surfaces. The capacitor components whose surface is pretreated with a roughness process is received in the hole of the substrate, such that at least one surface of the capacitor components is disposed with a plurality of electrode pads. The first and the second dielectric layers are formed on the surface of substrate and the surface of the capacitor components respectively such that the capacitor components are secured in position in the hole of the substrate. The first and the second dielectric layers have a plurality of openings to expose the electrode pads of the capacitor components.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: February 7, 2012
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Ping Hsu
  • Patent number: 8107253
    Abstract: A printed circuit board includes a chip capacitor having electrodes and a metal film formed on one or more of the electrodes, an accommodating layer accommodating the chip capacitor inside the accommodating layer, a connection layer formed over the accommodating layer and having a via hole opening extending to the metal film, and a first via hole structure formed in the via hole opening of the connection layer and connected to the metal film on the one or more of the electrodes of the chip capacitor.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: January 31, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8107254
    Abstract: A printed circuit board (‘PCB’) with a capacitor integrated within a via of the PCB, the PCB including layers of laminate; a via that includes a via hole traversing layers of the PCB, the via hole characterized by a generally tubular inner surface; a capacitor integrated within the via, the capacitor including two capacitor plates, an inner plate and an outer plate, the two plates composed of electrically conductive material disposed upon the inner surface of the via hole, both plates traversing layers of the laminate, the inner plate traversing more layers of the laminate than are traversed by the outer plate; and a layer of dielectric material disposed between the two plates.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Justin P. Bandholz, Jonathan R. Hinkle, Pravin Patel
  • Patent number: 8107248
    Abstract: A flexible device and a flexible pressure sensor. The present flexible device includes: a first flexible substrate formed of a flexible material to have a flexibility; an active element formed to have a predetermined thickness and a flexibility, and being attached on the first flexible substrate; and a second flexible substrate formed of a flexible material to have a flexibility, and being deposited on the active element. The flexible device and the flexible pressure sensor have a high flexibility, so that they may be applied for a medical treatment such as implantation to a living body, a human body and so forth. In addition, the flexible device has a high flexibility, so that it may be inserted to a curved surface, which contributes to remove the limit of space where the semiconductor package device may be inserted.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-ho Shin, Chang-youl Moon, Yong-jun Kim
  • Patent number: 8098495
    Abstract: A differential mode and common mode combination choke (DCCC) includes: a theta-shaped magnetic core including an essentially round magnetic ring and a magnetic plate engaged with magnetic ring across the area surrounded by the magnetic ring; and two common mode coils with the same number of turns and the same winding direction being wound around the magnetic ring. An EMI (electromagnetic interference) filter and an EMI filter module including the DCCC are also provided.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: January 17, 2012
    Assignee: EMIF Technology Limited
    Inventor: Ho Yan Ho
  • Patent number: 8093508
    Abstract: A printed wiring board including a first insulating layer, a second insulating layer formed over the first insulating layer, a capacitor portion including an upper electrode, a lower electrode and a ceramic high dielectric layer formed between the upper electrode and the lower electrode, the capacitor portion sandwiched by the first insulating layer and the second insulating layer, an upper electrode connecting portion passing through the capacitor portion without contact and through the second insulating layer and electrically connected to the upper electrode of the capacitor portion, and a lower electrode connecting portion passing through the second insulating layer and the upper electrode of the capacitor portion without contact and electrically connected to the lower electrode in contact.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: January 10, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Akira Mochida
  • Patent number: 8093506
    Abstract: A multilayer wiring board capable of feeding sufficient electric power to a circuit element, such as an IC chip. In one embodiment of the present invention, a multilayer wiring board is comprised of: a core board; a build up layer disposed on an upper surface of the core board; a build up layer disposed on a lower surface of the core board; and a power supply structure embedded in a through hole penetrating the core board and the build up layers. The power supply structure is comprised of: a conductive metal rod made of copper as a main material; a conductive metal tube made of copper as a main material and provided coaxially with the conductive metal rod; and an insulating material filling a gap between the conductive metal rod and the conductive metal tube.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: January 10, 2012
    Assignee: NGK Spark Plug Co., Ltd.
    Inventor: Tadahiko Kawabe
  • Patent number: 8089149
    Abstract: A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: January 3, 2012
    Assignee: Rohm Co., Ltd.
    Inventor: Noriaki Hiraga
  • Patent number: 8085547
    Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: December 27, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying-Cheng Wu, Kun-Hsiao Liu
  • Patent number: 8085548
    Abstract: There is provided a circuit substrate to be mounted in an electronic apparatus, and the circuit substrate has a power supply and a GND. The GND of the circuit substrate is electrically connected to GNDs of other components of the electronic apparatus through connecting parts. The circuit substrate has a part or circuit that implements a low impedance in an intended frequency range between the peripheral conductor of the connecting part opening to be used for the connection and the power supply of the circuit substrate.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hiroki Funato, Takashi Suga
  • Patent number: 8081484
    Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: December 20, 2011
    Assignee: Cisco Technology, Inc.
    Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
  • Patent number: 8072769
    Abstract: A component-embedded module includes a module substrate having wiring electrodes on the upper surface thereof, first circuit components mounted on the wiring electrodes, a sub-module disposed on an area on which no wiring electrodes are provided, and an insulating resin layer provided on substantially the entire upper surface of the module substrate such that the insulating resin layer covers at least a portion of the first circuit components and sub-module. The second circuit components including an integrated circuit element are mounted on the sub-module or embedded therein. Via conductors are provided through the module substrate from the lower surface thereof and are directly coupled to terminal electrodes on the lower surface of the sub-module. By using a substrate having a wiring greater accuracy than that of the module substrate, a reliable component-embedded module is obtained.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: December 6, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsutomu Ieki, Kazuyuki Yuda
  • Patent number: 8072775
    Abstract: A printed circuit board includes a signal layer and a voltage source layer. The signal layer includes a connecting area. The voltage source layer includes an isolation area corresponding to the connecting area. The isolation area is used for preventing interference caused by a pulsing current in the connecting area from affecting the voltage source layer.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: December 6, 2011
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Xiang Zhang
  • Patent number: 8071890
    Abstract: An electrically conductive structure includes a first conductive structure and a second conductive structure. Each has a conducting section at one end and a coupling section at the other end. The first and second conducting sections are electrically connected to a power and ground contact of an electronic device, respectively. The first and second coupling sections are respectively connected with power and ground layer of a circuit board. The first coupling sections are connected with the first conducting section through first extending sections and the second coupling sections are connected with the second conducting section through second extending sections. At least two coupling sections of the conductive structures are arranged in pairs. The first conductive structure and the second conductive structure are arranged in a staggered array to form two wiring loops having opposite current directions, thereby generating a magnetic flux cancellation effect.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 6, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chien-Min Hsu, Shih-Hsien Wu, Shinn-Juh Lai, Min-Lin Lee
  • Patent number: 8068347
    Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: November 29, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Don Chul Choi, Jae Cheol Ju, Dong Hwan Lee, Sang Soo Park, Hee Soo Yoon
  • Patent number: 8064216
    Abstract: An edge connector includes, a multilayer printed board having an inner layer and a connector edge, an electronic circuit disposed on the multilayer printed board, an electrical terminal on the multilayer printed board and spaced by a predetermined clearance from the connector edge, an electrical conductor on the multilayer printed board and connected between the electronic circuit and the electrical terminal, a via connected to the electrical terminal and extending to the inner layer of the multilayer printed board, and a lead conductor on the inner layer of the multilayer printed board and connected at one end to the via, another end of the lead conductor being exposed at the connector edge. The electrical terminal is plated. The sum of the length of the via and the length of the lead conductor is less than one-sixth of the wavelength of an electrical signal transmitted.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: November 22, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinji Shibao
  • Patent number: 8064215
    Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: November 22, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yul-Kyo Chung, Sung Yi, Soon-Gyu Yim, Seog-Moon Choi, Jin-Gu Kim, Young-Do Kweon
  • Patent number: 8064214
    Abstract: A press fit passive component, such as a resistor or capacitor, adapted to fit within, or partially within, a via of a printed circuit board. In one example, the press fit passive component has a cylindrically shaped body with solderable terminals at either end of the body, and a dielectric collar disposed at least partially about the cylindrically shaped body.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: November 22, 2011
    Assignee: Dialogic Corporation
    Inventor: Gary D Frasco
  • Patent number: 8064222
    Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: November 22, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yoji Nishio, Seiji Funaba
  • Patent number: 8059423
    Abstract: A multi-layered circuit board is provided having a buried capacitive layer and a device-specific embedded, localized, non-discrete, and distributive capacitive element. A printed circuit board is provided including (1) a first dielectric layer, (2) a first conductive layer coupled to a first surface of the first dielectric layer, (3) a second conductive layer coupled to a second surface of the first dielectric layer, and (4) a localized distributive non-discrete capacitive element adjacent the first conductive layer, wherein the capacitive element occupies a region that approximately coincides with a location over which a device to be coupled to the capacitive element is to be mounted. The embedded, localized, non-discrete, and distributive capacitive element may provide device-specific capacitance to suppress voltage/current noise for a particular device.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: November 15, 2011
    Assignee: Sanmina-Sci Corporation
    Inventor: Nicholas Biunno
  • Patent number: 8054607
    Abstract: There are provided a multilayer chip capacitor and a circuit board device. The multilayer chip capacitor includes a capacitor body including a plurality of dielectric layers that are stacked, first and second outer electrodes formed on an outer surface of the capacitor body and having opposite polarity, first and second inner electrodes opposing each other, interleaved with the dielectric layers in the capacitor body, and each including an electrode plate forming capacitance and a lead extending from the electrode plate, the lead of the first inner electrode and the lead of the second electrode being respectively connected to the first and second outer electrodes, and third inner electrodes interposed between the first and second inner electrodes. At least one of the third inner electrodes adjacent to the first inner electrode includes a conductive pattern having the same shape as the lead of the first inner electrode and is connected to the first outer electrode.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Dong Seok Park, Young Ghyu Ahn, Sang Soo Park, Min Cheol Park
  • Patent number: 8053681
    Abstract: An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hyun Jung, Shi-Yun Cho, Young-Min Lee, Youn-Ho Choi
  • Patent number: 8050045
    Abstract: The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a method of manufacturing the same. A common mode choke coil as the electronic component has an overall shape in the form of rectangular parallelepiped that is provided by forming an insulation layer, a coil layer (not shown) formed with a coil conductor, and external electrodes electrically connected to the coil conductor in the order listed on a silicon substrate using thin film forming techniques. The external electrodes are formed to spread on a top surface (mounting surface) of the insulation layer.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: November 1, 2011
    Assignee: TDK Corporation
    Inventors: Nobuyuki Okuzawa, Makoto Yoshida