Abstract: A motor controller comprising multiple types of interfaces assigned automatically, including a mother circuit board and a daughter circuit board. The daughter circuit board is plugged into the mother circuit board to form electric connection. The mother circuit board has a power circuit, a microprocessor unit of the mother circuit board, a rotor position sensing unit, a power inverter unit, and an analog sensing unit. The daughter circuit board includes a signal interface circuit. The mother circuit board further has a serial digital communication unit. The signal interface circuit includes a microprocessor of the daughter circuit board, and a serial digital communication unit of the daughter circuit board. The microprocessor unit of the mother circuit board communicates with the microprocessor of the daughter circuit board via the serial digital communication unit of the mother circuit board and the serial digital communication unit of the daughter circuit board.

Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.

Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: A circuit board includes an insulation layer having a first surface and a second surface on the opposite side of the first surface, an electronic component positioned in the insulation layer and having a terminal, a conductive pattern formed on the second surface of the insulation layer and electrically connected to the terminal, and an insulative film formed on the second surface of the insulation layer and on the conductive pattern. The terminal of the electronic component has a protruding portion which protrudes from the second surface of the insulation layer.

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of thermal via structures with surface features. In some embodiments the surface features may have dimensions greater than approximately one micron. The thermal via structures may be incorporated into a substrate of an integrated circuit device. Other embodiments may be described and/or claimed.

Abstract: The present invention relates to a device with portions of the device on plural substrate surfaces. The device includes a low resistivity substrate having first and second surfaces with a first electrically-conductive device component disposed over a first surface. An intermediate electrically-insulating layer may be disposed between the electrically-conductive component and the low resistivity substrate. A second electrically-conductive component is disposed over the second surface of the low resistivity substrate. A cavity formed in the low resistivity substrate is at least partially filled with a high resistivity material. One or more electrically-conducting pathways are formed in the high resistivity material electrically connecting the first electrically conductive component and the second electrically-conductive component to form a device. Exemplary devices include inductors, capacitors, antennas and active or passive devices incorporating such devices.

Abstract: The method includes positioning an electronic component using main marks formed on a metal layer and mounting the electronic component on a second surface of the metal layer with an adhesive layer interposed between the metal layer and both of the electronic component and terminals; then burying the electronic component and the main marks in an insulating substrate; then removing part of the metal layer and forming a first window for exposing the main marks therefrom and a second window for exposing the adhesive layer including a position corresponding to the terminal therefrom; then using the exposed main marks as references and forming a laser via hole LVH reaching the terminal in the adhesive layer exposed from the second window; and thereby forming a wiring pattern from the metal layer electrically connected to the terminal through a first conductive via formed by plating the LVH with copper.

Abstract: A semiconductor device includes: a conductive-patterned insulating substrate; conductive blocks fixed to conductive patterns of the conductive-patterned insulating substrate; a semiconductor chip fixed to each conductive block; a printed circuit board that has a conductive post fixed to the semiconductor chip; and a resin. The semiconductor device is configured such that the average volume of a conductive film per unit area of each conductive pattern around a section thereof, to which the corresponding conductive block is fixed, is reduced from the conductive block toward the outside.

Abstract: A bonding pad structure is disclosed, which is composed of two bonding pad units that are symmetrically disposed with respect to an axial line. Each bonding pad units is further composed of at least two bonding pads, i.e. each bonding pad unit is composed of at least one first bonding pad and at least one second bonding pad. In an embodiment, the first bonding pad is arranged next to the axial line and the second bonding pad is arranged at a side of the corresponding first bonding pad away from the axial line while enabling the first bonding pad and the corresponding second bonding pad to be interconnected to each other by a first neck portion. Thereby, a plurality of solder areas of different sizes can be formed by the interconnecting of the at least two bonding pad units that can be used for soldering electronic components of different sizes.

Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

Abstract: A multilayer laminate package and a method of manufacturing the same are provided. The multilayer laminate package includes a cavity layer, a non-cavity layer, an electronic component, and a metalized blind via. The cavity layer includes a first adhesive layer and two first circuit layers, which are stacked with the first adhesive layer between, and an opening. The non-cavity layer includes a second adhesive layer and a second circuit layer. The non-cavity layer is bonded to the cavity layer with the second adhesive layer so as to close one side of the opening. The electronic component is mounted in the opening and is electrically connected to the non-cavity layer exposed through the opening. The metalized blind via electrically connects the non-cavity layer to one of the circuit layers of the cavity layer.

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Abstract: In the present invention, generation of occurrence of a wiring area is prevented, and a reflection by an inconsistency of a characteristic impedance of a high-speed signal line and a through hole connecting portion. By doing so, a conductor pattern of a raised shape is formed on each of front and back of a through hole, on a GND layer closest to the high-speed signal line in the vicinity of the connecting portion of the high-speed signal line and the through hole. Further, the conductor pattern is a trapezoidal shape, and is a shape which becomes wider as it becomes closer to the through hole.

Abstract: An electronic component is mounted on a circuit board. The electronic component includes: a lead frame including a fixed portion, a lead portion connected to the fixed portion, and a heat-dissipating portion connected to the fixed portion; a semiconductor chip fixed on the fixed portion by a first binder; and an encapsulation resin for encapsulating the fixed portion, the semiconductor chip, and a base portion of the lead portion. A groove is provided in the fixed portion and the heat-dissipating portion of the lead frame. The groove extends from a portion of the fixed portion where the first binder is present toward the heat-dissipating portion.

Abstract: Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.

Abstract: A device includes: a wiring board having first and second surfaces opposing each other; and a plurality of memory packages on the first surface. The wiring board includes: a first set of terminals on the first surface; a plurality of second sets of terminals on the first surface; and a plurality of first signal lines. The terminals of the first set receive respective ones of a plurality of first signals supplied from a control device. Each of the second sets is provided for a corresponding one of the memory packages. The terminals of each of the second sets contact the corresponding one of the memory packages. The first signal lines extend from respective ones of the terminals of the first set while coupling respective ones of the terminals of each of the second sets. The first signal lines extend on the first surface without extending in the wiring board.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: An integrated circuit (IC) package with a fibrous interface is provided. The package includes a substrate, a bond coat and a top coat. The substrate is configured to contain IC components and connections. The bond coat layer is configured to encapsulate the IC components. The top coat layer has at least a portion embedded in the bond coat layer. Moreover, the top coat layer includes a fibrous interface configured to provide security and strengthen the bond coat layer.

Abstract: An electronic device includes a printed circuit board (PCB), at least one socket mounted to the PCB, at least one connector inserted into the at least one socket, a first member mounted to the PCB, a second member mounted to the PCB, and a first cover. The first cover covers and presses against the at least one connector, the first cover includes a first end for being fixed to the first member and a second end opposite to the first end for being fixed to the second member. At least one of the first member and the second member is soldered to the PCB, and a soldered area of the at least one of the first member and the second member is larger than a predetermined value.

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

Abstract: A Multi-configuration Processor-Memory device for coupling to a PCB (printed circuit board) interface. The device comprises a substrate that supports multiple configurations of memory components and a processor while having a single, common interface with a PCB interface of a printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components can be pre-tested, packaged memory components mounted on the substrate. The processor can be a surface mounted processor die. Additionally, the processor can be mounted in a flip chip configuration, side-opposite the memory components. In the first configuration, a heat spreader can be mounted on the memory components and the processor to dissipate heat.

Abstract: A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.

Abstract: A planar transformer assembly, for use in charging capacitors of an ICD, includes windings arranged to minimize voltage across intervening dielectric layers. Each secondary winding of a preferred plurality of secondary windings is arranged relative to a primary winding, in a hierarchical fashion, such that the DC voltage, with respect to ground, of a first secondary winding, of the plurality of secondary windings, is lower than that of a second secondary winding, with respect to ground, wherein the first secondary winding is in closest proximity to the primary winding. The primary winding and each secondary winding are preferably formed on a corresponding plurality of dielectric layers.

Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials.

Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.

Abstract: A method for manufacturing an integrated circuit may include forming an electronic circuit in or above a carrier; forming at least one metallization layer structure configured to electrically connect the electronic circuit; and forming a solid state electrolyte battery at least partially in the at least one metallization layer structure, wherein the solid state electrolyte battery is electrically connected to the electronic circuit.

Abstract: An electronic device comprising an electrically conductive core layer with a first layer composed of electrically conductive material, the first layer being applied on both sides and with at least one electronic component arranged in a cutout of the first layer, wherein the first layer is covered in each case with an electrically insulating, thermally conductive layer and a further layer composed of electrically conductive material is provided in each case on the thermally conductive layer, the further layer being coated in each case with a covering layer composed of electrically conductive material, and furthermore having plated-through boles composed of the material of the covering layer, which extend through the electrically insulating, thermally conductive layer covering the electronic component and the further layer composed of electrically and thermally conductive material for the purpose of making contact with the electronic component.

Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: Provided is a video and audio reproduction apparatus including a display unit; a speaker unit; a main board; and a power supply unit, and the main board includes a printed circuit board; a first connector area which is formed on a front side of the printed circuit board; a second connector area which is formed on the front side of the printed circuit board; and a main chip which is surface-mounted on a back side of the printed circuit board.

Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

Abstract: An interposer lead provides a connection between an integrated circuit and a circuit board. The interposer lead includes a first leg for interfacing with the circuit board. The interposer lead also includes a second leg disposed generally parallel to the first leg for interfacing with an IC electrical lead extending from the integrated circuit. A connecting portion operatively connects the first leg and the second leg. The interposer lead further includes a lip extending non-parallel from the second leg for limiting movement of the IC electrical lead on the second leg.

Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract: An electronic device comprises a functional stack (10) and a cover (50) coupled thereto by an insulating adhesive layer (30). The functional stack (10) comprises a first transparent and electrically conductive layer (22), a second electrically conductive layer (24) and a functional structure (26), comprising at least one layer, sandwiched between said first and second conductive layer. The cover (50) includes a substrate (52) and at least a first conductive structure (66, 68) that is arranged in a first plane between the adhesive layer (28) and the substrate (52). First and second transverse electrical conductors (32, 34) transverse to the first plane (61) electrically interconnect the first and the second electrically conductive layer (22, 24) with the first and the second conductive structure (66, 68) in the first plane (61).

Abstract: Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes.

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract: Disclosed is a wiring board with a built-in component and a method for manufacturing the same, the wiring board including: a wiring pattern; an electric/electronic component electrically and mechanically connected with a surface of said wiring pattern; and an insulating layer formed on the same surface of said wiring pattern as said electric/electronic component is connected and configured so as to embed said electric/electronic component, said insulating layer having an insulating resin and a reinforcing material included in the insulating resin, wherein the reinforcing material of said insulating layer exists in the insulating resin without reaching a region of said electric/electronic component in a lateral direction, and wherein the insulating resin of said insulating layer reaches said electric/electronic component so as to adhere to said electric/electronic component.

Abstract: A method and apparatus for filling a via with transparent material is presented, including the steps of providing a panel having a via, occluding the via with transparent material in a workable state so that a portion of the occluding material is internal to the via and a portion of the material is external to said via. The external and internal portions are separated so the transparent filler material, when set, forms a smooth and featureless surface. This causes the filled via to have a substantially even and uniform appearance over a wide range of viewing angles when lit.

Abstract: Embodiments of the invention provide an IC system in which low-power chips can be positioned proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system may include a first substrate, a high-power chip embedded within the first substrate, a second substrate disposed on a first side of the first substrate, the first substrate and the second substrate are in electrical communication with each other, and a low-power chip disposed on the second substrate. In various embodiments, a heat distribution layer is disposed adjacent to the high-power chip such that the heat generated by the high-power chip can be effectively dissipated into an underlying printed circuit board attached to the first substrate, thereby preventing heat transfer from the high-power chip to the low-power chip. Therefore, the lifetime of the low-power chip is extended.

Abstract: Data carrier for contactless data transmission comprising a substrate, a chip having at least one connection pad, wherein the chip is arranged by its side remote from the connection pad on the substrate and a first copper-coated prepreg layer is arranged on the chip and at least partly on the substrate and has a contact opening to the connection pad. A plated-through hole is situated within the contact opening for producing an electrically conductive connection between the connection pad of the chip and the copper layer of the first copper-coated prepreg layer, wherein a first antenna structure is formed in the copper layer of the first copper-coated prepreg layer.

Abstract: An electronic device such as a media player is formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts are used to play audio and to convey digital signals. Electrical components for the device are mounted to a substrate. The components are encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons remain uncovered by encapsulant during the encapsulation process. Integrated circuits are entirely encapsulated with encapsulant. The integrated circuits are packaged or unpackaged integrated circuit die. The substrate is a printed circuit board or is an integrated circuit to which components are directly connected without any printed circuit boards interposed between the integrated circuit and the components.