Abstract: On a multilayer wiring board which has a plurality of wiring pattern stacked in sequence separately from one another, insulating members each positioned between the plurality of wiring patterns, and interlayer connection bodies electrically connecting the plurality of wiring patterns and in which a voltage conversion IC is built in, a first capacitor, a second capacitor, and an inductor are mounted, the other of electrode portions in the first capacitor or one of electrode portions in the second capacitor is positioned between an input section of the first capacitor and the inductor, and the other of the electrode portions or the one of the electrode portions is electrically set to ground.

Abstract: Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide.

Abstract: A compact driver device for driving an LED lighting device is provided. The driver device includes a substrate, power capacitor that provides LED driving current to drive the LED lighting device, and a power resistor. Advantageously, the power capacitor and the power resistor are attached to the substrate and are solderlessly connected to each other to provide a very compact driver device.

Abstract: A high-frequency device includes a wireless IC chip and a board which is coupled to the wireless IC chip and electrically connected to radiator plates, and an inductor and/or a capacitance are provided as a static electricity countermeasure element in the board. The inductor is connected in parallel between the wireless IC chip and the radiator plates, and its impedance at the frequency of static electricity is less than an impedance of the wireless IC chip.

Abstract: A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.

Abstract: A multilayer circuit board of a wireless terminal, a circuit assembly comprising the circuit board and a wireless terminal comprising the circuit assembly are provided. The wireless terminal is of a type which utilizes a UICC. The multilayer circuit board is configured to accommodate a UICC encapsulated within one or more interior layers of the multilayer circuit board, for example as a semiconductor die. The multilayer circuit board is further configured to accommodate one or more additional components integral to functionality of the wireless terminal, optionally also embedded within the circuit board. Integration of components into the interior layers may facilitate theft deterrence and/or tamper resistance. A physical programming interface to the encapsulated UICC may be rendered inaccessible after initial programming.

Abstract: A conductive paint electromagnetic interference (EMI) shield for an electronic module or device. The conductive paint is composed of metal particles suspended in a fluidic carrier. In one embodiment, the conductive paint is sprayed onto exterior surfaces of an electronic module or device from a spray gun. The sprayed conductive paint is cured to remove the fluidic carrier, leaving a metal film coated to the outside of the module or device. In one embodiment used with electronic packages in array form, grooves are cut into an encapsulation material of a module so that the shield protection includes sidewalls of the package. In another embodiment used with camera modules, masking is used to selectively shield portions of the module. In a further embodiment, the shield is electrically connected to a ground conductor of a circuit of the electronic module.

Abstract: A composite wafer includes a molded wafer and a second wafer. The molded wafer includes a plurality of first components, and the second wafer includes a plurality of second components. The second wafer is combined with the molded wafer to form the composite wafer. At least one of the first components is aligned with at least one of the second components to form a multi-component element. The multi-component element is singulatable from the composite wafer.

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.

Abstract: Methods and apparatus for memory systems with memory chips are described. In an embodiment, a system includes a memory controller chip, memory chips, and a module connector each on a first substrate and at least two groups of conductors to provide read data signals from at least some of the memory chips to the memory controller chip and to provide read data signals from the connector to the memory controller chip. Furthermore, a memory module is inserted in the module connector and including memory chips on a second substrate at least some of which are to receive signals from at least some for the memory chips on the first substrate and at least some of which are to provide the read data signals to be provided to the second group of conductors. Other embodiments are described.

Abstract: A motherboard includes a first circuit board, a second circuit board, and wiring. The first circuit board includes at least a programmable chip, a programming interface, a first data interface, and at least one jumper corresponding to the programmable chip. The second circuit board includes a CPU (central processing unit), a RAM unit, and at least a second data interface corresponding to the programmable chip. The motherboard of the present disclosure concentrates programmable chips on the first circuit board, thereby providing a unified programming interface to enhance the convenience of programming multiple programmable chips.

Abstract: The disclosure provides a core layer for an information carrying card, resulting information carrying card, and methods of making the same. A core layer for an information carrying card comprises at least one thermoplastic layer having at least one cavity, an inlay layer, and, and a crosslinked polymer composition. At least one portion of the inlayer layer is disposed inside the at least one cavity of the at least one thermoplastic layer. The crosslinked polymer composition is disposed over the at least one thermoplastic layer and contacting the inlayer layer.

Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.

Abstract: The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory.

Abstract: An integrated circuit includes a substrate. A first integrated circuit die includes a first circuit and a first intra-chip clock interface that transmits a first clock signal via the substrate. A second integrated circuit die includes a second circuit that operates based on the first clock signal and a second intra-chip clock interface that recovers the first clock signal from the substrate.

Abstract: A solid state storage device includes a printed circuit board assembly, a memory arranged on the printed circuit board assembly, and a storage medium arranged on the printed circuit board assembly. The storage device further includes a processor arranged on the printed circuit board assembly, wherein the processor is coupled to the memory and to the storage medium via the printed circuit board assembly, and wherein the processor is configured to store data in the memory and the storage medium and to read data from the memory and the storage medium. The storage device further includes a removable power pack comprising a plurality of capacitors serially arranged in a housing, wherein the plurality of capacitors is detachably connected to the printed circuit board assembly to supply backup power to the processor, the memory, and the storage medium when the removable power pack is mounted in the solid state storage device.

Abstract: According to one embodiment, a television apparatus includes a circuit board, a pad, a heat-transfer layer, and a block. The circuit board is mounted with an electronic component. The pad is provided on a surface of the circuit board. The heat-transfer layer is formed on the inner surface of a through hole in the circuit board. The through hole has an opening on the pad. The block contains a resin material and is located inside the heat-transfer layer to block the through hole.

Abstract: A method for laying out a printed circuit board for use in a gigabit-capable passive optical network includes the steps of providing a printed circuit board and laying out an analog circuit module, an analog-to-digital conversion module, a signal processing module, an optoelectronic transmitting and receiving module, and a power module on the printed circuit board. The printed circuit board has a first periphery and an opposing second periphery. The analog circuit module and the optoelectronic transmitting and receiving module are laid out at the first periphery of the printed circuit board. The power module is laid out at the second periphery of the printed circuit board. Electromagnectic wave generated by a power IC inserted in the power module does not interfere with data transmission taking place at the optoelectronic transmitting and receiving module. Furthermore, a printed circuit board for use with the method is proposed.

Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Abstract: A semiconductor module assembly is provided. The semiconductor module assembly includes a motherboard, a socket, and a semiconductor module. The motherboard includes an opening for receiving the semiconductor module, the opening including at least three sides. The socket is disposed in the opening along at least a first side, second side, and third side of the at least three sides. The semiconductor module is disposed in the socket. The semiconductor module includes at least one semiconductor device mounted on a module board. The socket includes at least a first side along the first side of the opening, and a second side along the second side of the opening, and the semiconductor module electrically connects to the motherboard through at least the first and second sides of the socket.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: An improved power distribution network for an integrated circuit package that reduces the number of power supply pins that are used in the pin array and achieves better operating performance. In a preferred embodiment, the ratio of power supply pins to input/output (I/O) pins is in the range of approximately 1 to 24 to approximately 1 to 52. In this embodiment, the integrated circuit package comprises a substrate, an integrated circuit mounted on the substrate, a first decoupling capacitor mounted on the substrate, and a second decoupling capacitor formed in the integrated circuit. The package is formed by coupling a power supply pin to both the first and second capacitors by a low frequency path and a DC path, respectively, and the first and second capacitors are coupled by a high frequency path.

Abstract: A packaging system comprising: forming terminal leads; configuring a cavity by partially encapsulating the terminal leads with a compound; attaching an integrated circuit device, a micro-electromechanical system, a micro-mechanical system, or a combination thereof in the cavity; and bonding a cover to the terminal leads for enclosing the cavity.

Abstract: A system for providing power and ground vias for power distributions systems includes first and second conductive layers on a microelectronic package. The conductive layers may include one or more conductive components such as, but not limited to, power planes, ground planes, pads, traces, and the like for electrically connecting to electronic components. A via may electrically connect the first and second conductive layers. The via may have a cross-section of at least three partially-overlapping shapes. Each of the shapes partially overlaps at least two of the other shapes. The shapes may be, for example, circular, triangular, rectangular, square, polygonal, rhomboidal shape, or any other shape.

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract: One embodiment of the present invention provides a method that reduces power consumption by using capacitive coupling to perform a majority detection operation. The method involves driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. In addition, method involves feeding a signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The method further involves using the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by a computer system.

Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.

Abstract: According to one embodiment, an electronic apparatus includes a housing, a wiring pattern, a recess, a pad portion, and an electronic component. The wiring pattern is formed on an inner surface of the housing from an electrically conductive adhesive. The recess is in the inner surface of the housing. The pad portion is formed in the recess from the conductive adhesive and connected to an end portion of the wiring pattern. The electronic component includes a terminal which contacts the pad portion.

Abstract: A technique provides security to an electronic device. The technique involves disposing a microprocessor between a printed circuit board and a circuit element to restrict physical access to the microprocessor, the microprocessor having (i) a bottom which faces the printed circuit board in a first direction and (ii) a top which faces the circuit element in a second direction which is opposite the first direction. The technique further involves delivering power to the microprocessor from a power source while the microprocessor is disposed between the printed circuit board and the circuit element, the microprocessor performing electronic operations in response to the power delivered from the power source. The technique further involves electronically altering or preventing the microprocessor from further performing the electronic operations in response to tampering activity on the circuit element. Such detection of the tampering activity may involve monitoring a covert signal for tamper evidence detection.

Abstract: A device having an integrated circuit and a circuit package. A first terminal contact, a second terminal contact, and a third terminal contact are brought out of the circuit package. The first terminal contact and the second terminal contact are each connected to terminals of the integrated circuit for power supply. The third terminal contact is connected to a terminal of the integrated circuit in the circuit package for signal transmission. A first capacitor is connected to the first terminal contact and a second capacitor is connected to the third terminal contact, wherein a fourth terminal contact and a fifth terminal contact are brought out of the circuit package, and the first capacitor is connected to the fourth terminal contact, and the second capacitor is connected to the fifth terminal contact.

Abstract: An electronic device includes a printed circuit board (PCB), at least one socket mounted to the PCB, at least one connector inserted into the at least one socket, a first member mounted to the PCB, a second member mounted to the PCB, and a first cover. The first cover covers and presses against the at least one connector, the first cover includes a first end for being fixed to the first member and a second end opposite to the first end for being fixed to the second member. At least one of the first member and the second member is soldered to the PCB, and a soldered area of the at least one of the first member and the second member is larger than a predetermined value.

Abstract: An upper board having an opening and forming a circuit on a surface layer, a connection sheet between boards having an opening and forming conductive holes filled with conductive paste in through-holes, and a lower board forming a circuit on a surface layer are stacked up, heated and pressed. In particular, the connection sheet between boards is made of a material different from the upper board and the lower board. A multi-layer circuit board having a cavity structure, and a full-layer IVH structure with high interlayer connection reliability can be manufactured.

Abstract: Various embodiments relate to an in-cell battery management device including: an integrated circuit (IC) including a controller, a resistive balancer, a voltage sensor, and a pressure sensor; and an IC package that encloses the IC having a hole over the pressure sensor wherein the hole allows the pressure sensor to measure pressure in a battery cell; wherein the IC package is contact with the battery cell.

Abstract: A microstructural body includes a substrate such as an electrode substrate, a support portion, one post that fixes the support portion to the substrate, a frame-shaped movable portion provided around outer periphery of the support portion, and an elastic support portion that elastically connects the movable portion and the support portion. The elastic support portion supports the frame-shaped movable portion such that the movable portion is movable relative to the support portion. The elastic support portion includes torsion springs and an elastically deformable connecting portion.

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; processing a top edge of the support structure along an outermost periphery thereof, to include a recess for preventing mold bleed, the recess surrounded by the lead finger system; and encapsulating the recess and the electrical interconnect system with an encapsulation material to interlock the encapsulation material.

Abstract: An electronic board includes conducting traces having an upper surface at least partially sunken with respect to a gluing surface of the board. A surface mount technology electronic device for mounting to the board includes insulating windows that define gluing sites within one or more pins. An electronic system is formed by one or more of such surface mount technology electronic devices mounted to electronic board. The devices are attached using a wave soldering technique that flows through channels formed by the sunken conductive traces.

Abstract: A package substrate includes a main package body including a first principal surface on which an IC is mounted, and a second principal surface, opposed to the first principal surface, on which first bonding materials for mounting are provided. An internal circuit is provided within the main package body and connected to the first bonding materials. A sub-package is arranged on the second principal surface and includes electronic components embedded therein. A thickness direction dimension being the distance from the second principal surface to a portion of the sub-package most distant from the second principal surface, is not more than a thickness direction dimension being the distance from the second principal surface to an edge of the first bonding material at the second principal surface.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second microfeature devices having corresponding first and second bond pad surfaces that face toward each other. First bond pads can be positioned at least proximate to the first bond pad surface and second bond pads can be positioned at least proximate to the second bond pad surface. A package connection site can provide electrical communication between the first microfeature device and components external to the package. A wirebond can be coupled between at least one of the first bond pads and the package connection site, and an electrically conductive link can be coupled between the first microfeature device and at least one of the second bond pads of the second microfeature device. Accordingly, the first microfeature device can form a portion of an electrical link to the second microfeature device.

Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.

Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.

Abstract: For the purpose of providing a semiconductor element built-in type multilayered circuit board in which a semiconductor element is closely joined to a recess of an insulating substrate to effectively disperse heat generated from the semiconductor element through the insulating substrate at a working temperature region of the semiconductor element circuit board, to surely conduct an electrical connection of an electronic part such as semiconductor element or the like in a short wiring and to enable the high density mounting of semiconductor elements, miniaturization and increase of working speed, there is proposed a semiconductor element built-in type multilayered circuit board formed by laminating a plurality of semiconductor element built-in type boards each comprising an insulating substrate and a semiconductor element accommodated in a recess formed therein, characterized in that a difference between a linear expansion coefficient of the insulating substrate and a linear expansion coefficient of the semicon

Abstract: Packaged integrated circuits having inductors and methods to form inductors in packaged integrated circuits are disclosed. An example method comprises forming a substrate having a first trace and a contact, attaching an integrated circuit to the substrate over the first trace, and electrically coupling the first trace to the contact via an electrical conductor that extends over the integrated circuit to form the inductor in the packaged integrated circuit.

Abstract: An object of the present invention is to provide a functional device-embedded substrate that can be thinned and suppress occurrence of warpage. The present invention provides a functional device-embedded substrate including at least a functional device including an electrode terminal, and a covering insulating layer covering at least an electrode terminal surface and a side surface of the functional device, the functional device-embedded substrate including a first pillar structure around the functional device inside the covering insulating layer, the first pillar structure including a material having a thermal expansion coefficient between thermal expansion coefficients of the functional device and the covering insulating layer, wherein the first pillar structure is arranged at a position where a shortest distance from a side surface of the functional device to a side surface of the first pillar structure is smaller than a thickness of the functional device.

Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, a radio-frequency shielding structure may be mounted over the electrical components. The radio-frequency shielding structure may be formed from a printed circuit that includes a ground plane such as a flex circuit or rigid printed circuit board that includes at least one blanket layer of metal. The printed circuit board to which the electrical components are mounted may include a recess in which the electrical components are mounted. Additional components may be mounted to the interior and exterior surface of the radio-frequency shielding structure. The radio-frequency shielding structure may be formed from a flex circuit that has slits at its corners to accommodate folding.

Abstract: A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region.

Abstract: A circuit board includes a foil circuit provided on a synthetic resin plate formed by injection molding, made of a copper foil, and having a pattern different for the circuit board. Anchor pins projecting upward are provided on the resin plate and passed through pinholes made in the foil circuit. The foil circuit is positioned and secured to the resin plate. In a required portion of the resin plate, a terminal insertion hole is provided, and a receiving terminal is secured to the required portion of the terminal insertion hole and connected to the foil circuit.