Shaped Lead On Components Patents (Class 361/773)
  • Patent number: 11509078
    Abstract: A discrete electrical component is disclosed, including a component member having at least one lead; and a base member on which the component member is supported. The electrical component further includes at least one compliant pin member, each compliant pin member having a first end portion configured for press-fit engagement in a printed circuit board and a second end portion electrically connected to the at least one lead of the component member. The at least one compliant pin at least partly extends through or into the base member.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 22, 2022
    Assignee: VITESCO TECHNOLOGIES USA, LLC.
    Inventors: Patrick Su, Kevin D Moore
  • Patent number: 11462343
    Abstract: An object is to provide a resistor manufacturing method and a resistor capable of suppressing variation in the thickness of a thermally conductive layer intervening between a resistive body and electrode plates. The method of manufacturing the resistor according to the present invention includes a step of forming an uncured first thermally conductive layer on a surface of a resistive body, a step of curing the first thermally conductive layer, a step of laminating an uncured second thermally conductive layer on a surface of the first thermally conductive layer, and a step of bending electrode plates respectively disposed at both sides of the resistive body, curing the second thermally conductive layer, and performing adhesion between the resistive body and the electrode plates via the first thermally conductive layer and the second thermally conductive layer.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 4, 2022
    Assignee: KOA CORPORATION
    Inventors: Yuichi Abe, Seiji Karasawa, Michio Kubota, Yoji Gomi, Koichi Minowa
  • Patent number: 11044804
    Abstract: A connector assembly and a display device are provided. A connector assembly includes a first connector comprising a long-side portion at which a plurality of signal terminals is located and a short-side portion at which a power source voltage terminal is located, and a printed circuit board including a plurality of signal printed lines connected to the plurality of signal terminals and a power source voltage printed line connected to the power source voltage terminal, the first connector being arranged on the printed circuit board.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minyoung Park, Jongmin Shim
  • Patent number: 11025130
    Abstract: An onboard device includes a first cover member having a first abutment surface, a second cover member having a second abutment surface abutting on the first abutment surface and an internal space for housing an electrical apparatus with the first cover member, a transmission portion that is formed in one or both of the first and second cover members, extends, from the first and second abutment surfaces, outward in an abutment direction in which the first and second abutment surfaces abut against each other and transmits sound more easily from the internal space to outside of the first and second cover members than adjacent regions in the first and second cover members, and a soundproof cover that has a through-hole penetrating in the abutment direction. The first abutment surface, the second abutment surface, and the transmission portion are located inside the through-hole.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: June 1, 2021
    Assignee: SUBARU CORPORATION
    Inventors: Toshiya Tateishi, Yukihito Inaba, Tomoatsu Imamura, Takeki Nemoto, Hiroyuki Suzuki
  • Patent number: 10916491
    Abstract: A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)<1 holds, where A and B are the tensile strength of the first and second solder, respectively. As a result, even if the lead terminal which thermally expands because of heat generated by the semiconductor element expands or contracts toward the semiconductor element, a stress applied by the lead terminal is absorbed and relaxed by the first solder. This prevents damage to the surface electrode of the semiconductor element by suppressing the occurrence of cracks.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: February 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Kohei Yamauchi, Hiromichi Gohara, Tatsuhiko Asai
  • Patent number: 10910834
    Abstract: A solar array power generation system includes a solar array electrically connected to a control system. The solar array has a plurality of solar modules, each module having at least one DC/DC converter for converting the raw panel output to an optimized high voltage, low current output. In a further embodiment, each DC/DC converter requires a signal to enable power output of the solar modules.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 2, 2021
    Assignee: Solaredge Technologies Ltd.
    Inventors: F. William Capp, William J. Driscoll
  • Patent number: 10714411
    Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
  • Patent number: 10347995
    Abstract: A circuit structure disclosed in the present specification includes: a circuit board provided with a wiring portion; a conductor body (conductor plate) adhered to one side of the circuit board; and a terminal that electrically connects the wiring portion of the circuit board and the conductor body. The terminal includes a relay connection portion between a portion connected to the wiring portion and a portion connected to the conductor body, and the relay connection portion protrudes past the wiring portion, on the other side of the circuit board.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: July 9, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Yukinori Kita
  • Patent number: 10276535
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10276534
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10135162
    Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jose A. Hejase, Wiren D. Becker, Daniel Dreps, Sungjun Chun, Brian Beaman
  • Patent number: 9984822
    Abstract: An element body includes a first principal surface and a second principal surface opposing each other in a first direction. A first terminal electrode is disposed on the first principal surface side of the element body. A second terminal electrode is disposed on the second principal surface side of the element body. The first terminal electrode includes a first sintered metal layer formed on the first principal surface; and a first plating layer formed on the first sintered metal layer and including base metal. The second terminal electrode includes a second sintered metal layer formed on the second principal surface, a second plating layer formed on the second sintered metal layer and including base metal, and a solder layer formed on the second plating layer and including Sn and a metal having a higher melting point than the melting point of Sn.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: May 29, 2018
    Assignee: TDK CORPORATION
    Inventors: Masahiro Iwama, Takehisa Tamura, Atsushi Sato, Tomonori Oi
  • Patent number: 9437942
    Abstract: A battery assembly includes: a receptacle connector including a receptacle contact with a bolt hole for bolting formed therein, a receptacle housing attached to the receptacle contact; a battery having an upper surface on which the receptacle contact of the receptacle connector is attached by the bolting, and a right side surface roughly perpendicular to the upper surface. The receptacle housing of the receptacle connector is formed so as to extend in an elongated shape along the tangent direction of an imaginary circle C centered on the central axis of the bolt hole of the receptacle contact of the receptacle connector as viewed in the central axis direction of the bolt hole, and is capable of coming into contact with the right side surface of the battery at the time of the bolting.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: September 6, 2016
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LTD.
    Inventors: Yasukazu Itou, Akira Kuwahara
  • Patent number: 9418919
    Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: August 16, 2016
    Assignee: NXP B.V.
    Inventors: Roelf Anco Jacob Groenhuis, Markus Björn Erik Noren, Fei-ying Wong, Hei-ming Shiu
  • Patent number: 9414489
    Abstract: In order to prevent deformation or damage of a base of a lead terminal by alleviating stress which concentrates on the base of the lead terminal protruding from an electronic component main body, the lead terminal includes a connection pad connected to a connection terminal provided on a first substrate, and a lead portion extending from the connection pad, and the lead terminal also includes a first surface connected to the connection terminal, a second surface that is a rear surface thereof, and a third surface that is a side surface, and in which the lead portion includes a first bent section and a third bent section that are bent in a direction intersecting the first surface or the second surface, a second bent section that is bent in a direction intersecting the third surface between the first bent section and the third bent section.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 9, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Manabu Kondo
  • Patent number: 9119320
    Abstract: A printed circuit board assembly is disclosed, including a printed circuit board including at least one opening, and a system in package assembly, wherein the system in package assembly includes a system in package module and a lead frame bonded to the system in package module. The lead frame includes a plurality of pins. The system in package assembly is embedded into the opening of the printed circuit board.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 25, 2015
    Assignee: QUANTA COMPUTER INC.
    Inventor: Li-Cheng Shen
  • Publication number: 20150116970
    Abstract: A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.
    Type: Application
    Filed: April 5, 2013
    Publication date: April 30, 2015
    Inventors: Arata Kishi, Hironori Munakata, Koji Motomura, Hiroki Maruo
  • Patent number: 9013891
    Abstract: An electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 21, 2015
    Assignee: Finisar Corporation
    Inventors: Yunpeng Song, Yongsheng Liu, Hongyu Deng
  • Patent number: 8933554
    Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: January 13, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yoshihiro Kodaira
  • Patent number: 8923007
    Abstract: In at least one embodiment, a circuit board assembly that includes a printed circuit board is provided. The printed circuit board includes a top surface and a bottom surface for supporting at least one through-hole electrical component. The printed circuit board defines at least one component hole extending from the top surface to the bottom surface for receiving the at least one through-hole electrical component. The at least one component hole includes a first section having a first diameter and a second section having a second diameter. The first diameter is different from the second diameter. Each of the first and the second sections are configured to receive solder paste for forming a solder joint with the at least one through-hole electrical component.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 30, 2014
    Assignee: Oracle America, Inc.
    Inventors: Michael Francis Sweeney, Jorge Eduardo Martinez-Vargas, Jr., Michael Clifford Freda
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Patent number: 8908387
    Abstract: A wiring board includes a substrate having an opening portion, electronic components positioned in the opening portion of the substrate and including first and second electronic components, and an insulation layer formed over the substrate and the first and second components. The first component has first and second electrodes having side portions on side surfaces of the first component, the second component has first and second electrodes having side portions on side surfaces of the second component, the first electrode of the first component and the first electrode of the second component are set to have substantially the same electric potential, and the first component and the second component are positioned in the opening portion of the substrate such that the side portion of the first electrode of the first component is beside the side portion of the first electrode of the second component.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 9, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yukinobu Mikado, Shunsuke Sakai, Takashi Kariya, Toshiki Furutani
  • Patent number: 8867228
    Abstract: An electrode bonding structure sealed with a sealing resin, in which a flexible substrate is bonded to a first substrate via an adhesive, wherein: a region along a bottom face edge of an flexible substrate end part is bonded, via the adhesive, to an inner side region of a region along a top face edge of an first substrate end part; a gap is formed between an inner side region of the region along the bottom face edge of the flexible substrate end part and the region along the top face edge of the first substrate end part; the sealing resin is formed so as to enter, while covering a top face of the flexible substrate end part, at least a portion of the gap; and a height of the gap gets smaller towards the adhesive from the top face edge of the first substrate end part.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Hiroaki Katsura, Koso Matsuno, Yoji Ueda
  • Patent number: 8815646
    Abstract: A semiconductor device is formed by molding using a resin with a semiconductor element and one or two heat dissipating plates contained therein, said one or two heat dissipating plates being disposed to face one surface or both the surfaces of the semiconductor element. An intermediate layer is formed by spraying a metal powder to the semiconductor element and to one of or both of the heat dissipating plates using a cold spray method, and the semiconductor element and the heat dissipating plate are bonded together using a solder with the intermediate layer therebetween.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hirotaka Ohno
  • Patent number: 8816411
    Abstract: A semiconductor device featuring a semiconductor chip including a MOSFET and having a first main surface and a second, opposing main surface, a source electrode pad and a gate electrode pad over the first main surface, a drain electrode over the second main surface, a source external terminal and a gate external terminal, each having a first main surface electrically connected to the source electrode pad and gate electrode pad of the chip, respectively, and a drain external terminal having a first main surface and a second, opposing main surface and being electrically connected to the second main surface of the chip, each of the source, gate and drain external terminals having second main surfaces thereof in a same plane, and, in a plan view of the external terminals, the gate external terminal has a portion located between the source and drain external terminals in at least one direction.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 26, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiak Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20140204552
    Abstract: A sensor includes: a substrate on which an active chip including a semiconductor circuit is disposed; and a passive chip including an acceleration sensor, and a thick portion and a thin portion, the thick portion being disposed on the substrate so as to be in contact therewith. An active chip terminal is disposed on the active chip. A passive chip terminal is disposed on the passive chip at the thin portion. The passive chip terminal and the active chip terminal face each other and are connected via a bump.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicant: Seiko Epson Corporation
    Inventor: Satoshi Nakajima
  • Publication number: 20140198469
    Abstract: An electronic circuit having an electronic component mounted on a substrate, a light source device having the electronic circuit, and a method of manufacturing the electronic circuit on which the electronic component is mounted on the substrate are described. The electronic component has a plurality of lead pins to be electrically connected to wirings on the substrate. The substrate is formed with a hole having a larger dimension than a maximum distance between at least two lead pins of the lead pins. The lead pins are inserted into the hole from sides of tips of the lead pins while being bent at a plurality of bending portions, and fixed to the substrate by a solder.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 17, 2014
    Inventors: Hiroyuki BASHO, Katsuhiko MAEDA, Masashi SUZUKI, Yuugo MATSUURA
  • Patent number: 8779575
    Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Shinohara
  • Patent number: 8760840
    Abstract: A lead 3 of an electrochemical device includes a lead body 3A containing Al, and a bent metallic thin film 3a provided to a tip part of the lead body 3A. The metallic thin film 3a includes a thin film body 3a1 containing Ni, and a plating layer 3a2 containing Sn and covering at least an outer surface of the bent thin film body 3a1. A specific area of an inner surface of the bent thin film body 3a1 and a surface of the lead body 3A are welded in a predetermined area without the plating layer 3a2 being disposed there between.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: June 24, 2014
    Assignee: TDK Corporation
    Inventors: Hiroaki Hasegawa, Hidetake Itoh, Yoshihiko Ohashi, Kazuo Katai, Yosuke Miyaki
  • Publication number: 20140168922
    Abstract: A semiconductor device has a control terminal attached to a patterned insulating substrate; a first projection formed on the control terminal; a second projection formed on the control terminal; a concave formed between the first projection and the second projection; a resin case disposed to cover the patterned insulating substrate, and having an opening for passing the control terminal therethrough; a first concave portion; a beam portion disposed at the opening of the resin case; a second concave portion formed in the beam portion; a resin block inserted into the opening of the resin case and sandwiching the control terminal together with the sidewall of the opening of the resin case to fix the control terminal to the resin case; a convex step portion; a third projection formed on a side surface of the resin block; and a fourth projection thinned on a bottom surface of the resin block.
    Type: Application
    Filed: August 24, 2012
    Publication date: June 19, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Publication number: 20140160709
    Abstract: Provided is a tuner module including a tuner module main body involving a tuner board, a first leg projected from the tuner module main body and to be inserted into a first hole formed on a circuit board main body, a second leg projected from the tuner module main body and to be inserted into a second hole formed on the circuit board main body, the second leg being shorter than the first leg, and a signal terminal projected from the tuner board and to be inserted into a third hole formed on the circuit board main body, the signal terminal being shorter than the second leg. A taper is formed on at least tip end parts of the first leg and the second leg.
    Type: Application
    Filed: August 3, 2012
    Publication date: June 12, 2014
    Inventors: Tadashi Imai, Keisuke Yoshida, Kazunari Ueda, Toshiyuki Sudo, Makoto Makishima
  • Patent number: 8749989
    Abstract: An LTCC carrier composed of thermosetting polymer, woven glass fiber and ceramic has gold over nickel contact pads on top and bottom surfaces and conductive vias therethrough between aligned pairs of top and bottom pads. The vias prevent undesirable inductive paths from limiting high frequency operation of the circuitry. Solder deposits on the top pads attach the LTCC component, which is further secured to the carrier by epoxy, thus improving resistance to thermal stress and mechanical shock. A slot through the carrier body between top and bottom surfaces further reduces thermal stress and mechanical shock. Metallized castellations on opposite carrier sides provide additional surface area for reflow solder joints with the PCB, and a means for visually inspecting the solder joint quality. A gap in the metallization on the top layer of the carrier prevents solder spreading during multiple soldering cycles, which may result in poor solder joints.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: June 10, 2014
    Assignee: Scientific Components Corporation
    Inventors: Harvey L. Kaylie, Aron Raklyar
  • Publication number: 20140140027
    Abstract: The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for signal nodes and ground nodes which utilizes the cross-talk reduction by cancellation property of geometrically symmetry and orthogonality to reduce signal node to ground node ratio for increasing signaling density.
    Type: Application
    Filed: December 22, 2011
    Publication date: May 22, 2014
    Inventors: Raul Enriquez Shibayama, Jimmy A. Johansson, Kai Xiao
  • Publication number: 20140085850
    Abstract: Electronic devices may contain electrical systems in which electrical components are mounted on a substrate such as a printed circuit board. The electrical components may include surface mount technology components. Multiple surface mount technology components may be stacked on top of each other and beside each other to form an electrical component that minimizes the amount of area that is consumed on a printed circuit board. Noise suppression circuits and other circuits may be implemented using stacked surface mount technology components. Surface mount technology components placed on the printed circuit board may be pushed together and subsequently injection molded to form packed component groups. An integrated circuit may be mounted to the printed circuit board via an interposer and may cover components mounted to the printed circuit board. An integrated circuit may be mounted over a recessed portion of the printed circuit board on which components are mounted.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Xingqun Li, Carlos Ribas, Dennis R. Pyper, James H. Foster, Joseph R. Fisher, JR., Scott P. Mullins, Sean A. Mayo, Wyeman Chen
  • Publication number: 20140029226
    Abstract: An integrated circuit chip includes first and second electrode terminals electrically connected to an internal circuit, and a dummy bump arranged between the first and second electrode terminals on a back surface thereof. A wiring pattern includes first lines electrically connected to the first electrode terminals below the back surface of the integrated circuit chip and extend in the direction toward a display region outside the integrated circuit chip, and second lines electrically connected to the second electrode terminals below the back surface of the integrated circuit chip and extend in the direction opposite to the display region outside the integrated circuit chip. The dummy bump is configured to avoid at least one of the electrical connection between the dummy bump and all of the first lines and all of the second lines and the electrical connection between the dummy bump and the internal circuit.
    Type: Application
    Filed: July 16, 2013
    Publication date: January 30, 2014
    Inventors: Hideaki ABE, Yasushi NAKANO, Hitoshi KAWAGUCHI
  • Patent number: 8633408
    Abstract: A miniature housing, in whose housing body there is located an element emitting or receiving electromagnetic radiation, comprises at least two electrical terminal means projecting laterally beyond the housing body. The passage side of the miniature housing, through which the element emits or receives, is oriented substantially perpendicularly to the mounting plane of the miniature housing. The electrical terminal means of the miniature housing projecting laterally beyond the housing body are connected electrically conductively to conductors, which bring about direct contacting with the emitting or receiving element. The contacting faces of the terminal means are thus arranged substantially perpendicular to the passage side of the miniature housing. As a result of this arrangement the miniature housing may be embedded at least in part in a support, such that the miniature housing is no longer of any significance to the thickness of a lighting device.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: January 21, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Charles Lee, Feng Sheng, Jenny Zhou
  • Patent number: 8631706
    Abstract: One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Nickolaus J Gruendler, Paul M Harvey, Tae Hong Kim, Sang Y Lee, Michael J Shapiro
  • Patent number: 8619432
    Abstract: Some embodiments of the inventive subject matter are directed to a first circuit board configured to include an electronic component. The electronic component includes a plurality of leads. The first circuit board includes first wires configured to connect to a first portion of the plurality of leads. The second circuit board is affixed to the first circuit board. The second circuit board includes second wires. The second circuit board is smaller in size than the first circuit board. A plurality of electrical connectors extend through a thickness of the first circuit board and are configured to connect a second portion of the plurality of leads to the second wires.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Douglas A. Baska, Daniel M. Dreps, Rohan U. Mandrekar, Roger D. Weekly
  • Publication number: 20130335939
    Abstract: The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.
    Type: Application
    Filed: December 6, 2011
    Publication date: December 19, 2013
    Inventors: Aleksandar Aleksov, Sanka Ganesan
  • Publication number: 20130271937
    Abstract: According to one embodiment, an electronic apparatus includes a substrate, a first electronic component, and a reinforcing member. The substrate includes first electrodes. The first electronic component includes a base, second electrodes, and solders configured to connect the first electrodes to the second electrodes. The reinforcing member includes a supporting member between the substrate and the base and a reinforcing material fixed to the supporting member, the reinforcing member fixed to the substrate and the base, and the reinforcing material formed of a thermosetting resin configured to remove an oxide film and fastened to the solders and the substrate.
    Type: Application
    Filed: January 7, 2013
    Publication date: October 17, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhiro YAMAMOTO, Takahisa FUNAYAMA
  • Publication number: 20130258624
    Abstract: A printed circuit board according to one example embodiment includes a Z-directed component mounted in a mounting hole in the printed circuit board. The Z-directed component includes a body having a top surface, a bottom surface and a side surface. Four conductive channels extend through a portion of the body along the length of the body. The four conductive channels are spaced substantially equally around a perimeter of the body. An integrated circuit is mounted on a surface of the printed circuit board. The integrated circuit has a ball grid array that includes four conductive balls electrically connected to a corresponding one of the four conductive channels of the Z-directed component.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Inventor: Keith Bryan Hardin
  • Patent number: 8547701
    Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronic module includes at least one first embedded component (6), the contact terminals (7) of which face essentially towards the first surface of the insulating-material layer (1) and which is connected electrically by its contact terminals (7) to the conductor structures contained in the electronic module. According to the invention, a second embedded component (6?), the contact terminals (7?) of which face essentially towards the second surface of the insulating-material layer and which is connected electrically by its contact terminals (7?) to the conductor structures contained in the electronic module, is attached by means of glue or two-sided tape to the first component (6), and the contact terminals (7, 7?) are connected to the conductor structures with the aid of a conductive material, which is arranged in the insulating-material layer in holes (17) at the locations of the contact terminals (7, 7?).
    Type: Grant
    Filed: November 24, 2005
    Date of Patent: October 1, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Antti Iihola
  • Publication number: 20130250534
    Abstract: A cover shield for a circuit board having a body. A peripheral wall is disposed about an edge of the body. First and second slots each include a first portion that extends through the body and a second portion that extends through the peripheral wall. A barbed tab is disposed between the first and second slots. A notch extends through a portion of the barbed tab. A distinct abutting member is disposed on the peripheral wall.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Applicant: GENTEX CORPORATION
    Inventor: Lucas G. Schrab
  • Publication number: 20130235542
    Abstract: In an example embodiment, an electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: FINISAR CORPORATION
    Inventors: Yunpeng SONG, Yongsheng LIU, Hongyu DENG
  • Patent number: 8513819
    Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 20, 2013
    Assignee: Carsem (M) SDN. BHD.
    Inventors: Liew Siew Har, Law Wai Ling
  • Publication number: 20130194754
    Abstract: An apparatus for a single chip package using Land Grid Array (LGA) coupling is provided. The apparatus includes a multi-layer substrate, at least one integrated circuit chip, and a Printed Circuit Board (PCB). The a multi-layer substrate has at least one substrate layer, has at least one first chip region and at least one second chip region in a lowermost substrate layer, configures a transmission line transition of a vertical structure for transmitting a signal from at least one integrated circuit chip coupled in the first chip region in a coaxial shape or in a form of a Co-Planar Waveguide guide (CPW), and has an LGP coupling pad for connecting with a Printed Circuit Board (PCB) in the lowermost layer. The at least one integrated circuit chip is coupled in the first chip region and the second chip region. The PCB is connected with the multi-layer substrate using the LGA coupling via the LGA coupling pad.
    Type: Application
    Filed: October 5, 2011
    Publication date: August 1, 2013
    Applicant: Samsung Electronics Co. Ltd.
    Inventors: Dong-Yun Jung, Sung-Tae Choi, Young-Hwan Kim, Jung-Han Choi, Ji-Hoon Kim, Jei-Young Lee, Dong-Hyun Lee
  • Patent number: 8472205
    Abstract: An adaptive printed circuit board (PCB) connector consists of an adapter. The adapter comprises a printed circuit board having connectors connectable to battery terminals of a battery terminal structure of a populated circuit board (POP) of a mobile device. The adapter can have an opening shaped or adapted to receive the battery terminal structure of the POP. Battery terminals can be spring loaded. Spring loaded battery terminals can provide connective stability between POP and adapter by pushing against edge inside of opening of the adapter.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: June 25, 2013
    Assignee: Research In Motion Limited
    Inventors: Robert Michael Philip Gondosch, James Robert Bastow
  • Patent number: 8472208
    Abstract: A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer (5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 ?m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: June 25, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Oshika, Masayuki Nakano
  • Publication number: 20130128486
    Abstract: A method of forming a bump structure includes providing a first work piece including a dielectric layer having a top surface; placing a second work piece facing the first work piece; placing a heating tool contacting the second work piece; and heating the second work piece using the heating tool to perform a reflow process. A first solder bump between the first and the second work pieces is melted to form a second solder bump. Before the second solder bump solidifies, pulling the second work piece away from the first work piece, until an angle formed between a tangent line of the second solder bump and the top surface of the dielectric layer is greater than about 50 degrees, wherein the tangent line is drawn at a point where the second solder bump joins the dielectric layer.
    Type: Application
    Filed: December 28, 2012
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Publication number: 20130120948
    Abstract: The present invention provides a circuit component that enables satisfactory connection between a substrate and an IC chip and a method of making the same. The circuit component includes an IC chip and a substrate connected to each other using an electrically conductive adhesive containing electrically conductive particles. Bump electrodes and a non-electrode surface are provided on a mounting surface of the IC chip. The non-electrode surface is a portion of the mounting surface other than a portion where the bump electrodes are formed. Electrically conductive particles are placed in a first state between the surfaces of the substrate and the non-electrode surface so as to be in contact with both surfaces. Electrically conductive particles are placed in a second state between the surfaces of both the substrate and the bump electrodes, so as to be more flattened than the first state and dig into the bump electrodes.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 16, 2013
    Applicant: HITACHI CHEMICAL CO., LTD.
    Inventor: Hitachi Chemical Co., Ltd.