Shaped Lead On Components Patents (Class 361/773)
  • Patent number: 7391101
    Abstract: A semiconductor pressure sensor can reduce the damage of bonding wires to increase their life time even under an environment in which the temperature and pressure change rapidly and radically. The semiconductor pressure sensor includes a package (1) made of a resin and having a concave portion (1a), a lead (2) formed integral with the package (1) by insert molding, with its one end exposed into the concave portion (1a) and its other end extended from the package (1) to the outside, a sensor chip (3) arranged in the concave portion (1a) for detecting pressure, and a bonding wire (4) electrically connecting the sensor chip (3) and the lead (2) with each other. An interface between the lead (2) and the package (1) on the side of the concave portion (1a) is covered with a first protective resin portion (6) of electrically insulating property, and the bonding wire (4) is covered with a second protective resin portion (7) that is softer than the first protective resin portion (6).
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: June 24, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshimitsu Takahata, Hiroshi Nakamura, Masaaki Taruya, Shinsuke Asada
  • Publication number: 20080130256
    Abstract: A motherboard includes a printed circuit board having a first via and a second via, and an integrated circuit component having a first pin and a second pin. The integrated circuit component is mounted on the printed circuit board by inserting the first pin and the second pin of the integrated circuit component into the first via and the second via of the printed circuit board respectively, wherein the first pin and the second pin of the integrated circuit component are differently shaped in cross section, and the shapes of the first via and the second via are corresponding to the shapes of the first pin and the second pin. The electronic component cannot be mis-mounted on the PCB.
    Type: Application
    Filed: August 7, 2007
    Publication date: June 5, 2008
    Applicants: HONG FU JIN PRECISION INDUSTRY (ShenZhen) Co., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: ZHEN-SHENG WANG, KE-YOU HU
  • Publication number: 20080117610
    Abstract: The present invention relates to the mounting of electronic display devices with portals for attaching various other electronic devices using cables in a streamlined, versatile fashion. More specifically, the present system relates to an apparatus that provides cable management for electronic devices such as audio speakers, LCD projectors, electronic text boards, televisions, liquid crystal display (LCD) or other flat panel monitors (“display monitors”), and many other electronic devices. Furthermore, the present invention provides a versatile mounting system whereby any of the above electronic devices can be conveniently affixed to a variety of surfaces, such as walls, desks, and even unconventional bases such as store displays or mannequins.
    Type: Application
    Filed: October 23, 2006
    Publication date: May 22, 2008
    Inventor: Richard Picolli
  • Patent number: 7342267
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: March 11, 2008
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Patent number: 7332757
    Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: February 19, 2008
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Ryoichi Kajiwara, Masahiro Koizumi, Toshiaki Morita, Kazuya Takahashi, Munehisa Kishimoto, Shigeru Ishii, Toshinori Hirashima, Yasushi Takahashi, Toshiyuki Hata, Hiroshi Sato, Keiichi Ookawa
  • Publication number: 20080002381
    Abstract: The present invention refers to an “INTRABALL CONNECTION MODULE”, that is interconnected to an electronic board (2) by the communication means (3), thus allowing data transmission, information exchange and recharging the battery (6) installed in the electronic board (2). The connection module (1) comprises a connector (4), where a pin is introduced that allows internal access to the electronic board (2).
    Type: Application
    Filed: December 13, 2006
    Publication date: January 3, 2008
    Inventor: Roberto Estefano
  • Patent number: 7307339
    Abstract: A semiconductor device including: a substrate on which a plurality of leads are formed; and a semiconductor chip mounted on the substrate in such a manner that a surface of the semiconductor chip having a plurality of electrodes faces the substrate. Each of the leads includes a first portion that is bonded to one of the electrodes and a second portion that extends outward from the inner side of a region in the substrate that overlays the semiconductor chip. The second portion is entirely adhered to the substrate and curved.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: December 11, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Masami Uchida
  • Patent number: 7167377
    Abstract: A circuit-constituting unit forming a distribution circuit or the like in a vehicle. The circuit-constituting unit includes a plurality of bus bars for constituting a power circuit; a semiconductor switching device provided in the power circuit; and a control circuit board. The bus bars are bonded to a surface of the control circuit board such that the bus bars are arranged to be generally coplanar with each other. The semiconductor switching device is mounted on both of the corresponding bus bars and the control circuit board. An opening may be formed through the control circuit board. In this case, one of terminals of the semiconductor switching device may be connected to a surface of the control circuit board facing away from the surface to which the bus bars are bonded. The other terminals may be connected respectively to the bus bar through the opening.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: January 23, 2007
    Assignees: Sumitoo Wiring Systems, Ltd., Autonetworks Technologies, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Onizuka, Isao Isshiki, Ryuji Nakanishi, Kouichi Takagi, Tou Chin, Shigeki Yamane
  • Patent number: 7150387
    Abstract: An apparatus for mounting an electric component onto a board by means of a lead-free solder material. The apparatus of the present invention has a solder material supplying chamber in which a melt of the solder material is supplied to the board by a solder material supplying unit such that the solder material adheres to a predetermined portion of the board. The apparatus further includes a cooling chamber in which the board is cooled by a cooling unit such that the solder material adhering to the board is rapidly cooled to solidify. A conditioning chamber can also be positioned between the solder material supplying chamber and the cooling chamber. The conditioning chamber conditions the board such that the solder material adhering to the board is ensured to be a completely molten condition at least before the rapid cooling of the solder material.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: December 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Masato Hirano, Yoshinori Sakai
  • Patent number: 7132736
    Abstract: Devices and methods of fabrication thereof are disclosed. A representative device includes a complaint wafer-level package having one or more lead packages. A representative lead package includes a substrate having a plurality of die pads disposed thereon and a plurality of leads attached to the plurality of die pads. In addition, the lead package includes a plurality of pillars made of a low modulus material. Each pillar is disposed between the substrate and at least one lead, and each lead is disposed upon one of the pillars that compliantly support the lead.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 7, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, James D. Meindl, Chirag S. Patel
  • Patent number: 7113408
    Abstract: A printed circuit board includes a dielectric layer and an area array of contact elements extending above a first surface of the dielectric layer. Each contact element includes a conductive portion disposed to engage a respective pad of a land grid array module for providing electrical connection to the land grid array module. The land grid array module can include a land grid array package or a second printed circuit board. In one embodiment, the contact elements are selected from the group of contact types including metal springs, bundled wires, metal in polymer, and solid metal tabs. In another embodiment, a contact element in the area array includes a base portion of conductive material and an elastic portion of conductive material formed integrally with the base portion whereby the elastic portion extends from the base portion and protrudes above the first surface of the dielectric layer.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: September 26, 2006
    Assignee: Neoconix, Inc.
    Inventors: Dirk D. Brown, John D. Williams
  • Patent number: 7084490
    Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: August 1, 2006
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 7068520
    Abstract: In a flat pin to be used in a circuit board made of resin with pins comprising a rod portion having a diameter of not greater than 0.35 mm and a concentric tabular large diameter portion having a larger diameter than that of the rod portion formed on one end of the rod portion, the ratio (W/S) of the diameter of the large diameter portion to the rod portion is from not smaller than 2.16 to not greater than 2.67 and the ratio (T/S) of the thickness of the large diameter portion to the diameter of the rod portion is from not smaller than 0.40 to not greater than 0.67 supposing that the diameter of the rod portion and the large diameter portion of the flat pin are S and W, respectively, and the thickness of the large diameter portion is T.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: June 27, 2006
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Noritaka Miyamoto, Kazuhisa Sato
  • Patent number: 7064420
    Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: June 20, 2006
    Assignee: St Assembly Test Services Ltd.
    Inventors: Byung Joon Han, Byung Hoon Ahn, Zheng Zheng
  • Patent number: 7045720
    Abstract: A system may include an electronic component body, and one or more leads coupled to and extending from the electronic component body. A first lead of the one or more leads may comprise a first leg and a second leg, the first leg and the second leg defining an acute angle therebetween.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventors: Clement Sagayanathan, Paribalan Suntharalingam
  • Patent number: 6940013
    Abstract: A power converter includes electrical contacts arranged on a first surface and a connection device. The converter has a top surface above the first surface and a bottom surface below the first surface. A border of the bottom surface is inset from a border of the second surface. The connection device includes a pair of conductive legs, each leg comprising a first end and a second end. The pair of legs lie opposite each other in a pair of evenly spaced planes that intersect the first surface. The first ends are adapted to connect to one or more of the contacts on the first surface and the second ends are adapted to connect to one or more conductive pads on a surface of a substrate. The connection device is adapted to enable the first ends of the two legs to connect to the contacts from below the first surface.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: September 6, 2005
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Jay Prager, Michael B. LaFleur
  • Patent number: 6939740
    Abstract: A resin-sealed semiconductor IC package of a large integration size having a size substantially equal to that of its component semiconductor IC chip. The resin-sealed semiconductor IC package includes a semiconductor IC chip, a plurality of leads arranged on the semiconductor IC chip and having end portions bent so as to extend perpendicularly to the major surface of the semiconductor IC chip, a resin molding sealing the semiconductor IC chip and the leads therein so that the tips of the end portions of the leads are exposed on one surface thereof, and conductive elements connected respectively to the exposed tips of the leads.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: September 6, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tadashi Yamaguchi
  • Patent number: 6912781
    Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a set of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the conductors of the component are routed through the lead channels. A set of insertable lead terminals, adapted to cooperate with the specially shaped lead channels, are received and captured within the lead channels, thereby forming an electrical connection between the lead terminals and the conductors of the electronic component(s). A method of fabricating the device is also disclosed.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: July 5, 2005
    Assignee: Pulse Engineering, Inc.
    Inventors: Timothy J. Morrison, Aurelio J. Gutierrez, Thomas Rascon
  • Patent number: 6911736
    Abstract: A package substrate that is adapted to receive at least one subject integrated circuit having a subject contact pattern, where the subject integrated circuit is selected from a design set of integrated circuits. The package substrate has an upper surface with electrically conductive bump contacts in a bump array. The bump array is configured to provide electrical connections to all possible integrated circuit contact patterns in the design set of integrated circuits. A lower surface of the package substrate has electrically conductive ball contacts in a ball array. One each of the bump contacts is electrically connected to one each of the ball contacts through the package substrate. An electrically conductive ground plane is disposed between the upper surface and the lower surface. Grounding contacts are disposed adjacent the ball contacts, where the grounding contacts are electrically connected to the ground plane.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: June 28, 2005
    Assignee: LSI Logic Corporation
    Inventor: Kumar Nagarajan
  • Patent number: 6909168
    Abstract: A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: June 21, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Toru Nomura
  • Patent number: 6897378
    Abstract: A technique for mounting an electrical component to a circuit board includes deforming each of a number of electrical terminals extending from the electrical component to form a mounting portion and a tip portion extending away from the mounting portion. The circuit board defines a number of bores extending therein from a first surface to a second opposite surface, and the electrical component is mounted to the circuit board with the mounting portion of each of the number of electrical terminals supporting the component against the first surface of the circuit board with each of the tip portions extending into separate ones of the number of bores. The mounting portion of each of the electrical terminals is mechanically and electrically affixed to corresponding electrically conductive pads to thereby surface mount the electrical component to the circuit board. The disclosed technique is particularly advantageous for surface mounting display units.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: May 24, 2005
    Assignee: Delphi Technologies, Inc.
    Inventor: Michael Dennis Phalen
  • Patent number: 6888723
    Abstract: An LED lamp apparatus comprises LED, a circuit member, and a case member. The case member has an LED seat for holding the LED. The circuit member has metal plates embedded in the case member. The metal plates have LED connection members exposed from the case member. The LED connection members have been resistance welded respectively to leads of the LED.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: May 3, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takayuki Kamiya, Kazushi Noda, Mitsuhiro Nawashiro, Hiroshi Ito, Akihiro Misawa
  • Patent number: 6870261
    Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: March 22, 2005
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chih-Liang Hu, Wen-Long Chen, Pan-Nan Chen, Ming-Chong Liang, Cheen-Hai Yu
  • Patent number: 6862189
    Abstract: An electronic component including an element main body section for performing an electrical function and a terminal section for electrically connecting the element main body section to a conductive member of an external device, the electronic component comprises a pair of sections arranged above the terminal section and opposite to each other in a stacking direction of the electronic component and a distance between the sections corresponding to a maximum thickness of the electronic component.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuhito Higuchi
  • Patent number: 6800932
    Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: October 5, 2004
    Assignee: Advanced Analogic Technologies, Inc.
    Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
  • Patent number: 6791842
    Abstract: An image sensor includes a substrate, a frame layer, signal input terminals, a photosensitive chip, a transparent layer, a plurality of wires and a glue layer. The substrate has a first surface and a second surface. The frame layer is placed on the first surface to form a cavity together with the substrate. The signal input terminals are formed on the frame layer. The photosensitive chip has plural bonding pads, and is placed on the first surface of the substrate and positioned within the cavity. The transparent layer is placed over the frame layer to define, in the cavity, at least one exposure area through which the bonding pads of the photosensitive chip are exposed. The wires penetrate through the exposure area and electrically connect the bonding pads to the signal input terminals. The glue layer covers the exposure area to seal the plurality of wires.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: September 14, 2004
    Assignee: Kingpak Technology Inc.
    Inventor: Chung Hsien Hsin
  • Patent number: 6788547
    Abstract: The invention provides an electrical contact device, a pre-assembly for producing the electrical contact device, and a method of forming the electrical contact device. The electrical contact device includes a plurality of fine pitch electrical leads disposed in parallel spaced apart relation. An insulating member encapsulates portions of the electrical leads which extend from opposite sides of the insulating member. The insulating member retains the electrical leads in position and electrically isolated from one another. The contact device is used to facilitate connection with the leads of an IC package.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Walter Moden
  • Patent number: 6779264
    Abstract: A method for manufacturing an electronic device by placing within a die a first lead with an element placement pad, a second lead, and an electronic element placed on the element placement pad. The electronic element, the element placement pad, a part of the first lead, and a part of the second lead are sealed in a package by injecting a sealing resin in the die from a position on a longer side of the package, with the position being offset toward one shorter side thereof. The first lead is bent in an S shape, with a bending depth being at least as large as the thickness of the first lead. A thickness of the resin on a non-device side of the element placement pad is smaller than the bending depth.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: August 24, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Kobayashi, Hideki Fukazawa, Satoshi Utsunomiya
  • Patent number: 6778406
    Abstract: Resilient contact structures provide electrical interconnection between a semiconductor die and another electronic component. Multilayered packaging may be formed on the semiconductor die, and the resilient contact structures may be formed on portions of one or more of the layers. Heat dissipating structures may be provided on the die.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: August 17, 2004
    Assignee: FormFactor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 6764325
    Abstract: The present invention relates to apparatus and methods for minimizing open electrical connections between carrier substrates and components connected thereto that occur due to sag in the substrate incurred due to exposure to an increasing heat profile encountered to secure the component to the substrate. A zero insertion force heat activated retention pin expands or bends during the temperature increase, creating an upward force on the printed circuit board. This upward force counters the downward sag forces and enables the carrier substrate to maintain a coplanar relationship with the component being connected.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: July 20, 2004
    Assignee: Intel Corporation
    Inventors: George Arrigotti, Raiyomand Aspandiar, Christopher D. Combs, Tom E. Pearson
  • Patent number: 6762485
    Abstract: A conductive plastic lead frame and method of manufacturing, the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Jerrold L. King
  • Patent number: 6747356
    Abstract: Control of the characteristic impedance of wirings is performed with high accuracy.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: June 8, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideko Ando, Seiji Miyamoto
  • Publication number: 20040064941
    Abstract: Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 8, 2004
    Applicant: FormFactor, Inc.
    Inventors: Thomas H. Dozier, Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu, David V. Pedersen, Michael A. Stadt
  • Patent number: 6717066
    Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: April 6, 2004
    Assignee: Intel Corporation
    Inventors: Gilroy J. Vandentop, Yuan-Liang Li
  • Patent number: 6717822
    Abstract: An edge stiffener added to a lead-frame based circuit module provides protection of the peripheral flange of the circuit module during handling and manufacturing processes. The edge stiffener may be coupled to leads of the lead-frame for providing electrical contacts at the periphery of the circuit module or may be form widened portions of a tie bar that is connected to the lead frame by leads extending through gaps between the ends of the edge stiffener portions. Singulation of the circuit module will result in edge stiffener portions that are not coupled to the lead frame, but are secured within the encapsulant.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: April 6, 2004
    Assignee: Amkor Technology, Inc.
    Inventors: Jeffrey Alan Miks, Markus Karl Liebhard
  • Patent number: 6713836
    Abstract: In a leadframe packaging structure, a leadframe includes a plurality of first leads, a plurality of second leads, and a die pad. The first leads define a chip-bonding region in which is arranged the die pad. The second leads extend and terminate into a plurality of contact pads in the chip-bonding region. An adhesive tape further is bonded on bottom surfaces of the contact pads. A chip is bonded on the die pad. At least a passive device is mounted between and electrically connects the contact pads. A plurality of bonding wires respectively connect the chip, the passive device, and the first and second leads. An encapsulant material encapsulates the chip, the passive device, and the bonding wires.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Sheng-Tsung Liu, Kang-Wei Ma
  • Patent number: 6713849
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: March 30, 2004
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 6705006
    Abstract: Electrical nets are prepared by bonding an electrically conductive element in a deleted plated via. The electrically conductive element has a headed portion that contacts the bottom of the laminate and the other end of the electrically conductive element electrically connects to a BGA pad or surface trace line.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: March 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Baechtle, Stephen R. Howland
  • Patent number: 6704210
    Abstract: A bioprosthesis sealing film strip is attached to a surgical stapler by passing a jaw of the stapler through openings formed in the ends of the strip. Following stapling the strip is released by making a cut from the opening to the edge of the strip. Alternatively, one end of the strip may be releasably secured to pins formed on the jaw.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: March 9, 2004
    Assignee: Medtronic, Inc.
    Inventor: David J. Myers
  • Patent number: 6690583
    Abstract: A carrier intended for one or several electronic components and having spaces provided for the components on at least one surface is provided. The carrier has an at least partly conductive Low Temperature Cofire Ceramic (LTCC) material with good thermal conduction capacity, so that the carrier provides mechanical support for the components and conducts heat generated by the components.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: February 10, 2004
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Bergstedt, Per Ligander
  • Publication number: 20040016567
    Abstract: A surface mounted electronic component includes a case and a board mounting part. The board mounting part includes a leg bent in parallel with a printed circuit board at its tip, an outer frame soldered to a land of a mounted part on the board, and a projection disposed in the outer frame and inserted into a hole in the mounted part. The electronic component is mounted on a surface of the printed circuit board in various electronic instruments, and can keep to be mounted on the board tightly even when an external force is applied.
    Type: Application
    Filed: July 29, 2003
    Publication date: January 29, 2004
    Inventors: Masato Yamasaki, Koji Ono, Takumi Nishimoto, Jun Sato
  • Patent number: 6675471
    Abstract: A method of producing high-frequency modules at a higher efficiency is provided comprising: an electronic components mounting step 62 of fabricating on a master substrate 21 rows of sub substrates 22, each the sub substrate 22 having an identical pattern of circuit developed thereon, and mounting electronic components on the sub substrate 22; a step 64 of, after the step 62, providing slits for electrically isolating signal terminals formed integrally; a laser trimming step 66 of, after the step 64, engaging pins 39 of an inspection tooling in direct contact with the signal terminals to conduct an inspection; and a separating step 72 of, after the step 66, separating the sub substrates 22 from the master substrate 21. Accordingly, the productivity for the high-frequency modules will be improved.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 13, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Junichi Kimura, Toshiaki Tamura, Takahiro Yajima, Kazuhiko Tsuyama
  • Patent number: 6665930
    Abstract: A printed circuit board with SMD components electrically connected to the printed circuit board by means of a reflow soldering process. In order to provide the printed circuit board with connection elements which can be mounted at minimal cost, the printed circuit board is provided with one or more connection elements for making an electric connection to other electric components. These connection elements are journaled in recesses of the printed circuit board and do not project to the exterior via the surface of the printed circuit board on which the SMD components are secured.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: December 23, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Peter Matuschik
  • Patent number: 6657135
    Abstract: A connection structure of the present invention has a board with a through hole perforating therethrough, a land formed around the through hole, and a lead extending from an electronic component and disposed in the through hole. The land includes a wall surface land portion formed on a wall surface of the through hole, and front and back surface land portions formed on the front and back surfaces of the board respectively. A fillet connecting the land and the lead includes upper and lower fillet portions respectively contacting with the front and back surface land portions. A profile of the upper fillet portion is smaller than that of the lower fillet portion and is not smaller than that of the through hole. Therefore, occurrence of lift-off is effectively reduced while using a lead-free solder material.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: December 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenichiro Suetsugu, Masuo Koshi, Kenichiro Todoroki, Shunji Hibino, Hiroaki Takano, Mikiya Nakata, Yukio Maeda
  • Publication number: 20030189817
    Abstract: A multilayer ceramic capacitor with external terminals having terminal electrodes and external terminals of the electronic device body electrically bonded through a solder layer, wherein the solder layer is comprised of an Sn—Sb high temperature lead-free solder, the ratio between the Sn and Sb in this solder layer is, by ratio by weight percent, in a range of Sn/Sb=70/30 to 90/10, and the solder layer and terminal electrodes are formed between them with a diffusion layer formed by diffusion of a conductive ingredient of the terminal electrodes into the solder layer.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 9, 2003
    Applicant: TDK Corporation
    Inventors: Akitoshi Yoshii, Kazuhiko Kikuchi, Takashi Kamiya, Hiromi Kikuchi
  • Patent number: 6617510
    Abstract: A metallic or an electrical trace having a terminus and a stress relief bend formed in the trace adjacent the terminus. The electrical trace may have a portion carried by a flexible substrate to form a flexible circuit. The stress relief bend may be free floating and extend from the flexible substrate or may be encapsulated by the flexible substrate. The electrical circuit and the flexible circuit each have a generally planar portion extending in the X and Y axis, with the stress relief bend projecting into the Z axis. This allows electrical traces to be spaced with a very narrow pitch because the stress relief bend does not consume any valuable real estate on the flexible circuit or the substrate to which the electrical trace is applied.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: September 9, 2003
    Assignee: Delphi Technologies, Inc.
    Inventors: Chris M. Schreiber, Bao Le, Eric Dean Jensen
  • Patent number: 6617522
    Abstract: A connector, and an associated method, for connecting an electrical circuit component to a substrate, such as a printed circuit board. The connector is formed of one of more pin members formed of an electrically-conductive material which exhibits physical-memory characteristics. The pin member is initially configured into a memory configuration and thereafter reconfigured into an alternate reconfiguration. The alternate configuration is selected to facilitate mounting of the circuit component upon the substrate. Thereafter, the pin member is heated to beyond a deformation threshold temperature. When at such temperature, the pin member becomes reconfigured into the memory configuration. Through appropriate selection of the memory configuration, heating of the pin member causes connection of the circuit component with the substrate.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: September 9, 2003
    Assignee: Nokia Corporation
    Inventor: Cristian Tabacutu
  • Patent number: 6612024
    Abstract: A semiconductor device with bump electrodes having acutely shaped tips and method of mounting same. The bump electrodes are brought into contact with respective portions of a conductive pattern of a mounting substrate without any foreign matter between the tips of the bump electrodes and the respective portions of the conductive pattern. Thereafter, sealing material is allowed to surround the bump electrodes.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: September 2, 2003
    Assignee: Sony Corporation
    Inventors: Dai Sasaki, Tohru Terasaki, Masuo Kato, Masami Tsurumi
  • Publication number: 20030127723
    Abstract: A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory chip with a number of pins disposed in an interior of the TSOP memory chip housing. The pins leading out of a respective TSOP memory chip housing and, via a rewiring configuration, are connected to pins leading out of a respectively directly adjacent TSOP memory chip housing of the same TSOP memory chip housing stack. In order to be able to produce such a housing stack as cost-effectively and simply as possible by an automated mounting method, the rewiring configuration is implemented in the form of leadframes respectively disposed between or at the side between the individual TSOP memory chip housings.
    Type: Application
    Filed: February 26, 2003
    Publication date: July 10, 2003
    Applicant: Infineon Technologies AG
    Inventors: Andreas Worz, Alfred Gottlieb, Bernd Romer
  • Patent number: 6580160
    Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: June 17, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Jicheng Yang