Abstract: The system and methods describe a computer system implementing an adjustable control signal path whose length may be precisely adjusted to control timing of a control signal that propagates along the path. One such adjustable signal path has two clusters of possible signal paths. Each of the signal paths in each cluster has a length, and the overall length of the control signal path may be adjusted by selectively implementing one signal path from each of the clusters by electrically connecting that path into the electrical circuit by the selective installation of zero ohm resistors. In this way, a system designer may design several possible signal path lengths on to a motherboard or printed circuit card, and implement the path length which provides the most precise signal timing adjustment.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device includes: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.

Abstract: A high quality factor on-package, off-die inductor assembly is disclosed. The assembly includes a flip-chip, ball-grid array package substrate, an on-package, off-die trace line is coupled to one or more bumps attached to an upper surface of the package substrate. The trace line has a self-inductance and a predetermined length. The quality factor associated with the inductor is a ratio of the trace line's inductance to the trace lines resistance. The package substrate is a low loss laminate.

Abstract: An integrated circuit package comprises a set of bond fingers for connecting wire bonds from the chip, the bond fingers being placed overlapping on a transverse axis from the chip and extending inwardly and outwardly from vias positioned at different positions along the transverse axis, so that wire bonds connected to adjacent fingers have the same length.

Abstract: A jumper chip component of the present invention includes a connection conductor formed of a conductive layer over an upper face and opposite side faces of an insulating substrate, and a conductive material formed of a conductive layer between plates of the insulating substrate and on a side face at the corner of the insulating substrate so as not to be electrically connected to the connection conductor. Since the conductive material formed between the plates of the insulating substrate opposes the connection conductor formed on the upper face of the insulating substrate, the connection conductor formed on the upper face of the insulating substrate and a second conductive pattern disposed under the insulating substrate are shielded from each other by the conductive material, and good isolation is possible.

Abstract: In a high-frequency module mounting structure according to the present invention, a circuit board includes a reinforcing electrode on the lower surface thereof for increasing a mounting strength of the first and second electrode groups in a state of being in close proximity, a motherboard includes a reinforcing lands corresponding to the reinforcing electrodes in a state of being in close proximity to the lands, and the electrodes and the lands, and the reinforcing electrodes and the reinforcing lands are soldered. Therefore, soldering of the high-frequency module with respect to the motherboard is enhanced, and thus a reliable high-frequency module mounting structure is provided.

Abstract: The present invention provides an improved structure of gold fingers, which is to redesign a conventional gold finger on a packaging substrate into a gold finger set that contains a plurality of gold finger units. Between each single gold finger unit, there exists an electrical connection. Therefore, in the structure of stacked-chip packaging, each wire that is connected through wire bonding on the same gold finger of each layer chip can separately perform wire bonding on different gold finger units of the same gold finger set. Due to the improvement on the gold finger structure, the present invention can prevent the adhesive on a chip from flowing along the wire bonding path of a layer chip and smearing the whole gold finger. Thus, other layer chips can be prevented from being unable to perform wire bonding.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: A circuit board includes a substrate and electrical contacts to mate with a slot connector. The contacts include a first set of contacts that are associated with the communication of power and second set of contacts that are associated with the communication of signals and are not used to communicate power. Adjacent contacts of the first set have a first spacing, and adjacent contacts of the second set have a second spacing different from the first spacing. The circuit board has a retention profile to engage a retention mechanism of the slot connector. A housing of the slot connector may be made from a material that has a thermal conductivity of at least 0.27 W/m·K, and the slot connector housing may include fins that are formed on the slot connector to conduct heat away from circuitry of the circuit board.

Abstract: A through-hole formed in a printed circuit board is prevented from being contaminated with water-resistant liquid coated on circuit elements. To prevent the water-resistant liquid from flowing into the through-hole, a barrier such as a bank surrounding the through-hole is formed in a screen-printing process for printing other patterns on the circuit board. The barrier is easily and precisely formed in a space between the through-hole and the circuit elements coated with the water-resistant liquid without requiring an additional manufacturing cost. The through-hole is reliably protected against the water-resistant liquid, while eliminating a conventional process of masking the through-hole.

Abstract: The device has a package with a base plate, and at least two terminal pins perpendicularly protruding from the base plate of the package. At least one of the terminal pins is a high-frequency terminal pin that transmits a high-frequency signal. The device has a flexible conductor arrangement with a plurality of interconnects. The conductor arrangement provides an electrical connection between the terminal pins of the package and electrical contacts of a printed circuit board. The conductor arrangement has contact regions for electrically connecting the interconnects to a terminal pin and to a contact of a printed circuit board. At least the region of the conductor arrangement that provides a connection to high-frequency terminal pin lies in a plane aligned substantially perpendicular to the plane of the base plate.

Abstract: A reliable microchip controller board and a manufacturing method thereof suitable for mass production are provided. A board wherein a programmable microchip controller is mounted includes; terminals for writing a program into the microchip controller and a circuit pattern connecting an operating terminal to shared terminals which are disconnected. A non-programmed microchip controller is mounted on the board in a state where patterns are disconnected and then programmed. The disconnected portion is connected thereafter.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A semiconductor device has a plurality of first pads to a plurality of fourth pads laid out in a first direction, thereby forming first to fourth pad rows. The first to fourth pad rows are laid out in the named order in a second direction orthogonal to the first direction. First to fourth leads are respectively connected between the first to fourth pad rows and a semiconductor chip. A first slanted side inclined to the first direction is formed at each second pad at that corner which lies on that side of the third pad row. A second slanted side inclined to the second direction in such a way as to face the first slanted side is formed at each third pad. Each first lead has a first slanted portion provided between the first slanted side and the second slanted side and extending in a direction oblique to the first direction.

Abstract: A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Abstract: A technique has been developed whereby crosstalk induced in a first electrical connection by current flow at an adjacent second electrical connection is at least partially cancelled by an opposing crosstalk signal induced at an inductive coupling between electrical traces extending from or toward the first and second electrical connections, respectively. Crosstalk cancellation is provided by orienting the electrical traces such that current flow through the second electrical connection and respective electrical trace induces an opposing crosstalk signal at the inductive coupling. In some configurations, an inductive coupling between electrical traces includes essentially parallel portions of the traces and an aperture in a voltage plane. In some configurations, cancellation of crosstalk induced by multiple adjacent electrical connection is provided. Crosstalk inducing electrical connections include pins, solder bumps, leads, wires, edge connectors, etc.

Abstract: An electronic apparatus comprises a function module having a multilayer wiring unit including a first signal wiring corresponding to an internal layer wiring, a first signal via, a first reference potential wiring, a first signal pad to which the first signal wiring is connected through the first signal via, a first reference potential pad that surrounds the periphery of the first signal pad and to which the first reference potential wiring is connected, and a first reference potential connected to the first reference potential pad; a inultilayer circuit board; a first conductor; and a second conductor.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device (10) of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10). A metal base (10) can have side portions (12) with connection electrodes (15) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The semiconductor device (10) can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A multilayered substrate includes a plurality of connection point groups, each including connection points. At least two inside conductors are each electrically coupled to inside connection points in at least two connection point groups, wherein each of the inside conductors is substantially equal in length between the inside connection points of adjacent connection point groups which is defined as a inside conductor length. At least two outside conductors are each electrically coupled to outside connection points in at least two connection point groups, wherein each of the outside conductors is substantially equal in length between the outside connection points of the adjacent connection point groups which is defined as an outside conductor length. The inside conductor length is shorter than the outside conductor length.

Abstract: The present embodiments and associated methods provide for an integrated EMI shield for effective shielding not only from emissions perpendicular to the integrated circuit (IC) chip carrier but also parallel (edgewise) to the carrier. In one embodiment, a method includes forming at least a portion of an internal ground layer along at least a portion of a chip carrier edge, applying an electrically conductive layer to at least a portion of the chip carrier edge, the conductive layer being applied over the exposed portion of the ground layer and in electrical contact with said ground layer, and forming at least one cavity within the top surface of the chip carrier, where the at least one cavity configured to hold one or more integrated circuit chips therein.

Abstract: A solder paste contains a solder alloy powder and a metal powder dispersed in a flux. The solder alloy contains Sn and Zn, whereas the metal powder contains at least one element selected from the group consisting of Pd, Ti, and Ni. Preferably, the metal powder is contained in an amount exceeding the solubility limit of the metal powder with respect to the solder alloy at the melting point of the solder alloy powder. The solder paste may be used to form a structure for electrically connecting two objects by interposing a solder layer between their terminals.

Abstract: A printed circuit board having an insulating board and a plurality of wiring patterns formed over the insulating board by screen printing and provided with first conductive pattern bent parts and wiring parts linked to the first conductive pattern bent parts. A pattern width in the first conductive pattern bent parts is greater than that of the patterns of those of the wiring parts positioned close to and on both sides of the first conductive pattern bent parts.

Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.

Abstract: A method of manufacture of a semiconductor device comprises a step of providing an adhesive (30) between a semiconductor chip (20) and a substrate (10), a step of positioning electrodes (22) and leads (12) to oppose each other, and a step of applying pressure in the direction of making the gap between the semiconductor chip (20) and substrate (10) narrower, and on the substrate (10), in a region opposing the surface of the semiconductor chip (20) and avoiding the leads (12), a film (14) is formed with lower adhesion with the adhesive (30) than the substrate (10).

Abstract: A memory architecture includes a first substrate containing multiple memory devices and a first channel portion extending across the first substrate. The architecture further includes a second substrate containing multiple memory devices and a second channel portion extending across the second substrate. A connector couples the first channel portion to the second channel portion to form a single channel. The connector includes a first slot that receives an edge of the first substrate and a second slot that receives an edge of the second substrate. Another connector has a pair of slots that receive opposite edges of the first and second substrates. The channel portions extend across the substrates in a substantially linear path. Each channel portion includes multiple conductors having lengths that are approximately equal.

Abstract: Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.

Abstract: A warpage preventing substrate is provided. A plurality of first and second conductive traces are respectively formed on a first surface and a second surface of a core layer of the substrate, each conductive trace having a terminal, and a plurality of first and second non-functional traces are respectively formed on the first and second surfaces of the core layer at area free of the conductive traces. The first non-functional traces are arranged in different density from the second non-functional traces in a manner that, stress generated from the first conductive traces and first non-functional traces counteracts stress generated from the second conductive traces and second non-functional traces, to thereby prevent warpage of the substrate and maintain flatness of the substrate.

Abstract: A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.

Abstract: A modified connector footprint on a PWB includes a row of ground vias disposed outside a standard connector footprint that do not mate to pins in the connector. The extra ground vias provide additional shielding and reduce cross-talk in the connector/PWB interface.

Abstract: Multilayer printed circuit board includes a core substrate and multilayer wiring layers formed on the core substrate by alternately laminating interlaminar insulating layer and conductor circuit. The multilayer printed circuit board further includes a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers. Solder pads located in at least one and up to five rows from an outer position of the solder pad group have flat pads connected to a conductor pattern located on the outermost surface and have solder bumps formed on surfaces of the solder pads, while solder pads other than the solder pads connected to the conductor pattern on the outermost surface form an inner layer pad group.

Abstract: A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

Abstract: The linearity of a wideband RF power transistor amplifier is improved by including output matching circuit and an integrated bias/RF diplexer with RF and video bypassing capacitor network within the transistor package and connected directly to the transistor. By placing the RF and video bypass power supply circuitry within the package and close to the transistor, the input impedance resonance can be increased from approximately 50 MHz to over 125 MHz, thereby reducing AM/PM distortion in the output signal.

Abstract: A heat sink for a transceiver optoelectronic module including dual direct heat paths and a structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Abstract: An apparatus and method for positioning components on a circuit board and routing traces therebetween is disclosed. The circuit board has two pairs of electrical component-receiving footprint and a plurality of traces interconnecting the footprints. The two pairs of electrical component-receiving footprints are spaced from one another in a first direction, wherein the footprints in each of the pairs are substantially aligned in a second direction substantially perpendicular to the first direction, and wherein at least one of the footprints in one of the pairs is offset from at least one of the footprints in the other of the pairs in both the first and second directions. The plurality of traces interconnect each of the footprints includes at least one trace connecting the offset footprints.

Abstract: In a printed circuit board which has two layers with wiring patterns formed thereon and on which components of a booster circuit that boosts a voltage of an input power are mounted, within a plurality of wiring patterns which connect the input terminal of the input power to the terminal of a component to which the input power is supplied, patterns formed on the two layers are connected by a through hole formed near the input terminal and the terminal of the component. Accordingly, in the patterns to which a relatively large current flows upon receiving the input power, currents flowing to the patterns formed on the two layers are almost uniformed. For this reason, loss due to the wiring resistance in the patterns can be reduced.

Abstract: A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Abstract: The present invention provides a flexible shear-compliant laminate connector having a plurality of contacts formed on a first surface and second surface of the connector, wherein select contacts on the first surface of the connector are off-set from select contacts on the second surface of the connector.

Abstract: A reversible heat sink packaging assembly (400) for integrated circuits is provided. The packaging assembly (400) includes a chip carrier (102) having an opening (104) formed therein and a heat sink (302). The heat sink (302) is attached to one side of a die (304). The die (304) fits into the opening (104) of the carrier (102) with the heat sink (302) abutting one side (208) of the carrier and the die being wire bonded (402) to the other side (108) of the carrier. The packaging assembly (400) can be oriented either device side up or down.

Abstract: A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.

Abstract: A terminal body for use in combination with a circuitboard having edge conductor pads and being formed from a stamped metal blank so as to provide a first main longitudinally extending spring contact which is curved back on itself and inwardly toward the center of the terminal and a pair of stabilizing contacts which oppose and straddle the main contact. All of the contacts are sufficiently resilient to permit the circuitboard of thickness T to be inserted between them, the stabilizing contacts ensuring a firm grip on the circuitboard and non-intermittent contact between the main terminal contact and the circuitboard pad.

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract: A process for forming a circuit pattern on a substrate includes steps of forming a number of electrical circuits on a substrate, which circuits include an electrically conductive bus that interconnects the circuits, covering the electrical circuits with a soldermask, leaving electrical contact portions exposed, electroplating the exposed electrical contacts with a conductive surface finish by using the bus to electrolytically apply the surface finish, and then severing the bus at locations between circuits so that the circuits are electrically isolated from each other. The process may be used to make circuit boards and especially integrated circuit packages.

Abstract: An interconnected mesh plane system includes at least a pair of adjacent metal layers separated by dielectric, each layer having a plurality of spaced power, ground, and signal conductors extending in the same direction, with the conductors of one layer of the pair transverse to the conductors of the other layer, and with conductors of one layer connected to corresponding conductors of the other layer. The width of at least one signal conductor is increased to reduce signal loss, and the width of spaces between such a signal conductor and adjacent power and/or ground conductors is increased to provide a predetermined desired characteristic impedance of a transmission line that includes such a signal conductor.

Abstract: A method and structure are provided for implementing enhanced differential signal trace routing in a printed circuit board. The structure includes a differential signal trace pair and a differential pair via arrangement including a pair of vias. The pair of vias is coupled to the differential signal trace pair for routing the differential signal trace pair between first and second layers of the PCB. The vias are laterally offset by a predefined spacing sharing overlapping clearance holes and are diagonally oriented to allow minimal separation of the differential signal trace pair and matched signal trace lengths of the differential signal trace pair.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit that can be mounted to a circuit board.

Abstract: There in provided a circuit board including a substrate on which a plurality of screen-printed patterns are formed. Each of the screen-printed includes at least one of a passive device and an active device. A gap disposed between the plurality of screen-printed patterns is not more than 40 &mgr;m.

Abstract: A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed to the bottom of the recess. Input and output terminals of the electronic component are connected to electrode pads of the wiring board exposed within the window using wire bonding. A metal lid is bonded to the top surface of the metal substrate to close the opening of the recess. Electromagnetic waves generated by the electronic component are confined to the electronic device because the electronic device is surrounded by the metal substrate, the metal lid, and a ground electrode disposed on the wiring board. Heat dissipation performance is assured because the electronic component is connected to the metal substrate.

Abstract: A mounting substrate on which a semiconductor element is to be mounted by flip-chip bonding, the semiconductor element having a surface on which a plurality of electrode terminals are arranged in a line, each of said electrode terminals having a protruded electrode formed thereon, wherein the surface of the mounting substrate on which the semiconductor element is to be mounted is provided with a protective film having an opening corresponding to an area of the semiconductor element where the protruded electrodes are located, a plurality of connection electrodes being arranged in the opening, the connection electrodes being provided with a solder for bonding it to the protruded electrodes, and being arranged at the same interval as that of the protruded electrodes, and each of the connection electrodes being connected to a wiring pattern of the mounting substrate, and wherein the length of a portion of the connection electrode from the center of the opening to the end thereof that is not connected with the wir

Abstract: A wiring substrate for a display panel having a plurality of wiring electrodes thereon includes an airtight container formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes. The airtight container has an image forming member therein, in which an average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while an average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.