Abstract: A solution for mounting decoupling capacitors on a printed wiring board (PWB) used for mounting a high performance ball grid array (BGA) device is described. The via array that connects the BGA device is modified, the modification being that at least a portion of one row of said vias array is missing at least two adjacent vias. The missing vias are replaced by respective shared vias in an adjacent row, and the shared vias are connected to either a power supply or a power return. The shared vias are also provided with via pads on the other side of said PWB, and a decoupling capacitor can be electrically connected across the pair of via pads to decouple the power supply and the power return at the two adjacent vias.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: A pad for soldering a contact of a surface mounted component is provided herein. The pad includes a central portion and a plurality of separate extending portions extending from the central portion. All of the plurality of separate extending portions includes a free end and a connected end connected to the central portion. A width of the free end is larger than a width of the connected end. A circuit board and an electronic device are also provided.

Abstract: A control module includes a control circuit unit and a wiring unit contained between a cover and a base. The wiring unit has a resin molded part formed by resin-molding nearly central portions of bus bars. The base is shaped to be in contact with the cover when they are fitted to each other, and has protrusions each formed to position between the adjacent bus bars in the flexible region. Contact portions between the cover and the protrusions of the base are fixedly bonded to each other.

Abstract: Disclosed herein is a method for forming solder joints including providing a printed circuit board having a first outer surface, a second outer surface opposite the first outer surface, and a plurality of conductive interconnect traces. The printed circuit board supports on the first outer surface at least one electronic component having a plurality of leads, and further includes a plurality of through-hole clusters. Each through-hole cluster is associated with a single lead and includes a central hole portion surrounded by a plurality of other hole portions. A plurality of solder joints is formed by subsequently moving the printed circuit board over a wave soldering tank filled with solder. Each solder joint is formed between a respective lead inserted in the central hole portion of a respective through-hole cluster and a corresponding one of the plurality of conductive interconnect traces.

Abstract: Disclosed herein are a printed circuit board (PCB) and a probe including the same. The probe includes a transducer, a PCB having a pattern part contacting the transducer via face-to-face contact, and a bonding member bonding the transducer to the pattern part of the PCB. The bonding part of the PCB is provided with the pattern part to increase a bonding area of the bonding part and to allow the bonding member to contact not only a metal layer of the bonding part but also an electrical insulation part thereof, thereby improving a bonding force between the transducer and the PCB. As a result, the transducer can be reliably bonded to the PCB, so that performance of the transducer can be prevented from being deteriorated due to defective connection between the PCB and the transducer.

Abstract: An integrated circuit packaging system comprising: forming a substrate including; patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

Abstract: A heat dissipation device includes a heat sink and an LED module attached to the heat sink. The heat sink includes a base and a plurality of fins mounted on the base. A plurality of channels is defined between the fins of the heat sink and slits are defined in two opposite side edges of the base. The slits extend through the base and corresponding fins and cross with corresponding channels. A plurality of grooves is defined in the fins opposite to the LED module. Each of the grooves interconnects corresponding two aligned slits.

Abstract: A lead frame module integrally formed from a single thin metal sheet includes: parallel first and second rails extending in a first direction; and first and second lead frame sets connected to the first and second rails, respectively. The first and second lead frame sets respectively include a plurality of lead frames extending in a second direction perpendicular to the first direction. Each of the lead frames of the first and second lead frame sets has a pair of connecting leads and a pair of packaging leads. Each of the packaging leads is connected to a respective one of the connecting leads. The connecting leads of the lead frames of the first lead frame set are interdigitated with and are connected to the connecting leads of the lead frames of the second lead frame set.

Abstract: An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.

Abstract: A circuit board structure and a method for manufacturing a circuit board structure comprising an electrical component. The method comprises the steps of fabricating a conductive pattern on the surface of an essentially plane-like layer on the back side of the plane-like layer, and forming an electrical contact between at least one electrical component and the conductive pattern.

Abstract: A protective circuit board for a battery pack for controlling charge and discharge states of the battery pack includes an insulation layer and a first signal pattern disposed inside the insulation layer. The circuit can further include a second signal pattern disposed inside the insulation layer. The circuit can include a first dummy pattern spaced from a first side of the first signal pattern and a second dummy pattern spaced from a second side of the first signal pattern.

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract: An electrical connector includes a housing and a plurality of contacts within the housing that are configured to engage with mating contacts of a mating connector. The contacts form at least a first differential pair and a second differential pair. The electrical connector also includes a circuit board housed within the housing. The circuit board has a substrate body formed from a dielectric material and includes a first trace electrically coupled to a contact of the first differential pair and a second trace electrically coupled to a contact of the second differential pair. At least one of the first and second traces is an open-ended trace. The circuit board also has a non-ohmic plate that is positioned adjacent to the traces. The plate is positioned to electromagnetically couple the first and second traces to each other and the non-ohmic plate and traces are configured for a desired electrical performance.

Abstract: A transition circuit board for transitioning a cable to a connector is provided. A circuit board has an outer surface with a circuit trace, ground plane and ground link provided thereon. A cable pad and a contact pad are provided at opposite ends of the circuit trace. The ground link is electrically common with the ground plane and is located adjacent to, and separated by a space from, the circuit trace. An insulating coating is provided over at least part of the circuit trace, the ground plane and the outer surface of the circuit board. The insulating coating has a mask aperture there-through exposing an uncoated portion of the circuit trace and the ground link. A conductive jumper material is provided on the uncoated portion of the circuit trace and the ground link to electrically join the circuit trace with the ground plane.

Abstract: A semiconductor device includes: a wiring substrate including multiple connection pads provided on a top surface thereof and multiple lands that are provided on a bottom surface thereof and electrically connected to the corresponding connection pads; a semiconductor chip mounted on the top surface of the wiring substrate and electrically connected to the connection pads; a solder resist deposited on the bottom surface of the wiring substrate and having multiple openings to which the lands are respectively exposed, each of the openings being shifted with respect to a corresponding land of the lands; multiple external terminals connected respectively to the lands through the openings; and a dummy wiring arranged on the bottom surface of the wiring substrate and separately from the corresponding land so that a corresponding external terminal of the external terminals is connected to the corresponding land and the dummy wiring partially exposed to the corresponding opening.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.

Abstract: A printed circuit board includes at least two conductive traces, each having a first portion and a second portion. The printed circuit board also includes a cross-over section that includes two electrically conductive portions, each connecting electrically to the first and second portions of a corresponding one of the conductive traces, such that the conductive traces in their first portions lie on opposite sides of each other as they do in their second portions.

Abstract: A wired circuit board includes a wiring formation portion, a terminal formation portion, and a middle portion formed therebetween. The wiring formation portion includes a first conductive layer formed on a first insulating layer, and a second conductive layer formed on a second insulating layer so as to overlap the first conductive layer in a thickness direction. The terminal formation portion includes the first and second conductive layers formed in parallel in the same plane. The middle portion includes the first conductive layer formed on the first insulating layer, and the second conductive layer formed on a portion of the second insulating layer extending from the wiring formation portion to a mid-point between the wiring formation portion and the terminal formation portion, and formed on a portion of the first insulating layer extending from the mid-point to the terminal formation portion.

Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.

Abstract: A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Abstract: A contact tail for an electronic component useful for attachment of components using conductive adhesive, which may be lead (Pb)-free. The contact tail is stamped, providing a relatively low manufacturing cost and high precision. The contact tail has a distal portion with a large surface area per unit length. The distal portion shapes conductive adhesive into a joint, holding the adhesive adjacent the lead for a more secure joint. Additionally, the distal portion holds adhesive to the contact tail before a joint is formed, facilitating the use of an adhesive transfer process to dispense adhesive. To further aid in the transfer of adhesive, the contact tail may be formed with concave portions, which increase the volume of adhesive adhering to the contact tail. By adhering an increased but controlled amount of adhesive to the contact tail, arrays of contact tails may be simply and reliably attached to printed circuit boards and other substrates.

Abstract: A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A system, method and apparatus is provided for extended universal serial bus connectivity. In one embodiment, the invention is an apparatus. The apparatus includes a printed circuit board having a plurality or traces. The plurality of traces includes a first set of traces defining a universal serial bus. The first set of traces is routed between a connector site and an interface circuitry site. The plurality of traces also includes a second set of traces. The second set of traces defines extended signals of the universal serial bus. The second set of traces is routed between the connector site and the interface circuitry site.

Abstract: There is provided an LED lamp unit comprising an LED lamp, a protective component for an LED lighting circuit, a circuit section and a case part, characterized in that the circuit section has a metal plate which is embedded in the case part with its surface partially exposed, a lead of the LED lamp is electrically connected to the exposed surface of the metal plate, and the protective component for the LED lighting circuit is connected to the metal plate at an opposite side to a side where the lead of the LED lamp is connected.

Abstract: A printed circuit board having a pattern of fiducial marks on opposed edges of the board for assuring accuracy and alignment of an electrical connector printed on the board. The fiducial marks are printed as staggered indicia extending orthogoral to the printed contact row array of the electrical connector so that when the board is cut or routed, an inspection process can determine if the physical edges of the board, which determine the pin alignment with a mating receptacle, are within specification.

Abstract: A printed circuit board is fabricated so contacts for tight-pitch components are at an angle with respect to the bundles of glass fibers in the epoxy-glass printed circuit board such that adjacent component contacts do not contact the same bundle of glass fibers. This angle may be accomplished by manufacturing a printed circuit board panel with the glass fibers at an angle with respect to its edges. This angle may also be accomplished by placing parts on a printed circuit board panel that has a traditional X-Y orthogonal weave of glass fiber bundles at an angle with respect to the edges of the panel. This angle may also be accomplished by starting with a traditional panel that has an X-Y orthogonal weave, laying out parts on the panel along the X-Y weave, then placing components on the parts at an angle with respect to the edges of the parts.

Abstract: The invention provides a multilayer printed wiring board including: a power supply wiring layer and a ground wiring layer provided so as to oppose each other via an insulation layer; mounted integrated circuits; and decoupling capacitors mounted in proximity to the integrated circuits and connected between the power supply wiring layer and the ground wiring layer to absorb noise from the integrated circuits. The power supply wiring layer includes through holes for connecting the decoupling capacitors to the power supply wiring layer and has a polygonal form formed by straight lines which link some of the through holes.

Abstract: The invention relates to a device (1), in particular an intelligent power module. Said device comprises a power component (3,4) and a control circuit for controlling the power component (3), said component and circuit being located on a substrate (2). A connection between the power component (3) and the control circuit contains a layer consisting of an electrically insulating material, said layer being located on the power component and the substrate (2) and a layer of electrically conductive material, which is located on the layer of electrically insulating material. The invention thus provides an intelligent power module (1), which can be produced in a more cost-effective and compact manner.

Abstract: A wiring board according to the present invention includes: an insulating base 22; a plurality of first conductor wirings 23a aligned in an inner region on the insulating base; bumps 24 formed on the respective first conductor wirings; and a protective film 25a that is formed on the insulating base so as to cover the first conductor wirings and has an opening region through which the bumps are exposed. The height of at least part of a surface of the protective film from a surface of the insulating base is greater than the height of the bumps from the surface of the insulating base. With this configuration, it is possible to decrease the thickness in the state where a protective tape is placed on the wiring board to protect bumps, thereby increasing the length of the wiring board that can be held by a reel for supplying the wiring board.

Abstract: Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

Abstract: A biosensor that has a smart card configuration includes a semiconductor chip including a bioactive structure and contact areas disposed on a first side of the semiconductor chip, and a rewiring substrate including contact pads, external contact areas and rewiring lines that electrically connect the contact pads to the external contact areas. The rewiring substrate covers a portion of the first side of the semiconductor chip without covering the bioactive structure, such that the rewiring substrate overlaps the contact areas of the semiconductor chip and the contact pads and the contact areas are aligned with and electrically connect to each other. In addition, a measuring apparatus is configured to receive the biosensor and conduct measurements of a fluid medium that is delivered into the measuring apparatus.

Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.

Abstract: According to the invention, information processing equipment using a flexible printed-circuit board which does not lose bendability with repeated opening and closing of a display unit, and which suppresses radiation noise from signal wiring is provided. In the configuration of the invention, a first cover film is formed to cover a wiring layer on a first surface of a base film, and a second cover film is formed to cover a wiring layer on a second surface of the base film. Portions of the second cover film and the underlying wiring layer on the second surface in the loop formation region are discontinuously removed in the inward-bending area of the loop, and the base film is exposed in the removed parts. The wiring layer underneath the remaining second cover film, which is not removed, and the wiring layer on the first surface of the base film are electrically connected via through holes penetrating the base film.

Abstract: A package structure including a first carrier, a second carrier, at least a first electronic component and at least a second electronic component is provided. The second carrier is electrically connected to the first carrier. The first electronic component is disposed on the first carrier and electrically connected to the first carrier. The second electronic component is disposed on the second carrier and electrically connected to the second carrier.

Abstract: A stackable semiconductor package includes a top package, a bottom package, an adhesive layer, a plurality of wires and a molding compound. A part of a surface of a chip of the bottom package is exposed. The top package is inverted, and is adhered to the chip of the bottom package with the adhesive layer. The wires electrically connect a substrate of the bottom package and a substrate of the top package. The molding compound encapsulates the top package, the bottom package, the adhesive layer,and the wires, and exposes a part of a surface of the substrate of the top package. Thus, the stackable semiconductor package includes at least two chips, thereby increasing the chip density and improving the applicability.

Abstract: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.

Abstract: In a structure for mounting a first feedthrough capacitor and a second feedthrough capacitor on a mounting surface of a substrate, the first and second feedthrough capacitors are disposed so as to be substantially parallel and to face each other in their partial regions, and a current in the partial region of the first feedthrough capacitor flows in a direction opposite to that in the partial region of the second feedthrough capacitor.

Abstract: A stacked microelectronic assembly includes a base substrate having conductive elements projecting from a bottom surface thereof and a first microelectronic subassembly underlying a bottom surface of the base substrate. The first microelectronic subassembly includes a first dielectric substrate, a first microelectronic element connected with the first dielectric substrate and first conductive posts projecting from the first dielectric substrate toward the bottom surface of the base substrate for electrically interconnecting the first microelectronic element and the base substrate. The assembly also has a second microelectronic subassembly overlying the base substrate. The second microelectronic subassembly includes a second dielectric substrate, a second microelectronic element connected with the second dielectric substrate and second conductive posts projecting toward the top surface of the base substrate for electrically interconnecting the second microelectronic element and the base substrate.

Abstract: According to one embodiment, a circuit board carries thereon a connection pattern for the connection of a PC card receptacle selectively mounted in a mounting area, a connection pattern for the connection of an Express card receptacle, and a connection pattern for the connection of a smartcard receptacle. An end portion of the smartcard receptacle overlaps the connection pattern for the Express card receptacle. Therefore, the smartcard receptacle is connected to the connection pattern for the smartcard receptacle through a flexible printed wiring element and a connector with the connection pattern shifted to a position between the two connection patterns.

Abstract: Disclosed is a printed wiring board comprising an insulating layer having a rectangular flat shape and provided with fibers in the layer, the direction of the fiber in the layer being almost parallel to any side of the rectangle, a reference potential layer disposed on one surface side of the insulating layer, a plurality of wiring patterns for signal transmission disposed on the other surface side of the insulating layer so as to have nearly similar angles respectively with respect to the direction of the fiber in the insulating layer, and a pad portion to mount a semiconductor device, disposed on the other surface side of the insulating layer to conduct the plurality of wiring patterns.

Abstract: A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on.

Abstract: An optoelectronic system includes a printed circuit board having a ground pad and a bond pad as well as an optoelectronic element. The optoelectronic element is electrically connected to the bond pad via a bonding wire and is additionally fastened to the ground pad by a soldering connection. The ground pad is arranged such that one part of the space between the printed circuit board and the optoelectronic element is not filled with solder. Furthermore, a method is for manufacturing such an optoelectronic system.

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 ?m. The reason is as follows. If the diameter of the mesh hole is less than 75 ?m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 ?m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 ?m. The reason is as follows. If the distance is less than 100 ?m, the solid layer cannot function. If the distance exceeds 2000 ?m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract: According to one embodiment, first to fourth pads are arranged on a surface mounting area of a printed circuit board along one side of the mounting area, with a preset gap defined between each pair of adjacent ones of the pads. The first to third pads form a first land, and the second to fourth pads form a second land. When a first three-terminal regulator IC is mounted on the first land, a radiator-side terminal pin incorporated in the regulator IC is connected to a first radiator pad and a common radiator pad. When a second three-terminal regulator IC is mounted on the second land, a radiator-side terminal pin incorporated in the regulator IC is connected to a second radiator pad and the common radiator pad.

Abstract: In a circuit board device having an electronic component mounted on an electrode land on a board by reflow soldering, voids that adversely affect the solder joint in various ways are prevented from forming. The electrode land corresponding to a component electrode for the electronic component is divided into a plurality of land regions by solder resist having a prescribed width. The component electrode is laid above the solder resist so as to form a clearance communicating with the outside of the component electrode, so that gas generated by vaporization of a flux component contained in the solder during reflow-heating is passed through the clearances and let out of the component electrode. In this way, voids in the solder part can more readily be prevented from forming without increasing the number of person hours as compared to the conventional method.

Abstract: A flexible printed circuit board includes a flexible base, a working trace region, and at least one reinforcement trace. The working trace region and the at least one reinforcement trace are formed on the flexible base. The working trace is formed by a number of working traces. In the flexible base, the at least one reinforcement trace is disposed at a periphery of the working trace region.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.