Abstract: A semiconductor package includes: a semiconductor substrate; an inner insulator layer formed on the substrate; at least one internal wiring extending from a front side of the substrate along one of lateral sides of the substrate to a rear side of the substrate; a first outer insulator layer disposed at the front side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole; and a second outer insulator layer disposed at the rear side of the substrate, formed on the internal wiring, and formed with at least one wire-connecting hole which exposes a portion of the internal wiring.

Abstract: A multilayer wiring board having a structure in which wiring layers 12A to 12D and insulating layers 11A to 11C are alternately arranged, and in which one or plural kinds of wirings selected from a group of a signal wiring 25 having a signal electrode 15, a power supply wiring 26 having a power supply electrode 16, and a ground wiring 27 having a ground electrode 17 are formed on each of the wiring layers 12A to 12D. The signal wiring 25 and the power supply wiring 26 are alternately provided on the insulating layers. Alternatively, the signal wiring 25 and the ground wiring 27 are alternately provided on the insulating layers.

Abstract: A printed board includes footprints which are electrically solder-bonded to a surface-mounting substrate, on which electronic components are mounted, and which assists the heat release from the surface-mounting substrate. The footprint comprises a fillet-forming division which is placed on an outer-edge side of the surface-mounting substrate and where solder is supplied independently when solder-bonding is performed. The fillet-forming division is solder-bonded to the same electrode as the electrode of the surface-mounting substrate to which the footprint is solder-bonded.

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.

Abstract: A substrate panel primarily comprises a plurality of substrate strips arranged in an array, one or more current input lines, a plurality of cascaded lines connecting between the substrate strips, and a current input buffer gate. Current input lines connect a current input side of the substrate panel to the adjacent substrate strips. The current input buffer gate has a frame around the substrate strips and a plurality of meshes where the frame intersects with the current input lines and the meshes intersect with the cascaded lines with both ends of the meshes connecting to the frame. Therefore, the current can be evenly distributed to each substrate strip during plating processes to improve the issues of different plating thicknesses and different plating roughness caused by different current densities and to protect the internal circuits inside the substrate strips from the damages due to current surges and unstable voltages.

Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.

Abstract: A method of fabricating a rechargeable battery having an electrode assembly, a PCB and a battery case, wherein the electrode assembly is connected to the PCB, the method including preparing a PCB having a first surface with an external contact terminal formed thereon and having a second surface with a conductive feature formed thereon, wherein the conductive feature is electrically connected to the external contact terminal through a conductive trace, and plating the external contact terminal by electrically connecting a plating electrode to the conductive feature.

Abstract: An information processing apparatus including: a main unit; a cooling fan that suctions open air into the main unit to cool inside the main unit with an air flow; and a nonvolatile semiconductor storage device that is provided within the main unit to be used as an external storage device, the device including: a printed circuit board; a nonvolatile semiconductor memory that is mounted on the printed circuit board; a memory controller that is mounted on the printed circuit board and controls the nonvolatile semiconductor memory; and a temperature sensor that is mounted on the printed circuit board and detects temperature within the nonvolatile semiconductor storage device, wherein the memory controller is disposed at an upstream side of the air flow and the temperature sensor is disposed at a downstream side of the air flow.

Abstract: A printed circuit board includes a base and a signal trace laid on the base. The signal trace includes a plurality of straight line segments parallel to the first fibers. The signal trace is laid on the base in such a manner that the line segments of the signal trace mapped on the base partly superpose the first fibers and partly superpose gaps between two adjacent first fibers.

Abstract: An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract: A circuit arrangement for buck converters has a multiplicity of half bridges (10, 11). Each half bridge (10, 11) contains a first chip (HS1, HS2, HS3, HS4) and a second chip (LS1, LS2, LS3, LS4) , the first chip (HS1, HS2, HS3, HS4) and the second chip (LS1, LS2, LS3, LS4) in each case having a vertical power transistor. The load paths of the power transistor of the first chip (HS1, HS2, HS3, HS4) and of the power transistor of the second chip (LS1, LS2, LS3, LS4) are connected in series. The control inputs (G1, . . . , G8) of the power transistors can be driven individually. The half bridges (10, 11) are jointly accommodated in a semiconductor package and the first chip (HS1, HS2, HS3, HS4) and the second chip (LS1, LS2, LS3, LS4) lie above one another in each half bridge (10, 11).

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: An electrical connection board includes electrical connection terminals on one face with a view toward connecting with a semiconductor component and electrical connection tracks connected respectively to these terminals. The terminals are arranged in a square matrix having two orthogonal directions. On its face, the board includes a multiplicity of identical adjacent connection groups, each group having N adjacent terminals and N tracks placed along this direction while extending towards an edge of the matrix. The terminals of a group are offset by one pitch relative to the terminals of an adjacent group. The board and a semiconductor component are connected together by electrical connection balls.

Abstract: A printed circuit board includes an insulated base sheet, a heat-conducting layer, and a plurality of heat-conducting blocks. The heat-conducting layer is disposed on the insulated base sheet. The heat-conducting blocks are formed on the heat-conducting layer. Each of the heat-conducting blocks is separated from each other.

Abstract: In the case where a printed board is contained in a casing of an electrical junction box, and where electrical components such as relays disposed on the printed board are connected to a bus bar disposed in the casing, a heat generated in the bus bar is uniformed in the casing without causing an uneven heat distribution around the bus bar, thereby requiring no means for radiating the bus bar. An electrical junction box including a casing, a printed board contained in the casing, an insulation plate disposed on the printed board, a bus bar mounted on the insulation plate, and a relay mounted on the printed board. The bus bar is provided with an electrical power source terminal to be connected to an electrical power source side. Branched portions provided on the bus bar are connected to a conductor on the printed board, respectively. A terminal of the relay is connected to the printed board conductor connected to the branched portions of the bus bar.

Abstract: A cable with conductive bumps is fabricated by forming a photoresist layer with multiple openings on a cable substrate, coating a conductive layer on the photoresist layer whereby the conductive layer in the openings forms the bumps at circuits on the cable substrate, and then removing the photoresist layer. When connecting the cable to a task object such as an LCD glass substrate or PCB, only a usual non-conductive paste is applied to join the cable and the task object, without use of expensive anisotropic-conductive paste or film.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.

Abstract: A signal transfer member for a liquid crystal display (LCD) apparatus includes a power line for receiving power from an external source and for driving a semiconductor chip disposed on the transfer member or the display apparatus. The power line is bent so as to incorporate a serpentine structure, which enables the length of the power line to be easily adjusted and results in the line being longer than a power line formed with a relatively straight structure. Accordingly, the length of the power line can be adjusted to take into account the respective impedances of the chip and the external source so as to suppress electromagnetic waves in the power line. This prevents the creation of noise, distortion of signals, damage to the semiconductor chip, and disconnection of the input interconnection thereof that are caused by the electromagnetic waves, so that product yields are thereby improved.

Abstract: An exemplary semiconductor die package is disclosed having one or more semiconductor dice disposed on a first substrate, one or more packaged electrical components disposed on a second substrate that is electrical coupled to the first substrate, and an electrically insulating material disposed over portions of the substrates. The first substrate may hold power-handling devices and may be specially constructed to dissipation heat and to facilitate fast and inexpensive manufacturing. The second substrate may hold packaged components of control circuitry for the power-handling devices, and may be specially constructed to enable fast and inexpensive wiring design and fast and inexpensive component assembly. The first substrate may be used with different designs of the second substrate.

Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.

Abstract: An electronic device is provided. The electronic device includes: a circuit board having a surface on which a hollow is formed; an electronic component placed into the hollow; a pattern wiring which is formed on a bottom surface of the hollow and whose tip is provided at a position corresponding to a signal electrode of the electronic component; a signal wire connecting a tip of the pattern wiring and the signal electrode of the electronic component; two in-hollow ground patterns formed so as to sandwich the tip of the pattern wiring therebetween on the bottom surface of the hollow; and two or more ground wires that connect two ground electrodes provided on the electronic component so as to sandwich the signal electrode therebetween to the corresponding in-hollow ground patterns, respectively.

Abstract: A material board for producing a hybrid circuit board includes a plurality of hybrid circuit board sections 1 on each of which an electronic component 2 is mounted and a metallic terminal plate 3 for external connection is bonded so as to project from the hybrid circuit board section. A frame portion 6 is defined between the hybrid circuit board sections, and the hybrid circuit board sections are integrally connected to the frame portion via a thin strip 8 provided at an intermediate portion of grooves 7 each surrounding a respective one of the hybrid circuit board sections entirely. In bonding the terminal plate 3 to the hybrid circuit board by soldering, the terminal plate is temporarily bonded to the frame portion 6 with an adhesive 9. The adhesive is prevented from spreading toward the end of the terminal plate.

Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.

Abstract: A flexible wiring cable includes a flexible flat base, and a plurality of first and second leads wired on first and second surfaces of the base respectively. First and second circuit elements are mounted on the first and second leads respectively. A plurality of terminal electrodes is provided on the first surface of the base. The terminal electrodes include a plurality of first terminal electrodes formed on the first leads and a plurality of second terminal electrodes formed on the second leads, being exposed to the outside of the first surface side via through holes formed in the base.

Abstract: A circuit substrate ready to slot is revealed, primarily comprising a board base with slot-reserved area. A plurality of bonding fingers, a plating bus loop, and a plurality of plating lines disposed on the bottom surface of the board base. The bonding fingers are located adjacent to but outside the slot-reserved area and the plating bus loop is located inside the slot-reserved area. The plating lines connect the bonding fingers to the plating bus lines. The plating bus loop includes two side bars closer to the long sides of the slot-reserved area than the bonding fingers to the long sides. Accordingly, the lengths of the plating lines within the slot-reserved area are shortened. It is possible to solve the issues of metal burs and shifting of the remaining plating lines when routing a slot along the peripheries of the slot-reserved area. Moreover, the plating current can evenly distribute to improve the plating qualities on the surfaces of the bonding fingers.

Abstract: Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage.

Abstract: A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins.

Abstract: The present invention provides a circuit board and a method for manufacturing the circuit board, the circuit board and method allowing a further shorter connection distance between electrodes of a semiconductor device, and also allowing a sufficient thickness of a solder pre-coat in a soldering process. The circuit board comprises bonding pads for being connected with bumps of a semiconductor element, which act as connection terminals, the bonding pads being arrayed in parallel lines on a surface of the circuit board, and, on the adjacent parallel lines, the bonding pads being positioned to form a zigzag pattern along the parallel lines longitudinally.

Abstract: A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A semiconductor integrated circuit device described herein includes a semiconductor chip and a package on which the semiconductor chip is disposed. The semiconductor chip includes first electrode pads, and the package includes second electrode pads connected to the first electrode pads. The second electrode pads include signal pads and power supply pads, and are arranged in rows along the semiconductor chip. All the power supply pads of the second electrode pads are for supplying power to the semiconductor chip and are disposed in a row positioned farther from the semiconductor chip than another row. Each power supply line that leads out from a second power supply pad has a width not less than a width of the second power supply pad.

Abstract: An intra-connection layout of array is disclosed. An alterable area is disposed between the devices of a device array. The alterable area includes an insulation layer, a plurality of first conductive wires and a plurality of second conductive wires. The first conductive wires are disposed within the alterable area along a first direction for selectively connecting electrical paths in the first direction between different devices. The second conductive wires are disposed within the alterable area along a second direction for selectively connecting electrical paths in the second direction between different devices. The insulation layer is disposed within the alterable area and between the above-mentioned first conductive wires and second conductive wires, wherein the insulation layer has an opening to allow one of the first conductive wires and one of the second conductive wires to be contacted with each other.

Abstract: The embodiments described herein provide for a packaging configuration that provides leads or connections for a packaging substrate from opposing surfaces of a package. Through silicon vias (TSV) are provided in order to accommodate additional input/output (I/O) pins that smaller dies are supporting. Various combinations of packages are enabled through the embodiments provided.

Abstract: A substrate with plane patterns formed in a liquid process wherein the plane patterns are formed based on a combination of plane shapes by which a difference in internal pressure of a solution between any two points of the solution is small, the solution being ejected onto the substrate so as to form the plane patterns by the liquid process.

Abstract: A system in package integrating a plurality of semiconductor chips, including a first chip mounted commonly in a plurality of system in packages and at least including a CPU, a second chip having a different specification for each of the plurality of system in packages depending on a connection of internal lines, and a module substrate including the first chip and the second chip adjacent to each other and having a shape common to the plurality of system in packages. The first chip includes a first module connection terminal on the first chip along a first side facing the second chip or in an area different from the first chip and facing the second chip. A second side of the second chip includes a second module connection terminal to be connected with the first chip. The first and the second module connection terminals are connected by a bonding wire.

Abstract: A wiring board of the present invention includes a dummy wiring in a semiconductor-chip mount area on which a semiconductor chip is to be mounted. The dummy wiring is arranged in a manner such that all wiring-lines included in the dummy wiring each have a free end within the semiconductor-chip mount area. This prevents a defect due to vaporization and expansion of moisture inside a semiconductor apparatus, with a simple structure and without raising costs.

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Abstract: A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.

Abstract: An embodiment of a printed circuit board according to the present invention is provided with an insulating layer, a conductive layer that is laminated on the insulating layer and that has a connecting portion and a circuit pattern portion formed connected to the connecting portion, and a film cover layer that covers the insulating layer and the conductive layer via an adhesive layer and that has an opening for connecting a mounted component to the connecting portion. The circuit pattern portion is provided with a recessed portion that is concave with respect to the connecting portion.

Abstract: An exemplary FPCB includes a differential pair consisting of a first transmission line and a second transmission line, a signal layer with the first transmission line arranged therein, a ground layer having a void which includes the area beneath the first transmission line, and a dielectric layer lying between the signal layer and the ground layer. The second transmission line is arranged in the ground layer offset from the first transmission line in the horizontal direction. The FPCB can transmit high speed signals.

Abstract: A structure for mounting a compound circuit on a circuit board is provided. The compound circuit includes a high voltage circuit and a low voltage circuit whose supply voltages are different from each other. The structure includes: a main circuit board on which constituents of the low voltage circuit are mounted; and a hybrid IC which includes a sub circuit board on which at least a part of constituents of the high voltage circuit is mounted and a moisture preventing agent coating the sub circuit board, and is arranged over the main circuit board. Both an insulation distance between terminals provided on the main circuit board for connecting to the hybrid IC and an insulation distance between terminals provided on the hybrid IC for connecting to the main circuit board are larger than a minimum insulation distance between terminals provided on the constituents mounted on the sub circuit board.

Abstract: A land pattern, a method of manufacturing a printed circuit board (PCB) and a PCB incorporating a land pattern. In one embodiment, the land pattern includes: (1) a quadrilateral component outline area having diagonally opposed first and second corners and diagonally opposed third and fourth corners, defined according to a body configuration of a particular component type and located on a surface of a substrate and (2) first and second exposed conductive pads located within said area respectively proximate said first and second corners, coupled to respective first and second circuit conductors of said substrate, configured according to a terminal configuration of said type and separated from said third and fourth corners such that a component of said particular component type may be placed on the land pattern in multiple orientations without causing a short circuit.

Abstract: A printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Because the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: A sensor device includes a communication line having a high-level line and a low-level line, and printed wiring layers. The printed wiring layers are connected to the communication line so as to have a differential communication with an electronic control unit of an occupant protection system. First and second layers are ungrounded, and have a low-level conduction pattern connected to the low-level line and a circuit element having a standard corresponding to the low-level line. Third printed wiring layer is arranged between the first and second layers through insulations, and has a high-level conduction pattern connected to the high-level line.

Abstract: A conductive line pattern of a pad area includes a plurality of terminals arranged side by side. Each terminal includes an opening portion with a side edge and a line portion connecting with the side edge of the corresponding opening portion. The relative position of each line portion and the corresponding opening portion varies according to the location of the terminal in the pad area.

Abstract: An electronic device and method of fabrication are provided. The electronic device comprises a substrate, a patterned conductive layer serving as an antenna layer formed on the outer surface of the substrate, electrically connected with a printed circuit board (PCB) for sending or receiving a wireless signal, wherein the substrate is placed between the patterned conductive layer and PCB. The patterned conductive layer may be electrically connected to the PCB through a hole in the substrate by a connecting piece. The substrate may be a housing of the electronic device.

Abstract: A semiconductor device includes a terminal case containing a semiconductor element, a plurality of pin terminals of equal length mounted in the terminal case and electrically connected to the semiconductor element, the plurality of pin terminals projecting outward from a predetermined surface of the terminal case in the same direction, and at least one protruding pin terminal mounted in the terminal case and projecting outward from the predetermined surface of the terminal case in the same direction farther than the plurality of pin terminals.

Abstract: LED mounting arrangements are described which provide flexibility for LED users to mount a first LED having different physical, electrical, thermal, or other characteristic footprints from those for a second LED on a mounting pad designed for the second LED. With such arrangements, migration from one LED to another can be facilitated without the need for redesigning the printed circuit board for a lighting application. Flexibility is thereby provided to LED customers.

Abstract: A circuit module containing a ceramic carrier substrate to carry electronic parts, ceramic substrate pads provided on a surface of the ceramic carrier substrate, and a lid having a cavity and a bottom surface joined to the ceramic substrate pads with solder, the lid being a stepped lid having protrusions adjacent to the cavity, and dents adjacent to the cavity with the protrusions intervening therebetween, the protrusions being in contact with the ceramic carrier substrate with a prescribed distance to the ceramic substrate pads, and the dents being joined to the ceramic substrate pads with solder.