Abstract: Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.

Abstract: Supercapacitor structures are provided which include, for example: one or more layers of supercapacitors; and one or more contact tabs. The one or more contact tabs electrically contact and extend outward from the supercapacitor structure to facilitate electrical connection to the supercapacitor structure, and the one or more contact tabs include a multi-contact tab. The multi-contact tab is configured and sized with multiple contact locations which are disposed external to the supercapacitor structure. Various supercapacitor structures are provided, including one supercapacitor structure with a shared C-shaped current collector, and another supercapacitor structure with stacked supercapacitors. One or more additional multi-contact tabs may also extend from the supercapacitor structure(s) and distribute the same or a different capacitor voltage than the multi-contact tab.

Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract: A Multi-configuration Processor-Memory device for coupling to a PCB (printed circuit board) interface. The device comprises a substrate that supports multiple configurations of memory components and a processor while having a single, common interface with a PCB interface of a printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components can be pre-tested, packaged memory components mounted on the substrate. The processor can be a surface mounted processor die. Additionally, the processor can be mounted in a flip chip configuration, side-opposite the memory components. In the first configuration, a heat spreader can be mounted on the memory components and the processor to dissipate heat.

Abstract: The device includes a first inductor, a first insulating layer, a second inductor, and a third inductor. The first inductor includes a helical conductive pattern. The second inductor is located in a region overlapping the first inductor through the first insulating layer. The second inductor includes a helical conductive pattern. The third inductor is connected in series to the second inductor, and includes a helical conductive pattern.

Abstract: Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Abstract: An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.

Abstract: A microelectronic circuit having at least one component adjacent a carrier which is not a semiconductor or sapphire.

Abstract: A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies.

Abstract: Embodiments of provide an integrated circuit (IC) device. The IC device can include a substrate having first and second opposing surfaces, an IC die electrically coupled to the first surface of the substrate, a plurality of contact members coupled to the first surface of the substrate, and an interposer. The interposer can include a plurality of contact elements located on a first surface thereof, each conductive element being coupled to a respective one of the plurality of contact members, and an antenna formed using a conductive layer of the interposer, the antenna being electrically coupled to the IC die through at least one of the plurality of contact elements and at least one of the plurality of contact members.

Abstract: A circuit board assembly includes metal plates to be used as conducting medium, an encapsulation enclosing therein the metal plates and provided with holes defined in the encapsulation to allow extension of the metal plates out of the encapsulation for electrical connection and electronic components securely mounted on the encapsulation and electrically connected to the metal plates to form a closed loop.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body; an active layer including a plurality of electrodes formed to be alternately exposed to both end surfaces of the ceramic body; an upper cover layer; a lower cover layer having a thickness greater than that of the upper cover layer; and external electrodes, wherein when a distance from an end portion of the lowermost internal electrode of the active layer to an end portion of the external electrode covering a portion of a lower surface of the ceramic body is E, the shortest distance from the end portion of the external electrode to the lowermost internal electrode of the active layer is T, and a margin of the ceramic body in the length direction is F, 1.2?E/T and 30 ?m?F are satisfied.

Abstract: The described embodiments relate generally to a capacitor assembly for mounting on a printed circuit board (PCB) and more specifically to designs for mechanically isolating the capacitor assembly from the PCB to reduce an acoustic noise produced when the capacitor imparts a piezoelectric force on the PCB. Termination elements in the capacitor assembly, including a porous conductive layer in the capacitor assembly may reduce an amount of vibrational energy transferred from the capacitor to the PCB. Termination elements including a soft contact layer may also reduce the amount of vibrational energy transferred to the PCB. Further, capacitor assemblies having thickened dielectric material may reduce the amount of vibrational energy transferred to the PCB.

Abstract: An ultra-wideband assembly is provided. The assembly includes a non-conductive tapered core having a conductive wire wound on an outer surface of the non-conductive tapered core, a low-frequency inductor coupled to the non-conductive tapered core via the distal end of the conductive wire and configured to allow mounting of the non-conductive tapered core at an angle with respect to the circuit board. The low frequency inductor is being disposed on a dielectric board configured to be coupled to the circuit board. The assembly includes an ultra-wideband capacitor coupled to the non-conductive tapered core via the proximate end of the conductive wire, the ultra-wideband capacitor being also coupled to the transmission line on the dielectric board.

Abstract: A connector for connecting surface mount devices, such as light emitting diodes (LEDs), to printed circuit boards (PCBs). The connector may be prepackage with an LED assembly or on a PCB to which the LED assembly will be mounted. Connection complexity can be moved from the PCB to the connector, and LED assemblies may be customized differently for different customers. One to many and many to one connections are readily supported with variations on the connector.

Abstract: A multilayer circuit board (1) includes resin bases (101 to 10N) stacked while placing separators (121 to 12N?1) in between, interconnect patterns (111 to 11N) respectively formed on one surface of each of the resin bases (101 to 10N), and electro-conductive bumps (201 to 20N?1) which electrically connect the interconnect patterns (111 to 11N). The resin bases (101 to 10N) and the separators (121 to 12N?1) are heat-bonded, the separators (121 to 12N?1) are composed of a first thermoplastic resin material having a first glass transition temperature, and the resin bases (101 to 10N) are composed of a second thermoplastic resin material having a second glass transition temperature higher than the first glass transition temperature.

Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.

Abstract: An electronic product includes a case; a first board placed inside the case; and a second board having an Electromagnetic Band Gap (EBG) structure inserted therein. The second board is coupled to an inside of the case facing the first board so as to shield a noise radiated from the first board.

Abstract: In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer. A separator separates the first and second nanostructured substrates and allows ions of an electrolyte to pass through the separator. The structure may be a nanostructured electrolytic capacitor with the first nanostructured substrate forming a positive electrode and the second nanostructured substrate forming a negative electrode of the capacitor.

Abstract: There is provided a multilayer ceramic capacitor including: a ceramic body including a dielectric layer; a first internal electrode having a first non-pattern portion and a first pattern portion having one end exposed to one or more of surfaces of the ceramic body; a second internal electrode having an overlap region with the first pattern portion with the dielectric layer interposed therebetween and having a second non-pattern portion and a second pattern portion having one end exposed to one or more of surfaces of the ceramic body; and first and second external electrodes electrically connected to the first and second internal electrodes, respectively, wherein the first and second pattern portions have a metal oxide region having a predetermined width from an exposed end portion of a region thereof not connected to the first or the second external electrode, among exposed end portions, toward a central portion thereof, respectively.

Abstract: The present invention relates to a flexible modular assembly (100) comprising at least two flexible electronic modules (110 and 111) supported by a textile support (130). The two flexible electronic modules and the textile support each comprise a set of electrical conductors. The flexible modular assembly further comprises flexible connectors (140) for interconnecting two sets of electrical conductors. The flexible modular assembly of the invention is a modular textile assembly for use in large-area applications of electronic textiles.

Abstract: There is provided a stacked-type multilayer ceramic electronic component including: a ceramic body, a plurality of first and second internal, and first and second external electrodes formed on both surfaces of the ceramic element opposing one another; and first and second metal frames disposed to face one another and allowing the first and second external electrodes of the ceramic body to be attached thereto, respectively, wherein two or more ceramic bodies are attached between the first and second metal frames in a length direction of the first and second metal frames with an interval therebetween, and the respective ceramic bodies have different levels of capacitance.

Abstract: There are provided a coil component capable of decreasing leakage inductance and a display device including the same. The coil component includes a cylindrical body part having a plurality of coils wound and stacked on an outer peripheral surface thereof; and one or more spacing parts formed on the outer peripheral surface of the body part to uniformly distribute the coils directly wound on the body part.

Abstract: Disclosed are various embodiments of power source redundancy in a power supply for a rack mounted computing device. The power supply includes a plurality of AC power converters configured to receive power from corresponding power sources. A first AC power converter provides DC power to a common DC bus of the power supply. A second AC power converter provides DC power to the common DC bus in response to a change in the voltage level provided by the first AC power converter.

Abstract: An inductor arrangement comprises a first inductor formed on a substrate, a second inductor formed on the substrate, a first loop formed on the substrate adjacent to the first inductor and a phasing network connected to the first loop which is arranged to receive an input signal representative of a flow of magnetic flux through the second inductor and to apply a first current to the first loop for generating a flow of magnetic flux for reducing magnetic coupling between the second inductor and the first inductor. A second loop can be formed on the substrate adjacent to the second inductor which is arranged to generate a second current in response to a flow of magnetic flux through the second loop, with the second current being the signal representative of a flow of magnetic flux through the second inductor.

Abstract: Data carrier for contactless data transmission comprising a substrate, a chip having at least one connection pad, wherein the chip is arranged by its side remote from the connection pad on the substrate and a first copper-coated prepreg layer is arranged on the chip and at least partly on the substrate and has a contact opening to the connection pad. A plated-through hole is situated within the contact opening for producing an electrically conductive connection between the connection pad of the chip and the copper layer of the first copper-coated prepreg layer, wherein a first antenna structure is formed in the copper layer of the first copper-coated prepreg layer.

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one power feed-through capacitor is provided. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.

Abstract: Methods of making an assembly are disclosed. The assembly may include a circuit board with a top surface and a circuit component mounted on the top surface of the circuit board. The method may include positioning an inductor coil above the circuit component and the top surface of the circuit board and encapsulating the inductor coil, the circuit component and at least part of the top surface of the circuit board in a magnetic material. Assemblies according to such methods are also disclosed.

Abstract: A multilayer substrate is configured by stacking conductive layers and insulation layers. The multilayer substrate includes a core that is one of the conductive layers and is thicker than any of other conductive layers, and a first signal line that is included in the conductive layers and is adjacent to the core so that a first insulation layer that is one of the insulation layers is interposed between the core and the first signal line, the first signal line being used for transmission of an RF signal. The core has a recess portion so as to face the first signal line.

Abstract: An EMI noise shield board, in which an EBG structure is inserted, includes a first board portion and a second board portion. The first board portion has an upper surface, on which an electronic part is disposed, and a circuit for transferring a signal and power to the electronic part. The second board portion is located on a lower surface of the first board portion. The electromagnetic bandgap structure is inserted into the second board portion, and has a band stop frequency property such that an EMI noise transferred from the first board portion is shielded from being radiated to the outside of the EMI noise shield board.

Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.

Abstract: An inductor assembly includes an inductor body including an inductor core and a mounting bracket that includes a first leg, a second leg, and a third leg. A portion of the mounting bracket passes through the inductor body, at least one of the first leg and the second leg of the mounting bracket is arranged to be mounted on a substrate, and the third leg of the mounting bracket is arranged to be mounted on an electrical component mounted on the substrate.

Abstract: There is provided a multilayer ceramic electronic component including: a ceramic body in which a plurality of dielectric layers are stacked; a plurality of first and second internal electrodes formed on at least one surfaces of the dielectric layers and alternately exposed through both end surfaces of the ceramic body in a length direction of the ceramic body; a first acoustic noise absorption layer formed on one surface of the ceramic body in a stacking direction of the dielectric layers and having a thickness of 3 ?m to 500 ?m; first and second external electrodes formed on both end surfaces of the ceramic body and electrically connected to exposed portions of the first and second internal electrodes; and a printed circuit board having the first and second external electrodes mounted thereon while facing the first acoustic noise absorption layer.

Abstract: The described embodiments relate generally to electronic components and more specifically to a capacitor array that can increase component density on a printed circuit board and reduce a distance to a ground plane. An array of capacitors can be formed by coupling a group of capacitors on their sides interspersed with interposer boards. The resulting configuration can increase component density and reduce an amount of resistance and effective series inductance between a set of power decoupling capacitors and an integrated circuit.

Abstract: An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.

Abstract: A printed-circuit board arrangement electrically connects the at least one transmitter and/or receiver unit with at least one antenna element, whereas the at least one transmitter and/or receiver unit and the at least one antenna element are at least partially integrated into the printed-circuit board arrangement. In this context, the printed-circuit board arrangement includes different printed circuit boards, which are mechanically connected to one another in a rigid manner. A first part of the printed-circuit board arrangement is formed by at least one printed-circuit board, of which the substrate is made from a first material which is suitable for high-frequency, and a second part of the printed-circuit board arrangement is formed by at least one printed-circuit board, of which the substrate is made from a second material different from the first material, which is still sufficiently suitable for a low frequency and/or for a direct-voltage range.

Abstract: A through-hole stub AC termination circuit including a resistor and a capacitor, is connected to an open end of a stub of a through-hole provided in a circuit board.

Abstract: An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: A filter circuit 103 includes capacitor elements 121 and 122. The capacitor element 121 returns a common mode current included in a signal output from, a signal output terminal 111 of a semiconductor element 102, to a ground terminal 113 of the semiconductor element 102. The capacitor element 122 returns a common mode current included in a signal output from a signal output terminal 112 of the semiconductor element 102, to the ground terminal 113 of the Semiconductor element 102. The capacitor elements 121 and 122 are arranged such that the mutual inductance between a parasitic inductance of the capacitor element 121 and a parasitic inductance of the capacitor element 122 for the common mode currents is a negative value. Accordingly, the effective inductances of the first and second capacitor elements for the common mode currents are reduced, which suppresses radiation noise.

Abstract: The present invention relates to a method for the production of an expandable circuit carrier in which a starting material for an expandable substrate is applied on an electrically conductive foil which forms an expandable substrate layer which is connected to the foil, after which the foil is structured such that it forms a conductor structure having at least one expandable strip conductor. The present invention further relates to an expandable circuit carrier which can be produced by the method.

Abstract: In a high-frequency switch module, a switch IC is mounted on a multilayer board to define a high-frequency switch module. The multilayer board includes two internal wirings and two internal ground electrodes. The internal ground electrodes are spaced apart from each other at an interval when viewed from a lamination direction of the multilayer board. The first internal wiring is located on the upper surface side of the first internal ground electrode, and is entirely separated from an RF wiring, and the first internal wiring includes a power supply wiring for supplying power to the switch IC. The second internal wiring is located on the upper surface side of the second internal ground electrode, and is entirely separated from the power supply wiring, and the second internal wiring includes a signal wiring through which an RF signal propagates.

Abstract: Disclosed herein is a position indicator that includes: an enclosure forming a hollow and rod-shaped tubular body; a substrate disposed in the hollow portion of the enclosure and having a circuit configured to process signals exchanged with a position detection sensor; and a film-shaped capacitor having first and second conductor layers. The first conductor layer is formed on one side of a sheet-shaped dielectric, and the second conductor layer is formed on another side of the sheet-shaped dielectric and is opposed to the first conductor layer with the sheet-shaped dielectric provided therebetween. The film-shaped capacitor is fastened to the substrate in such a manner as to make up part of said circuit, and the size of an area over which the first and second conductor layers of the film-shaped capacitor are opposed is changeable by changing the size of the film-shaped capacitor to specify a constant for said circuit.

Abstract: The present invention provides a dual chip signal conversion device, comprising: a carrier, one side surface thereof being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact; a first chip disposed at one side surface of the carrier and electrically connected to the second and fourth contacts; a second chip disposed at one side surface of the carrier and electrically connected to the first chip; and an antenna disposed within the carrier and electrically connected to the second chip.

Abstract: A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads.

Abstract: This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

Abstract: Provided is a circuit board including a resin base, and a resistance element formed above the resin base. The resistance element includes a resistance pattern including an electrode portion and an extending portion, and an electrode formed on the electrode portion of the resistance pattern and including a foot portion reduced in thickness toward the extending portion.

Abstract: An assembly carrying a radioisotope power source for attaching to a printed circuit board.