Abstract: An ultra-wideband assembly in an electrical circuit having a circuit board with a conductive micro-strip line is provided. The assembly includes a non-conductive tapered core having an outer surface, a distal end, and a proximate end. The distal end is being larger than proximate end. The assembly includes a conductive wire having a proximate end and a distal end and being wound about at least a portion of the non-conductive tapered core. The proximate end of the conductive wire extends away from the proximate end of the non-conductive tapered core and is being conductively coupled to the micro-strip line of the circuit board. The distal end of the conductive wire extends away from the distal end of the non-conductive tapered core. The conductive wire contacts at least a portion of the outer surface of the non-conductive tapered core. The assembly includes a supporting bracket coupled to the non-conductive tapered core. The bracket includes a base portion and a core attachment portion.

Abstract: A connector for connecting surface mount devices, such as light emitting diodes (LEDs), to printed circuit boards (PCBs). The connector may be prepackage with an LED assembly or on a PCB to which the LED assembly will be mounted. Connection complexity can be moved from the PCB to the connector, and LED assemblies may be customized differently for different customers. One to many and many to one connections are readily supported with variations on the connector.

Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

Abstract: A chip component is provided with a block including a dielectric, input and output terminals, which are the first and second terminals that are provided on the surface of the block, an adjustment terminal that is a third terminal that includes an internal electrode extended into the block and that is provided on the surface of the block, and at least two inter-terminal circuits that are provided in the block and that are connected between at least two sets of two terminals of the first, second, and third terminals.

Abstract: An electronic part module includes a wiring substrate, a passive device group of passive devices formed on the wiring substrate, and device chips mounted on the wiring substrate. Such an electronic part module is made in the following manner. First, a wiring substrate wafer is made, to include a plurality of electronic part module formation areas. Then, a plurality of passive devices are formed in each of the electronic part module formation areas on the wiring substrate wafer. Then, the device chips are formed on each of the electronic part module formation areas on the wiring substrate wafer. Finally, the wiring substrate wafer is divided.

Abstract: An assembled circuit comprising a substrate, a coil, a first conductive segment, a second conductive segment, a first through-hole connector and a second through-hole connector is disclosed. The first conductive segment is electrically connected to one end of the first through-hole connector, the other end of the first through-hole connector is electrically connected to one end of the second through-hole connector via the first conductive segment, and the other end of the second through-hole connector is electrically connected to the second conductive segment.

Abstract: A MMIC having: a substrate; a plurality of active and passive electrical elements disposed on a top surface of the substrate; a plurality of coplanar waveguide transmission line sections disposed on the top surface of the substrate for electrically interconnecting the active and passive electrical elements; an electrical conductor disposed on a bottom surface of the substrate under the coplanar waveguide section. Edges of ground plane conductors of the coplanar waveguide (CPW) sections have slots therein in regions thereof connected to the active and passive devices. The design of such circuit includes mathematical models of the CPW with the pair of local ground planes and the strip conductor thereof have relatively narrow connectable ports.

Abstract: An improved integrated circuit (IC) layout is described that provides conductive pads on opposite sides of a substrate. The conductive pads provide for connectivity to the chip in different chip orientations. Accordingly, multiple chips having the same layout can be provided in a package, instead of providing each chip with a different layout. Since the same layout may be used for each chip, manufacturing costs are reduced.

Abstract: A capacitor array substrate includes a substrate, first traces, second traces, capacitors, connecting lines, and signal lines. The substrate has a first, a second, and a third side. The first side is connected with the second and the third side. The first traces are disposed on the substrate in parallel and are not vertical or parallel to the first side. The second traces are disposed on the substrate in parallel. The capacitors are disposed on the substrate at intersections of the first and the second traces and are connected to the first and the second traces. The connecting lines are disposed on the second and the third side of the substrate. Each connecting line is connected to a first and a second trace. The signal lines are disposed on the substrate. Each signal line is connected to a first or a second trace and transmits signals from the first side.

Abstract: A device has a first terminal, second terminal and at least four lateral faces provided with contact areas, of which two respective ones each are mutually opposite. The contact areas of the mutually opposite lateral faces are connected to different ones of the first and second terminals.

Abstract: A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: An electronic component mounting structure which can reduce the ESL while saving the space when mounting electronic components is provided. A first electronic component 7 is electrically connected to surface-mounted electrode parts 11A, 12A at metal terminals 26, 27 such that a first capacitor 24 having a greater capacitance and a mounting surface 4a of a multilayer substrate 4 are separated from each other. A second electronic component 8 is arranged between the first capacitor 24 and the mounting surface 4a and electrically connected to surface-mounted electrode parts 12B, 11B at second terminal electrodes 32, 33. The second electronic component 8 overlaps the first capacitor 24 when seen in the laminating direction. The first electronic component 7 is mounted to the multilayer substrate 4 such that first terminal electrodes 22, 23 oppose each other in a predetermined direction D1.

Abstract: An embodiment of an electronic component includes a circuit element disposed within a package, which includes a surface and at least one standoff protruding from the surface. For example, where the circuit element is an inductor in a power supply, the standoff may allow one to mount the inductor component over another component, such as a transistor component. Therefore, the layout area of such a power supply may be smaller than the layout area of a power supply in which the inductor and transistor components are mounted side by side.

Abstract: A printed circuit board includes a high-speed differential signal control chip, first to eighth coupling capacitor pads, first to fourth connector pads, a first transmission line, a second transmission line, a third transmission line, a fourth transmission line, first to eighth transmission lines, two ninth transmission lines, first and second vias, and first to fourth sharing pads. The printed circuit board is operable to selectively support multiple connectors.

Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: Disclosed are an electromagnetic bandgap structure and a printed circuit board including the same. In accordance with an embodiment of the present invention, the printed circuit board can include a dielectric layer, a plurality of conductive plates, and a stitching via, which is configured to electrically connect the conductive plates to each other. The stitching via can pass through the dielectric layer, and a part of the stitching via can be placed in a planar surface that is different from a planar surface in which the conductive plates are placed. With the present invention, the electromagnetic bandgap structure can prevent a signal of a predetermined frequency band from being transferred.

Abstract: A capacitive touch switch having a printed circuit board and a capacitive electrode connected to the circuit board is disclosed. The printed circuit board is transparent and is interposed between a planar light guide provided with a light source and a non-conductive transparent cover, the electrode being icon-shaped and supported by the printed circuit board.

Abstract: A circuit module is mounted with an IC that modulates and demodulates a multicarrier signal. The circuit module has a laminated board, which is provided internally with a plurality of conductive layers laminated having insulating layers in between, and an IC, which is provided with a plurality of ground terminals to be grounded. Of the plurality of conductive layers, a conductive layer provided proximate to the IC configures a ground layer electrically connected to the plurality of ground terminals.

Abstract: In an electronic component in which a semiconductor chip (semiconductor element) and a passive component are integrated on a multilayer wiring board and the semiconductor chip and the passive component constitute a feedback circuit, an input end and an output end of the semiconductor chip (semiconductor element) are electrically separated from each other. The electronic component includes the multilayer wiring board, the semiconductor chip disposed on the main surface of or inside the multilayer wiring board, and the passive component having a first terminal and a second terminal connected to the input end and the output end of the semiconductor chip respectively, and is configured such that a conductive member constituting the multilayer wiring board is located at a position where a distance from at least one of the first terminal and the second terminal is smaller than a distance between the first terminal and the second terminal.

Abstract: A wiring board is formed with a substrate designating either the upper surface or the lower surface as a first surface and the other as a second surface; an electronic component arranged inside the substrate; and a first conductive layer formed on the first-surface side of the substrate by means of a first insulation layer made up of a first lower insulation layer and a first upper insulation layer. In such a wiring board, the first lower insulation layer and the first upper insulation layer are made of different materials from each other. Moreover, the first lower insulation layer is positioned on the first surface of the substrate and the electronic component, and the material that forms the first lower insulation layer fills a clearance between the substrate and the electronic component.

Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

Abstract: A transformer assembly is disclosed. An example circuit board assembly includes a circuit board. A drum core inductor is also included and has a drum core, a first winding, and first and second terminals extending from a first end of the drum core inductor. A wire of the first winding is wound around an axis of the drum core. The first winding has first and second ends coupled to the first and second terminals of the drum core inductor, respectively. A bobbin has first and second terminals extending from a first end of the bobbin. A wire of a second winding is wound around an axis of the bobbin. The second winding has first and second ends coupled to the first and second terminals of the bobbin, respectively. The first ends of the drum core inductor and the bobbin are attached to a circuit board such that the drum core inductor is positioned on the circuit board inside an opening of the bobbin defined along the axis of the bobbin. The drum core inductor and the bobbin are detached from one another.

Abstract: A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.

Abstract: The present invention provides devices for controlling a desired output of an output device. These devices include a first conductor, a second conductor having a varying, predetermined spacing from the first conductor, and a third conductor positioned on the actuator mechanism and having a plurality of interconnecting positions between the first conductor and the second conductor. A predetermined one of a plurality of output signals may be produced when the third conductor connects the first conductor and the second conductor to control the desired output of the output device.

Abstract: An electronic circuit device including a circuit board having electronic parts, and a flexible wiring board for connection between the circuit board and external equipment. The circuit board has circuit-side connection terminals juxtaposed on a mount surface having the electrical parts mounted thereon or a non-mount surface. The wiring board has terminals juxtaposed on one of the surfaces thereof so that the wiring-board-side connection terminals confront the circuit-side circuit board connection terminals, and free-end portions each formed so as to include at least one of the wiring-board-side connection terminals, and the wiring board free-end portions are not adhesively attached to the circuit board, and the circuit-side connection terminals are electrically connected to the corresponding wiring-board-side connection terminals while the circuit-side connection terminals confront the wiring-board-side connection terminals.

Abstract: An integrated circuit package system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Abstract: A Multi-configuration Processor-Memory device for coupling to a PCB (printed circuit board) interface. The device comprises a substrate that supports multiple configurations of memory components and a processor while having a single, common interface with a PCB interface of a printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components can be pre-tested, packaged memory components mounted on the substrate. The processor can be a surface mounted processor die. Additionally, the processor can be mounted in a flip chip configuration, side-opposite the memory components. In the first configuration, a heat spreader can be mounted on the memory components and the processor to dissipate heat.

Abstract: A capacitor with a combined with a resistor and/or fuse is described. This safe capacitor can rapidly discharge through the resistor when shorted. The presence of a fuse in series with the capacitor and results in a resistive failure when this opens during and overcurrent condition. Furthermore, the presence of a resistor in parallel to the capacitor allows the energy to be rapidly dissipated when a failure occurs.

Abstract: A manufacturing method for manufacturing an electronic device is disclosed. Conductive elastomers comprising of various configurations and resistivity are coupled to contact pads of an electronic device. The conductive elastomers are also coupled to substrate contacts on a substrate, allowing the conductive elastomers to function as electrical connection from device to substrate as well as to embed one or more passive components at the contact pads of the electronic device.

Abstract: A printed wiring board includes a core substrate having a cavity and having first and second surfaces, an inductor component accommodated in the cavity, a filler resin filling a gap formed between the substrate and component in the cavity, and a buildup layer formed on the first surface of the substrate and the component. The component has a coil layer, a second insulation layer formed on the coil layer, an electrode formed on the substance layer, and a via conductor formed in the substance layer and connecting the coil layer and the electrode, the component is accommodated in the cavity such that the electrode faces the first surface of the substrate, and the buildup layer includes an interlayer insulation layer formed on the first surface of the substrate and the component, a conductive layer formed on the insulation layer, and a connection via conductor connecting the conductive layer and electrode.

Abstract: A printed circuit board includes first and second layers, a control chip, bonding pads, and several electronic elements. The bonding pads can be selectively applied to interconnect the first and second layers, and the control chip with any of the electronic elements in a simple layout.

Abstract: Disclosed are apparatus and methodology for providing land grid feedthrough capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Low equivalent series inductance (ESL) is provided by current cancellation techniques involving opposite current flow in power or signal and ground current paths through the device.

Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, light emitting devices including such a sub-mount, and methods of manufacturing such a sub-mount are provided. The sub-mount including a base substrate including a first surface and a second surface different from the first surface, a conductive pattern on the first surface, a first pair and a second pair of first and second electrodes on the second surface, and vias extending through the base substrate between the first and second surfaces, wherein the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes of the first and second pair of first and second electrodes through the vias.

Abstract: A printed circuit board includes a signal layer, a power layer, and a ground layer. The signal layer includes an analog audio input/output (I/O) port and an audio chip. The audio chip includes a main body, a first group of signal pins connected to the analog audio I/O port and a second group of signal pins connected to a control chip. The power layer and the ground layer each is divided into two unconnected parts, an audio part and a digital part, by a dividing groove. The two audio parts act as a whole reference plane for traces between the analog audio I/O port and the first group of signal pins of the audio chip. The two digital parts act as reference planes for traces between the control chip and the second group of signal pins of the audio chip.

Abstract: A multilayer body includes first and second capacitance conductors and an internal conductor, which define a capacitor, provided therein. First and second external electrodes are respectively connected to the first and second capacitance conductors via first and second led out conductors. The internal conductor faces the first and second capacitance conductors. Third and fourth external electrodes are connected to the first capacitance conductor via third and fourth led out conductors. Fifth and sixth external electrodes are connected to the second capacitance conductor via fifth and sixth led out conductors.

Abstract: In the present electronic structure, a substrate is provided in the form of a circuit board. First and second electronic devices are positioned on opposite sides of the circuit board, each having a plurality of contacts connected to the circuit board. Each of the contacts of the first device is connected to a contact of the second device by a connector though the circuit board. At least one of the contacts of the first device is connected to the contact of the second device which is most adjacent to that contact of the first device across the circuit board.

Abstract: An electronic assembly includes a substrate having bond pads on a surface of the substrate. A solder mask covers the surface of the substrate, and a solder connection is disposed on each of the bond pads. At least one trench is formed in the solder mask, and is located between adjacent ones of the bond pads. At least one component has contact pads, and each contact pad is connected to one of the bond pads via one of the solder connections. The trench is located beneath the device and extends at least from one edge of the device to a location underneath the device. Underfill material fills the trench and space between the solder mask and the device.

Abstract: In a DC-DC converter module, a first through-hole conductor provided in a substrate as a first lead for electrically connecting a terminal as a voltage output terminal of an IC and a first terminal of an inductor component to each other and a second through-hole conductor provided in the substrate as a second lead for electrically connecting a terminal as a switching terminal of the IC and a second terminal of the inductor component to each other oppose each other in a direction intersecting a direction in which the first and second terminals oppose each other in the inductor component (i.e., the longitudinal direction of the substrate and inductor component).

Abstract: To provide a technique that can improve the reliability of coupling between a package with a PA module and a mounting board in mounting the package over the mounting board. The width of a back conductor pattern is made smaller than the width of each of back terminals. Specifically, for example, the back terminals are arranged in the X direction. The back terminals arranged in parallel to the X direction are coupled together by the back conductor pattern. At this time, the coupling direction (coupling line direction) of the back conductor pattern is the X direction. Taking into consideration the Y direction orthogonal to (intersecting) the X direction, the width of the back conductor pattern in the Y direction is made smaller than the width of each of the back terminals in the Y direction.

Abstract: This is a PCBA that can be used in any system where one component or package is connected to another component or package. This invention provides a very short connector or signal path that avoids the necessity of a signal trace termination in the PCB. The PCB has on its upper surface a first component or package and on its lower surface a second component or package in vertical physical and signal alignment with the first component or package. The first component or package has a BGA on its bottom surface and the second component has a BGA on its top surface, both of these BGAs are in electrical contact with each other. Because of the short signal trace provided, the PCB provides signal transitions as fast as 200 pS.

Abstract: An assembly including: a first substrate having a first surface and housing a first electrical-interconnection element and a second electrical-interconnection element in a position corresponding to the first surface; a second substrate having a second surface, housing a third electrical-interconnection element and a fourth electrical-interconnection element in a position corresponding to the second surface, and provided with a dielectric layer extending on top of the third interconnection element; and a first bump and a second bump made of conductive material, extending between the first electrical-interconnection element and the third electrical-interconnection element and, respectively, between the second electrical-interconnection element and the fourth electrical-interconnection element, at least partially aligned to the respective electrical-interconnection elements, the first bump being ohmically coupled to the first interconnection element and capacitively coupled to the third interconnection element,

Abstract: An electronic device including a PCB, a first electronic component, and at least one second electronic component arranged on the PCB. A circuit layer is formed on the PCB. The first electronic component has at least two pins. The pins of the first electronic component are electrically connected to the circuit layer. The first electronic component engages with the PCB to define a chamber. The at least one second electronic component is received in the chamber and electrically connected to the circuit layer.

Abstract: A microelectronic assembly includes a dielectric element, first and second microelectronic elements, signal leads, and one or more jumper leads. The dielectric element has oppositely-facing first and second surfaces and first and second apertures extend between the surfaces. A plurality of electrically conductive elements are positioned thereon. Signal leads are connected to one or more of the microelectronic elements and extend through one or more of the first or second apertures to some of the conductive elements on the dielectric element. One or more jumper leads extend through the first aperture and are connected to a contact of the first microelectronic element. The one or more jumper leads span over the second aperture and are connected to a conductive element on the dielectric element.

Abstract: A printed wiring board is formed by laminating a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer with insulating layers respectively interposed therebetween. An IC and an IC are electrically connected to each other by signal wiring via a signal via hole. In the printed circuit board, a power supply through-hole electrically connected to the power supply layer and a ground through-hole electrically connected to the ground layer are formed. On the outer layers of the printed wiring board, capacitors are mounted, each of which has one end electrically connected to the power supply through-hole and the other end electrically connected to the ground through-hole.

Abstract: A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices.