Abstract: An EL driving circuit which can operate at a satisfactory operation speed is disclosed. A voltage higher than the voltage for operating the EL element is input, and the input voltage is stepped down by the voltage step-down circuit (2) which is provided in each unit block (1). The stepped-down voltage is then supplied to a transistor (3) functioning as the driving element for driving the EL element. Therefore, even when the number of EL elements increases, sufficient source voltage can be supplied to each unit block.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: An inverter capacitor module includes a plurality of substrates having a plurality of ceramic capacitors provided on the top surfaces thereof, and first and second feeding unit lands having conductive films provided on both surfaces thereof and arranged to feed the plurality of ceramic capacitors, the first and second feeding unit lands on both surfaces thereof being electrically connected to each other, a conductive spacer inserted between the plurality of substrates for establishing one of an electrical connection between the first feeding unit lands of an underlying substrate and its overlying substrate and an electrical connection between the second feeding unit lands of an underlying substrate and its overlying substrate, a fixing member arranged to fix the plurality of substrates laminated via the conductive spacer, and a switching module fixed below the bottom substrate among the plurality of substrates that are laminated.

Abstract: Several embodiments of enhanced integrated circuit probe card and package assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: A technique and apparatus for integrating a speaker with button (or keyboard) components such as a tactile membrane and/or PCB. The tactile membrane conventionally used between buttons and switch mechanisms to provide tactile feedback to a user upon depression of the button is extended to form a vibrating portion of a speaker. The vibrating portion is doped with or otherwise includes an activating material (e.g., copper) which will be physically affected by a magnetic field. The activating material may be adhered to the upper and/or lower side of the vibrating portion, or doped therein. A coil for the speaker is formed with a coil tracing pattern formed on one or more layers of a PCB. One or more amplifier circuits may be included to drive one or more coil patterns, to cause a fluctuating magnetic field in the direction perpendicular to the vibrating portion of the tactile membrane.

Abstract: The present invention provides a small-sized capacitor module for use in an inverter, which is capable of suppressing the occurrence of unwanted inductance components in an electric connection path and which is suitable for a large current use. The present capacitor module is constituted by: mounting a plurality of ceramic capacitors 3 having first and second terminals 3a and 3b on the first surface 1 of a substrate 2; forming a first conductor 12 on the first surface of the substrate 2; forming a second conductor 14 on the second surface of the substrate 2; electrically connecting first and second terminals 3a and 3b to the first conductor 12 and the second conductor 14, respectively; forming, on the substrate 2, first and second terminal mounting portions where the respective first and second terminals of a switching module are mounted; and electrically connecting the first and second terminal mounting portions to the first and second conductors 12 and 14, respectively.

Abstract: A resin-formed substrate is provided which has a component side for mounting an electronic component thereon, and a solder side for soldering thereto a lead extending from the electronic component, which is the reverse to the component side, the resin-formed substrate comprising a metal frame forming an electronic circuit pattern; and a resin covering the metal frame, the resin having an aperture formed therein, for exposing a portion of the metal frame, wherein the portion of the metal frame exposed through the aperture serves as an electrode portion for mounting of the electronic component, wherein the resin has a rib integrally formed on the component side, thereby suppressing warp of the resin-formed substrate due to a temperature difference made between a component side and a solder side during soldering.

Abstract: The electronic device of the invention is such constructed that the antenna part (3) and the RF circuit part (4) can show their respective functions even after the antenna part (3) and the RF circuit part (4) have been separated. Besides a scribe line 6 is formed on a—preferably ceramic—substrate for separating the antenna part (3) from the RF circuit part (4). Both parts may be separated after a change in any environmental condition, such as a change in the circuit configuration of the board on which the device (10) is to be mounted.

Abstract: An arrangement of voltage variable materials for the protection of electrical components from electrical overstress (EOS) transients. A device having a plurality of electrical leads, a ground plane and a layer of voltage variable material. The voltage variable material physically bonds the plurality of electrical leads to one another as well as provides an electrical connection between the plurality of electrical leads and the ground plane. A die having a circuit integrated therein is attached to the ground plane. Conductive members electrically connect the plurality of electrical leads to the integrated circuit. At normal operating voltages, the voltage variable material has a high resistance, thus channeling current from the electrical leads to the integrated circuit via the conductive members.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate.

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.

Abstract: A multilayer printed-circuit board is provided which is formed by stacking one on the other a plurality of circuit boards, each including a hard insulative substrate having a conductor circuit formed on one or either side thereof, and having formed therein via-holes formed through the hard insulative substrate to extend to the conductor circuit and each filled with a conductive substance, with an adhesive applied between the plurality of circuit boards, and heating and pressing the circuit boards together. One of the outermost ones of the stacked circuit boards has formed on the surface thereof conductive bumps each positioned right above the via-hole and electrically connected to the via-hole, and the other outermost one of the stacked circuit boards has formed on the surface thereof conductive pin or balls each positioned right above the via-hole and electrically connected to the via-hole.

Abstract: Modularly constructed multichip modules with are disclosed. A plurality of miniature capacitor substrates and/or miniature resistor substrates are assembled and attached to a base substrate, preferably in a regular pattern. Power supply substrates are preferably attached to the base substrate along with the miniature substrates. All of the attached components are preferably pretested and have thicknesses close to one another. The pretesting substantially increases the manufacturing yield. Gaps between the miniature substrates and power supply substrates are filled with a polymer material, such as a powder-filled polyimide precursor. Thereafter, dielectric layer is formed over the components to provide a more planar surface. The dielectric layer is preferably planarized, such as by a chemical mechanical polishing process, to provide for a more planar layer.

Abstract: An optimal microelectronic semiconductor device mount area on a printed circuit board is provided. A novel mount area includes a plurality of collinear arrangements of attach pads and collinear arrangements of vias so that, at a minimum, at least one signal trace may be routed directly through the mount area. Additionally, capacitors may be coupled directly within the mount area on a bottom surface of the printed circuit board. The mount area includes a plurality of collinear arrangements of attach pads and a plurality of collinear arrangements of vias. Each of the collinear arrangements of attach pads are preferably separated from the nearest adjacent collinear arrangements of attach pads by an equivalent distance. A plurality of collinear arrangements of vias are separated from adjacent collinear arrangements of vias by a first distance. At least two mutually adjacent collinear arrangements of vias define a trace routing channel through the mount area.

Abstract: Apparatus and methods for connecting a device to an integrated circuit. The apparatus includes an insulating substrate that has two major sides and a number of sites for housing components. Each site has a first node on one of the two sides of the insulating substrate and a second node on the other of the two sides of the insulating substrate. Each site also has components that are aligned normal to the sides of the insulating substrate and are connected to the nodes at the site. Such apparatus are useful as adapters for testing an integrated circuit, such as connecting a test device to the integrated circuit with the adapter and observing and/or driving signals through the adapter.

Abstract: There is disclosed a three-dimensional semiconductor device having a printed wiring board or insulating film having first and second surfaces. Semiconductor components are packed on the first surface. External terminals are mounted to the second surface. Semiconductor components or a thin-film inductor producing a large amount of heat are installed in a space on the second surface via an anisotropic conductive film. This reduces the packaging density. After packaging, the rigidity of the printed wiring board or insulating film is enhanced. Heat generated by the semiconductor components is efficiently dissipated to reduce the affects on other components.

Abstract: An identification card is prepared by attaching an antenna and integrated circuit chip onto a core layer of polyolefin, attaching a bottom sheet to the core layer thus encasing the antenna and integrated circuit chip, providing an image-receiving layer on one or both outer surfaces of the resulting sandwich, and laminating a protective layer or layers over the image-receiving layer(s). The identification document displays improved durability, ease of manufacture and protection of the electronic components.

Abstract: An eletronic package comprising a printed circuit board on which are mounted a plurality of decoupling capacitors is disclosed. A carrier component electrically connects an integrated circuit to the printed circuit board through a plurality of solder balls. The plurality of solder balls comprises at least one solder ball for the integrated circuit ground voltage connection and at least one solder ball for the integrated circuit power voltage connection. The plurality of decoupling capacitors is organized as a set of ‘n’ capacitors ranged from a lower capacitor value Clow to a higher capacitor value Chigh such that the range Clow to Chigh of the ‘n’ capacitor values is a function of the frequency range Flow to Fhigh on which the integrated circuit operates.

Abstract: The inductance of the capacitor is reduced by connecting the capacitor directly to a via. In one embodiment inductance of a capacitor is reduced by a plurality of via, the number of via greater than the number of electrical couplings from the voltage pad to the voltage plane. In one embodiment the capacitor has a ground pad of a minimum size. In another embodiment the capacitor is electrically coupled to a trace having a length reduced to minimize inductance.

Abstract: Integrated packages incorporating multilayer ceramic circuit boards mounted on a metal support substrate can be used for temperature control by the metal support substrate. Various electronic components, as well as additional temperature control devices, can be connected to the circuit boards and to the metal support substrate to control or regulate the temperature of operation of the components. The integrated package can be hermetically sealed with a lid.

Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: A wiring lay-out is provided, for electrically connecting a decoupling cap on a front surface of a multilayer printed circuit board (e.g., a motherboard), with a surface-mounted electrical component (e.g., a micro-ball grid array packaged semiconductor device, such as a PC core logic chip set) on the front surface of the printed circuit board. The wiring lay-out includes a wiring portion formed from a copper plane on the front surface of the printed circuit board; this wiring portion, providing electrical connection from one of the balls of the ball grid array to the decoupling cap, is provided only on the front surface of the printed circuit board. In order to provide a route for the wiring between the electrical component and decoupling cap, vias through the printed circuit board are positioned in a row with bonding pads. All decoupling caps on the printed circuit board are provided on the front surface of the printed circuit board.

Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.

Abstract: An electrical apparatus and method for matching the input power source and output impedance of the electrical apparatus utilizes electromagnetic devices having two or more inductive windings, which may be connected in various series and/or parallel circuit configurations, by inserting them into a circuit board specially configured to accept my improved electromagnetic devices, and attaching jumpers to the circuit board for selecting the particular inductive windings to be incorporated into the electrical apparatus. The windings not selected for a given electromagnetic apparatus remain unconnected within the electromagnetic device.

Abstract: A transformer of a switching power-supply circuit is placed and mounted nearly in the middle area of a circuit board. The transformer is of a low-profile type, and a broad and flat upper surface of the transformer functions as a suction surface for a suction nozzle. When a surface-mount type switching power-supply unit is mounted in a mother board, firstly, the upper surface of the above transformer is held by the suction nozzle, the surface-mount type switching power-supply unit is transferred to a target mounting area on the mother board by the suction nozzle, and the surface-mount type switching power-supply unit is surface mounted in the mother board. Because it is not required to provide a nozzle suction surface for the suction nozzle's exclusive use, transfer molding is not needed, and accordingly a low-profile and low-cost surface-mount type switching power-supply unit can be facilitated.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: Fault tolerance is incorporated within the integral electric heaters of a reworkable electronic semiconductor component, such as a reworkable multi-chip module, to increase production yield and longevity of the rework feature. Components of the foregoing kind contain a multi-layer substrate to bond to a printed wiring board, and, for rework, the component includes a plurality of electric heaters arranged side by side on a bottom layer of the substrate. When energized with current, the heaters generate sufficient heat to weaken the adhesive or solder bond to the printed wiring board without delaminating the layers of the substrate, allowing the electronic semiconductor component to be pulled away from the printed wiring board for rework. Additional circuitry is included to automatically route heater current around, that is bypass, any current-interrupting break(s) as may form in any of the electric heaters giving the heaters a fault tolerance.

Abstract: A miniaturized high-frequency module includes an integrated circuit and chip capacitors electrically connected therewith within a recess in a substrate and to make a crystal oscillator and the substrate virtually equal in size. Thereby, a miniaturized high-frequency module can be obtained.

Abstract: One embodiment comprises a substrate having a top surface for receiving a semiconductor die. According to a disclosed embodiment, an inductor is patterned on the top surface of the substrate. The inductor is easily accessible by connecting its first and second terminals to, respectively, a substrate signal bond pad and a semiconductor die signal bond pad. In another disclosed embodiment, an inductor is fabricated within the substrate. The inductor comprises via metal segments connecting interconnect metal segments on the top and bottom surfaces of the substrate. The first and second terminals of the inductor are easily accessible through first and second substrate signal bond pads. One embodiment comprises at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and a printed circuit board attached to the bottom surface of the substrate.

Abstract: At least two electric elements (203) such as semiconductor chips or surface acoustic wave devices are mounted on wiring patterns (201), and the electric elements (203) are sealed with a thermosetting resin composition (204). An upper surface of the at least two electric elements (203) and an upper surface of the thermosetting resin composition (204) are abraded at the same time, thereby forming surfaces substantially flush with each other. Since they are abraded while being sealed with the thermosetting resin composition (204), it is possible to reduce the thickness without damaging the electric elements (203). Also, the electric elements (203) and the wiring patterns (201) can be prevented from being contaminated by an abrasive liquid. In this manner, it is possible to obtain an electric element built-in module whose thickness can be reduced while maintaining its mechanical strength.

Abstract: A mounting configuration of electric and/or electronic components, in particular electrolytic capacitors, on a printed circuit board is described. The printed circuit board is formed by at least two metallic plates insulated electrically from one another by an insulating layer that preferably conducts heat well and has holes for the connecting pins of the electric and/or electronic components. Through which holes the connecting pins are plugged and connected electrically to the respectively associated metallic plate.

Abstract: A new packaging technology which improves the electrical and mechanical performance of the circuits using magnetic elements. High frequency current loops generate electromagnetic fields which are radiated or induce high frequency current in the rest of the circuit. To reduce the radiated field, these loops have been minimized by locating the high frequency switching components close to each other and very close to the magnetic elements. By separating the high frequency switching electronic components from the rest of the electronic components and locating them on the same multilayer PCB where the magnetic element is constructed, optimal results are obtained.

Abstract: A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.

Abstract: In an electronic circuit equipment using a multilayer circuit board on which a semiconductor chip is mounted, a thin film capacitor is provided on the multilayer circuit board. Moreover, a first electrode of the thin film capacitor and a first wiring of the multilayer circuit board are electrically connected to each other, and a second electrode of the thin film capacitor and a second wiring of the multilayer circuit board are electrically connected to each other, respectively. Furthermore, a thin film dielectric of the thin film capacitor was grown epitaxially with the first electrode as its base. The employment of the multilayer circuit board makes it possible to provide the electronic circuit equipment using the multilayer circuit board that includes the built-in thin film capacitor having the high dielectric-constant thin film dielectric.

Abstract: A method for producing a molded flip chip package is described. The incomplete flip chip package comprising a thin substrate and a silicon chip is placed in a mold. A resin, such as an epoxy, is injected into the mold filling the gap between the surface of the flip chip and the adjacent substrate. Additionally, a stiffening structure is formed to increase the overall rigidity of the thin substrate specifically and the package as a whole.

Abstract: A vertical stack of semiconductor devices is formed by folding a strip-like flexible interconnector assembled with integrated circuit chips, packages and/or passive components and attaching coupling members solderable to other parts (FIGS. I4A and I4B).

Abstract: A semiconductor package with a flash-proof device is proposed, in which at least one chip and at least one passive device mounted on a substrate are covered by a flash-proof device dimensionally designed for positioning the substrate in a conventional mold and preventing a molding resin from flashing on the substrate in a molding process, and thus quality of the fabricated package can be assured. Due to no need of a specifically designed mold, fabrication costs are reduced. Furthermore, the flash-proof device has its top side exposed to outside of an encapsulant formed in the molding process, thereby allowing heat dissipating efficiency to be improved. Moreover, the flash-proof device provides shielding for the chip and the passive device received therein, so that external electromagnetic interference with performance of the semiconductor package can be reduced.

Abstract: An improved method and means for decoupling a printed circuit board are disclosed. A power plane is included having a peripheral edge. The power plane includes a first region and a second region which is separate from and contiguous to the first region. The first region is located from the peripheral edge to a middle portion of the power plane. The first region includes a peripheral portion of the power plane. The second region includes only the middle portion of the power plane. A ground plane is coupled in parallel to the power plane. The ground plane has a peripheral edge. The ground plane includes a first region, and a second region which is separate from and contiguous to the first region. The first region includes the peripheral edge and includes a peripheral portion of the ground plane. The second region includes a middle portion of the ground plane. A first plurality of decoupling elements are connected to the first region of the power plane and to the first region of the ground plane.

Abstract: A multi-chip module includes bare IC chips mounted on respective areas of a printed wiring board. Outer electrode pads on the peripheries of the board are soldered to another printed wiring board such as a motherboard. Lead pads and the outer electrode pads are interconnected through a circuit pattern, through holes, and interstitial via holes. The circuit pattern is disposed on a die bonding surface of the bare IC chips for which insulation is not necessary.

Abstract: An interconnect system for use with interposers or chip carriers provides highly efficient area utilization by attaching very small chip components (50) such as resistors or capacitors to the solder pads (30) on the underside of a carrier substrate (10) such that only one end (55) of the chip component is attached to the solder pad, while the other end (56) is suspended free in space. When the interposer or chip carrier is soldered to a main printed circuit board, the free end of the chip component is soldered to a corresponding pad on the printed circuit board. The vertically mounted chip components provide an electrical function, such as decoupling, and also provide an electrical interconnection between the interposer and the printed circuit board. The interposer has electrical vias that pass vertically through the substrate from the solder pads to a conductive circuitry pattern on the top side, which also contains an integrated circuit die or an array of larger discrete chip components.

Abstract: Compositions and methods are provided whereby electronic components may be produced that comprise a) a substrate layer; b) an insulator layer coupled to the substrate layer, wherein the insulator layer comprises at least two different kinds of embedded passive components; and c) at least one additional layer coupled to the insulator layer. A preferred method comprises a) imaging an insulator layer to create a first pattern on the insulator layer; b) etching the first pattern on the insulator layer to create a first compartment in the insulator layer; c) filling the first compartment with a first material to form a first passive component; d) imaging the insulator layer to create a second pattern on the insulator layer; e) etching the second pattern on the insulator layer to create a second compartment in the insulator layer; and f) filling the second compartment with a second material to form a second passive component.

Abstract: A small circuit board, preferably having or providing capacitance is mounted on the surface of a main circuit board opposite the surface where a BGA or other integrated circuit is mounted, and within the footprint defined the integrated circuit package. Preferably the small circuit board is formed from multiple interleaved conductive and dielectric layers to provide inherent capacitance in the circuit board itself. Capacitance provided by the small circuit board can be configured by selecting the number and/or size and/or placement of the conductive layers. Discrete devices can be mounted on the small circuit board if desired.

Abstract: A surface mountable and low profile electrical component which can be electrically coupled to the solder side of a PCB, while other electrical components are mounted to a component side of the PCB. The surface mountable electrical component includes a mounting substrate having a diode or LED chip with electrical terminals. The terminals pass through the mounting substrate to be electrically coupled to first and second electrical contacts, which provide an electrical pathway between the terminals and the PCB.

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

Abstract: A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

Abstract: A printed circuit board assembly with improved bypass decoupling for BGA packages. In one embodiment, a capacitor may be interposed between a BGA package and a PCB within a perimeter of the contact pads that form a BGA footprint. The capacitor may have physical dimensions which allow a BGA package to be mounted such that there is no physical contact between the capacitor and the BGA.

Abstract: The invention relates to an electronically detectable resonance label, in particular an RFID label, with a substrate made of plastic foil and with conductive surfaces on the front and rear of the substrate, with some of the conductive surfaces forming a capacitor in a mutual area of overlap, comprising a first capacitor plate on the front of the substrate and a second capacitor plate on the rear of the substrate. The capacitor plates are in the shape of elongated strips of uniform width along their entire length; with said strips overlapping only partially. The area of overlap is arranged at a distance from both ends of at least one capacitor plate. This provides the advantage that during the production process relative displacement of the capacitor plates can take place in two directions.

Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node.

Abstract: Provided is a semiconductor memory module capable of decreasing a parasitic capacitance and a parasitic inductance which are incidental to a signal transmission path, thereby reducing a distortion of a signal waveform. In a memory module, four DRAMs are provided on a muttilayer printed circuit board in one line corresponding to a direction of arrangement of external terminals thereof and board terminal groups of the module are provided to make a pair along two long sides of the multilayer printed circuit board. The DRAM has external terminals extended from one of the long sides and external terminals extended from the other long side. Board terminals and board terminals in the board terminal group of the module are connected to the DRAM, and board terminals and board terminals in the board terminal group TGB of the module are connected to the DRAM.