Abstract: An apparatus for buffering power transients in a supply power for expansion cards inserted into expansion slots on a computer motherboard. The apparatus comprises a printed circuit board, a connector on the printed circuit board, and at least one capacitor on the printed circuit board. The connector is configured to fit into one of the expansion slots on the motherboard, and comprises at least one power pin and at least one ground pin. The at least one capacitor is connected to the power and ground pins of the connector and has sufficient capacitance to buffer power transients within the supply power to the expansion slots.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least the desired area of the surface of the second insulation layer, and a processing step includes a removing step of removing an upper part of the area higher than the second insulation layer on the substrate obtained at the laminating step, and an exposing step of exposing a part of the area of a conductive pattern adjacent to the lower side of the second insulation layer.

Abstract: Methods and apparatus to couple a device, such as, for example, a surface mount device, with a substrate, such as, for example, a printed circuit, are disclosed. An apparatus, according to one aspect, may include a substrate, a plurality of terminals coupled with the substrate, a conductive bonding material coupled with the plurality of terminals, an electronic device coupled with the conductive bonding material, and a holder that is coupled with the substrate to hold the electronic device. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed therebetween, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract: A first substrate includes a coil assembly and an integrated circuit mounted thereon. A second substrate includes capacitors 16 and resistors mounted thereon. The first substrate and the second substrate are interconnected by an encapsulating medium.

Abstract: According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.

Abstract: An electronic package has a circuit board including a substrate electrical circuitry including circuit traces and first and second contacts for connecting to surface mount device(s). The first and second contacts each have multiple components including first and second pads. The first pad is separate from the second pad to allow for low cost and easy testing of the electrical circuit.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

Abstract: The present invention provides an electromagnetic component formed from adjacent conducting layers of a multi-layer PCB and two additional conducting layers in contact with the PCB. The inventive component includes one or more winding turns formed by connecting the multiple layers of the multi-layer PCB with conductive vias and by connecting the additional conducting layers to respective top and bottom surfaces of the PCB. In one embodiment, one of the conducting layers is soldered to a top conducting layer of the PCB and the other of the conductive layers is soldered to a bottom conducting layer of the PCB, effectively increasing the cross-sectional area of the top and bottom winding layers. In another embodiment, the additional conducting layers are separated from the adjacent conducting PCB layers by a layer of insulation, permitting the additional conducting layers to form separate winding turns.

Abstract: Circuit boards capable of receiving different sets of electrical devices are fabricated from raw boards of the same type by forming respective networks of electrically conductive traces with a common layout on the raw boards, including open circuits within the networks. Electrical device receivers and controllers are then loaded on the boards, and some of the open circuits are closed such that some of the boards have different patterns of closed circuits and thereby different interconnections. Some of the receivers can accommodate two different types of electrical devices, with some of the boards configured to support one type and the others another type. The loading of receivers and controllers, and the closing of open circuits, can be performed simultaneously with the placement of zero ohm resistors used for circuit closings. Numerous different circuit board configurations can thus be supported from a common supply of raw boards.

Abstract: A surface mounted power supply circuit apparatus, including a circuit substrate, circuit constituting parts mounted on the circuit substrate, and a sealing member provided on the circuit substrate for covering the circuit constituting parts, at least one portion of the circuit constituting parts being configured to be contained in a containing portion formed in the circuit substrate.

Abstract: A semiconductor device (10) includes a semiconductor die (20) and an inductor (30, 50) formed with a bonding wire (80) attached to a top surface (21) of the semiconductor die. The bonding wire is extended laterally a distance (L30, L150) greater than its height (H30, H50) to define an insulating core (31, 57). In one embodiment, the inductor is extended beyond an edge (35, 39) of the semiconductor die to reduce loading.

Abstract: Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: An integrated circuit (IC) package includes a chip carrier and a chip mounted to the chip carrier. The chip carrier has a centrally located power delivery region and a peripherally located input-output (I/O) delivery region disposed in partially surrounding relationship to the power delivery region. Power and ground paths are disposed in the power delivery region and I/O signal paths are disposed in the I/O delivery region.

Abstract: This invention is directed to reduce degradation, loss, and reflection of high frequency signals of a coupling circuit for an alternating current. The coupling circuit, for connecting a first circuit element to a second circuit element, comprises a die capacitor and a chip capacitor connected in parallel to each other. The die capacitor has a first electrode that faces to and is in contact with the first circuit element, and a second electrode that is wire-bonded to the second circuit element. The chip capacitor also has a first electrode that is in contact with the first circuit element and a second electrode that is in contact with the second electrode of the die capacitor. The coupling circuit may show both advantages of superior performance at high frequencies attributed to the die-capacitor and relative large capacitance attributed to the chip-capacitor.

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes a first compensation structure provided on an inner metalized layer of the PCB at a first stage area of the PCB, and a second compensation structure, provided at a second stage area of the PCB, for increasing compensation capacitance with increasing frequency.

Abstract: A circuit board comprises a base film that is a base layer, a first conductive circuit manufactured by hardening conductive paste material formed in a predetermined shape on the base film, a first insulating layer manufactured by hardening insulating paste material formed on the base film and the first conductive circuit, and a second conductive circuit manufactured by hardening conductive paste material in a predetermined shape on the first insulating layer, wherein an electronic part built-in by the first insulating layer and second insulating layer is connected to the second conductive circuit, and the first conductive circuit is connected to the second conductive circuit through a via hole.

Abstract: The present invention realizes the miniaturization of a semiconductor module. The semiconductor module includes a module board having external electrode terminals and a heat radiation pad over a lower surface thereof, a first semiconductor chip incorporating an initial-stage transistor of a high frequency power amplifying device therein, a second semiconductor chip incorporating a next-stage transistor and a final-stage transistor therein, and an integrated passive device which constitutes a matching circuit. At least one of the first semiconductor chip and the second semiconductor chip and the integrated passive device are mounted over an upper surface of the module board in an overlapped manner.

Abstract: An integrated circuit ground system includes an integrated circuit (IC) ground connection, first and second IC package pins, first and second printed circuit board (PCB) pads, a PCB ground connection, and a resonant circuit. The IC ground connection is fabricated on a substrate of an integrated circuit. The first IC package pin is operably coupled to the IC ground connection via a first bond wire. The second IC package pin is operably coupled to the IC ground connection via a second bond wire. The second PCB pad is operably coupled to the second IC package pin to provide a low impedance DC ground connection for the integrated circuit to the printed circuit board. The resonant circuit is operably coupling the first IC package pin to the first PCB pad, wherein the resonant circuit is tuned to resonant with the first bond wire at high frequency range to provide a low impedance AC ground connection for the integrated circuit to the printed circuit board within the high frequency range.

Abstract: At least one of a feedback path and a feed path is divided into two paths, and the divided feedback path and the feed path for feeding a signal form a twisted pattern to suppress radiation noise of a high frequency by a twisted pair effect. The other divided feedback path decreases a resistance value of a direct current component and decreases a whole direct current resistance to feed a sufficient current to the path.

Abstract: The invention describes a method for producing chip cards with contactless and/or contact-type operation having a multilayer card body, an integrated circuit and at least one coil (2, 21) for data exchange and for power supply. The coil (2, 21) is applied to one or more layers (11) of the card body by printing technology, whereby after production of the printed coil a metal foil (4, 41) is placed over the coil terminals (32, 33) and laminated into the card body, thereby producing the connection between the contact areas (32, 33) of the printed coil and the metal foil (4, 41).

Abstract: In a mounting structure of an integrated circuit, an electrolytic capacitor for smoothing power of a heating element is disposed out of range of thermal effect of the heating element, and a ceramic capacitor for supplementing the operation of the electrolytic capacitor is additionally disposed between the electrolytic capacitor and the heating element. Accordingly, a long lifespan of the electrolytic capacitor and a stable operation of the heating element can be guaranteed.

Abstract: A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability.

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A passive device and a module for a transceiver are provided. The passive device for a transceiver includes a semiconductor substrate or a dielectric substrate, at least one capacitor, a dielectric layer, at least one inductor, a via hole, a metal electrode, radio frequency signal lines, and a radio frequency ground. The at least one capacitor is formed on the substrate. The dielectric layer is formed on the capacitor and the substrate. The at least one inductor is formed on the dielectric layer. The via hole penetrates through the dielectric layer. The metal electrode is formed in the via hole and electrically connects the capacitor and the inductor. The radio frequency signal lines are for the inductor and the capacitor. The radio frequency ground is formed on the substrate and isolated from the radio frequency signal lines. A reduction in the area required for mounting passive devices and modules thereof contributes to the downsizing of communication systems.

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract: A method of making a resonant frequency tag having a predetermined frequency comprises forming a first conductive pattern comprising an inductive element and a first land having a first end connected to an inductive element end, and a second end spaced a predetermined distance from the first end; separately forming a second conductive pattern comprising a second land having a predetermined width and a link element; placing the second conductive pattern proximate the first conductive pattern at a first location wherein the second land overlies a portion of the first land with a dielectric therebetween establishing capacitive element plates having a first capacitance along with the inductive element forming a resonant circuit; measuring the resonant circuit frequency and comparing the measured and predetermined frequencies moving the second land along of the first land length to match the resonant frequency; and securing the second conductive pattern to the first conductive pattern.

Abstract: A contact-less high-speed signaling interface and method provide for the communication of high-speed signals across an interface, such as a die-substrate interface or die-die interface. The interface includes a transmission-line structure disposed on a dielectric medium to carry a high-speed forward incident signal, and another transmission-line structure disposed on another dielectric medium and substantially aligned with the other transmission-line structure to generate a coupled high-speed signal in a direction opposite to the incident signal.

Abstract: A PCB having a card slot receiving a card provided with signal input/output pins and a circuit element to provide extended capability is inserted, and having data transmission pins, a power pin and a ground pin in correspondence to the signal input/output pins, comprises an electronic device internally provided for impedance matching with the card, and having a first end connected to one of the data transmission pins and a second end connected to one of the power pin and the ground pin. With this configuration, a card slot internally comprises an electronic device for impedance matching, so that a space of the PCB can be efficiently utilized.

Abstract: A modular electronic assembly and a method for making a modular electronic assembly are disclosed. The subject modular electronic assembly is constructed in such a way as to maximize available surface area on printed wiring boards by incorporating pretested discrete passive elements within the body of such printed wiring boards and electrically connecting the elements in a volume-efficient manner. A modular electronic assembly constructed according to the presently disclosed subject matter is formed by arranging a plurality of diverse, pretested passive components between a plurality of copper and tacky epoxy sheets, holding the passive components in place by an epoxy resin layer and electrically connecting the components together by electrical vias penetrating the tacky epoxy layers.

Abstract: An intermediate substrate includes a substrate core formed by a main core body portion constructed of a sheet of polymer material and having a subsidiary core accommodation portion formed therein. A ceramic subsidiary core portion, which is constructed of a ceramic sheet, is accommodated in the subsidiary core accommodation portion and is of a thickness matching that of the main core body portion. A thin film capacitor is formed on a first main surface side of a plate-like base of the core portion and includes first and second thin film electrodes separated from each other by a thin film dielectric layer so as to provide direct current isolation between the electrodes. First and second direct current isolated terminals of a first terminal array are electrically connected to the first and second thin film electrodes.

Abstract: An electronic package of the kind having a folded substrate is provided. The substrate is configured so that a stress concentration is created where folding is desired. In the present example, the stress concentration is created with first a resilient metal ground layer that resists bending and has an edge that promotes the creation of a stress concentration in a flexible layer at or near the edge. A second metal ground layer resists bending in another portion of the substrate, and also has an edge creating a stress concentration in a different area of the flexible layer. The portions of the substrate having the first and second resilient metal ground layers can be folded over one another with substantially no bending in these portions, while a fold portion between the edges bends to allow for folding of the substrate.

Abstract: Electrode lead wires for each capacitor are soldered to land patterns of a mounting plate of insulation. Spacers each having a flexible structure composed of a grid of metal lines are mounted on electrode patterns printed on a printed circuit board, and tip portions of the electrode lead wires which project from the mounting plate are stuck into the spacers to provide mechanical contact therebetween. While keeping this contact, the mounting plate is secured with bolts to the printed circuit board. This forms a capacitor mounting structure. For replacement of the capacitors, by simply loosening the bolts, the entire mounting plate including all the capacitors can be demounted from the board.

Abstract: The system and methods describe a computer system implementing an adjustable control signal path whose length may be precisely adjusted to control timing of a control signal that propagates along the path. One such adjustable signal path has two clusters of possible signal paths. Each of the signal paths in each cluster has a length, and the overall length of the control signal path may be adjusted by selectively implementing one signal path from each of the clusters by electrically connecting that path into the electrical circuit by the selective installation of zero ohm resistors. In this way, a system designer may design several possible signal path lengths on to a motherboard or printed circuit card, and implement the path length which provides the most precise signal timing adjustment.

Abstract: According to one embodiment of the invention, a compact wireless modem card placement in compliance with thickness requirement of type II PCMCIA standard and type II Compact Flash form factor standard is provided which includes a first side and a second side. The first side has a height clearance of approximately 2 mm. The second side, which is opposite the first side, has a height clearance of approximately 1.45 mm. In one embodiment, those components with a height greater than 1.4 mm are placed on the first side of the card. The first side of the card includes a radio-frequency transmitter (RFT) chip located at the lower left of the first side. The RFT chip performs signal processing functions to up-convert baseband signals received from a mobile station modem (MSM) chip to radio-frequency signals. The first side also includes a radio-frequency (RF) surface acoustic wave (SAW) filter located above and to the left of the RFT chip.

Abstract: A high quality factor on-package, off-die inductor assembly is disclosed. The assembly includes a flip-chip, ball-grid array package substrate, an on-package, off-die trace line is coupled to one or more bumps attached to an upper surface of the package substrate. The trace line has a self-inductance and a predetermined length. The quality factor associated with the inductor is a ratio of the trace line's inductance to the trace lines resistance. The package substrate is a low loss laminate.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: A method of using blind via to house electronic components within an electrical device is provided. Such a method allows for the vertical orientation of various types of passive components within a layer of a printed circuit board (PCB) or an integrated passive device (IPD). One exemplary embodiment of the method provides for the passive component's electrical connection between an embedded ground and another device on the surface of the PCB. By virtue of its component positioning, such a method reduces the space demands placed upon the surface of the PCB, enhances the flexibility of circuitry design, and allows for a greater variety of passive components and integral passive devices to be utilized within the PCB itself. Another exemplary embodiment of the method provides for greater flexibility in the design and manufacture of IPDs by allowing for the vertical electrical connection of various passive components through the placement of intervening passive components into via.

Abstract: A formable wiring structure, an interposer with the formable wiring structure, a multichip module including the interposer and in particular a microprocessor and L2, L3 cache memory mounted on the interposer. The formable wiring structure includes wiring layers separated by dielectric layers. Attachment locations for attaching to module substrates, printed circuit cards or for mounting chips (microprocessor and cache) are provided on at least one interposer surface. The microprocessor is centrally located opposite a module attach location and the cache chips are on portions that are bent away from the module attach location to reduce and minimize module real estate required.

Abstract: An electronic package with a passive component includes a circuit carrier, at least a passive component and an anisotropic conductive layer. The circuit carrier has at least a passive-component-pad set including multiple pads. The passive component has multiple electrodes placed over the corresponding pads of the passive-component-pad set. The anisotropic conductive layer is deposited between the electrodes and the pads.

Abstract: A capacitor mounting structure has four capacitors close-arranged so that the outline of the arrangement is almost rectangular. The capacitors are arranged so that an angle formed by the current vectors of each pair of adjacent capacitors is 90 degrees and that one end face in the length direction of each capacitor is directed in parallel to an inner side face of another adjacent capacitor.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. Several different variations of the chip module are disclosed.

Abstract: A memory module preferably includes a printed circuit board (PCB) panel having multiple memory chip pad groups arranged on both sides thereof. Each memory chip pad group preferably includes multiple pads that correspond to lead lines of multiple memory chips arranged on the PCB panel. Connectors are preferably formed along an edge of the PCB panel to electrically connect the memory chip pad groups to an external device. Multiple damping chip pad groups preferably include built-in damping chips. One or more of the damping chip pad groups are preferably arranged adjacent to a lateral edge of one or more of the memory chips. The damping chip pad groups can electrically connect the connectors to the memory chip pad groups and dampen the signal noises.

Abstract: A noncontact ID card composed by laminating an antenna circuit board where an antenna is formed and an interposer board formed by connecting an enlarged electrode to an electrode of a mounted IC chip and bonding between an antenna electrode of the antenna circuit board and the enlarged electrode of the interposer board with electroconductive adhesive material, wherein a substrate of the antenna circuit board and a substrate of the interposer board are bonded. In addition, in another composition, at least one local deformation is applied to a boding face of the electrodes each other in a direction crossing the bonding face.

Abstract: A method of making a microelectronic package. The advanced microelectronic component package incorporates a specially shaped base element which holds and electrically separates the individual conductors associated with the microelectronic component(s) so that the individual conductors may be bonded to external package leads and other conductors within the package. In a first embodiment, jacketed, insulated wire is used as one winding of a toroidal transformer, while unjacketed insulated wire is used as another winding. The jacketing is stripped from the first winding and the exposed conductors are routed into channels along the sides of the base element. The unjacketed conductors are also routed into the same channels, where both conductors are bonded to the external package leads. Raised elements along the sides of the base provide the required electrical separation between the conductors during both manufacture and operation. A method of manufacturing the improved microelectronic package is also disclosed.