Abstract: A transformer of a switching power-supply circuit is placed and mounted nearly in the middle area of a circuit board. The transformer is of a low-profile type, and a broad and flat upper surface of the transformer functions as a suction surface for a suction nozzle. When a surface-mount type switching power-supply unit is mounted in a mother board, firstly, the upper surface of the above transformer is held by the suction nozzle, the surface-mount type switching power-supply unit is transferred to a target mounting area on the mother board by the suction nozzle, and the surface-mount type switching power-supply unit is surface mounted in the mother board. Because it is not required to provide a nozzle suction surface for the suction nozzle's exclusive use, transfer molding is not needed, and accordingly a low-profile and low-cost surface-mount type switching power-supply unit can be facilitated.

Abstract: A resistor-capacitor network for terminating transmission lines. The network includes a core of dielectric material. Capacitors are formed within the core from spaced apart electrode plates. Terminals extend from the electrode plates to a top surface of the core. The electrode plates are oriented perpendicular to the top surface. Ball pads are located on the top surface. Resistors are located on the top surface and are connected between the ball pads and terminals. Conductive spheres are attached to the ball pads.

Abstract: An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: The flat mount assembly, or transponder, has at least one semiconductor chip that is connected to an antenna for interchanging data and power with an electronic apparatus. The antenna is formed of two electrical conductors. A conductive layer is formed on the mount in overlapping relationship with the electrical conductors of the antenna. The overlapping conductive layer results in greater capacitive coupling between the electronic apparatus and the flat mount assembly.

Abstract: A method for determining via placement for wireless test fixture printed circuit boards (PCBs) utilizes the fixed test interface pattern of the bottom conductive pads to quickly locate the nearest bottom pad to a given top pad. The distance between the top pad and its nearest bottom pad is then calculable based on the coordinates of the respective pads on the PCB. If the distance is greater than a predetermined clearance requirement, a via is placed within the interior of the nearest bottom pad; otherwise, the via is placed exterior to the nearest bottom pad.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract: A slot apparatus for a memory module on a printed circuit board. The slot apparatus includes a first memory slot set, a second memory slot set, a terminal resistor, and a serial resistance. The first and second memory slot sets are disposed on the printed circuit board. The terminal resistor is disposed between the first and second memory slot sets. The serial resistance is disposed on the printed circuit board and is electrically connected to the first and second memory slot sets through the printed circuit board. The terminal resistor is respectively and electrically connected to the first and second memory slot sets through the printed circuit board. The terminal resistor and the first and second memory slot sets are connected to a terminator voltage.

Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost.

Abstract: A package with a Power Supply In Package (PSIP) feature may include a charge pump external to the die in order to take advantage of a smaller die size. The die may be mounted on a substrate with an array of solder balls of a Ball Grid Array. The package may have substantially the same size as a package without PSIP capability. In one embodiment, the passive components may be mounted on the die using epoxy. In another embodiment, the reduced-size passive components may be mounted on the substrate of the ball grid array in a region free of solder balls.

Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.

Abstract: A chip carrier for testing electrical performance of a passive component includes: a core layer having a plurality of conductive traces on a surface thereof; at least one first trace connected with the passive component and having a first predetermined position and two ends, wherein the two ends are respectively electrically connected to a first bond finger on the surface of the chip carrier and to a first ball pad on an opposite surface of the chip carrier; at least one second trace not connected with the passive component and having two ends and a second predetermined position located on the same surface as the first predetermined position, one end of the second trace being electrically connected to a second ball pad located on the same surface as the first ball pad; and a solder mask layer applied over the conductive traces, with the first and second predetermined positions exposed.

Abstract: A capacitor module incorporating a ceramic capacitor having terminal members for reducing stress caused by thermal stress or electrostriction in the ceramic capacitor itself, and a semiconductor device using the capacitor module. The capacitor module and the semiconductor device are designed to have a reduced size and improved reliability.

Abstract: The invention is related to a multi-chip-module and to a method for its manufacture. The module comprises a base carrier, on which at least in some areas signal conductor tracks and signal contact surfaces arranged at least in a single layer are located, and with at least one semiconductor component operating in the signal range and connected with the signal conductor track and signal contact surfaces. The purpose is to achieve a high degree of integration with a multi-chip-module of this type. To do so, in addition at least in some areas on the base carrier power conductor tracks and power contact surfaces arranged in at least one layer are located. Furthermore, at least one power electronics component operating in the power range is provided, which is connected with at least one power conductor track, at least one power contact surface and at least one signal conductor track.

Abstract: A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Abstract: The adapter couples a power module to a circuit board. An adapter embodying the present invention can be configured to allow the connection of any power module regardless of pin out to any circuit board. Signal modifying circuitry can also be added to the adapter to enhance or simply modify the signal to the end user's circuit board. The modifying circuitry can act on either the input to the adapter or the output from the adapter. At least one conductive path couples the input interconnects and the output interconnects.

Abstract: In a printed circuit board design support apparatus for supporting design of a printed circuit board by calculating a radiation amount of electromagnetic radiation caused by an interconnection on the basis of design information related to each of the printed circuit board having a ground plane, interconnections formed on the printed circuit board, and components to be mounted on the printed circuit board, an arithmetic unit calculates a common mode (CM) radiation amount of the interconnection on the basis of a CM radiation amount ratio that indicates a ratio of a common mode (CM) radiation amount of electromagnetic radiation caused by the ground plane in correspondence with the interconnection to a differential mode (DM) radiation amount of electromagnetic radiation caused by the interconnection. A printed circuit board design support method and program are also disclosed.

Abstract: A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

Abstract: A decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The decoupling capacitor structure is arranged so that parasitic inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is reduced. The circuit boards include at least two voltage planes. An ASIC having active device(s) is connected to one face of the circuit board. A decoupling capacitor structure is provided having at least two conductive plates in a dielectric material and is connected directly or indirectly to the ASIC. Vias extend from the conductive plates through the dielectric material to connect to circuit board vias on a second face of the printed circuit board or to the ASIC. The decoupling capacitor vias are parallel to each other; and each via connected to one conductive plate is located adjacent a via connected to another conductive plate to minimize voltage deviation.

Abstract: A semiconductor device includes: a multi-layered wiring substrate in which a multiple wiring pattern layers are laminated through insulating layers. The multi-layered wiring substrate has a first, semiconductor element mounting face and a second face opposite to the first face. A semiconductor element is mounted on and connected to connecting pads on the first face. A chip-capacitor is arranged on and connected to the connecting pads on the second face. An electric power supply circuit includes the chip-capacitor for supplying electric power to the semiconductor element. Conductor paths for electrically connecting the first connecting pads with the second connecting pads are substantially extended vertically and penetrate through the multi-layered wiring substrate through so as to reduce the length of the conductor paths to a minimum, so that the chip-capacitor is located at the opposite side of the semiconductor element.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: Electrode lead wires for each capacitor are soldered to land patterns of a mounting plate of insulation. Spacers each having a flexible structure composed of a grid of metal lines are mounted on electrode patterns printed on a printed circuit board, and tip portions of the electrode lead wires which project from the mounting plate are stuck into the spacers to provide mechanical contact therebetween. While keeping this contact, the mounting plate is secured with bolts to the printed circuit board. This forms a capacitor mounting structure. For replacement of the capacitors, by simply loosening the bolts, the entire mounting plate including all the capacitors can be demounted from the board.

Abstract: An optical linkage device includes a trimmable resistance for controlling output characteristics of a laser diode; a board having the trimmable resistance mounted thereon; and a case at least covering the board, the case provided with an adjustment hole for adjustment of a resistance value of the trimmable resistance. This arrangement permits the adjustment of the output of the laser diode to be performed with the case fixed to place. Thus is provided the optical linkage device capable of maintaining a more stable product quality.

Abstract: Apparatus is described for capacitively signalling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signalling, and reduces or eliminates the requirements for exotic metallurgy.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: A PCB having a card slot receiving a card provided with signal input/output pins and a circuit element to provide extended capability is inserted, and having data transmission pins, a power pin and a ground pin in correspondence to the signal input/output pins, comprises an electronic device internally provided for impedance matching with the card, and having a first end connected to one of the data transmission pins and a second end connected to one of the power pin and the ground pin. With this configuration, a card slot internally comprises an electronic device for impedance matching, so that a space of the PCB can be efficiently utilized.

Abstract: In the surface mount typed electronic circuit of the invention, an insulating substrate has an inductance element formed in a conductive pattern whose end portions are connected to the second lands. A bare chip is superimposed on the insulating substrate, so as to respectively connect the first electrodes and the second electrodes to the first lands and the second lands. Therefore, since the inductance element is positioned below the bare chip, the length of the connecting conductor between the inductance element and the semiconductor circuit can be extremely shortened, and a high-Q electronic circuit, especially in high-frequency, can be provided.

Abstract: A method and apparatus to mount a capacitor plate to a substrate, under a component. One embodiment of the invention involves a method to assemble a capacitor plate on a substrate. A second embodiment of the invention involves a method to fabricate a capacitor plate. A third embodiment of the invention involves an assembled substrate with a capacitor plate on the second side of the assembled substrate, under an electrical contact area of a component on the first side of the assembled substrate.

Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Abstract: In a circuit board comprising multiple layers and having an integrated circuit mounted on the outer layer thereof, a main power supply plane and a sub-power supply plane, which is disposed in an island fashion with a clearance that terminates electric connection with the main power supply plane, are formed on the same layer. The main power supply plane and the sub-power supply plane are connected by first power supply patterns that are formed on a layer different from the layer on which the power supply planes are formed and to which bypass condensers are connected. Power supply to some power supply terminals is achieved via second power supply patterns that are connected to the sub-power supply plane. The leakage of noise from the power supply terminals connected to the second power supply patterns is controlled by the first power supply patterns. Through this construction, the EMI noise radiated from the circuit board can be reduced while minimizing the number of bypass condensers.

Abstract: A resistor-capacitor network for terminating transmission lines. The network includes a core of dielectric material. Capacitors are formed within the core from spaced apart electrode plates. Terminals extend from the electrode plates to a top surface of the core. The electrode plates are oriented perpendicular to the top surface. Ball pads are located on the top surface. Resistors are located on the top surface and are connected between the ball pads and terminals. Conductive spheres are attached to the ball pads.

Abstract: An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.

Abstract: A process for manufacturing a Printed Circuit Board (PCB) substrate with passive electrical components (e.g., capacitors, inductors and/or resistors) includes weaving a plurality of dielectric strands (e.g., fiberglass yarns) and at least one electrically conductive strand (e.g., a copper wire) to form a woven fabric. The woven fabric is impregnated with a dielectric resin material to form an impregnated fabric and, thereafter, the impregnated fabric is cured to form a cured fabric. The cured fabric's upper and lower surfaces are then planed. The planing of the upper and lower surface segments the electrically conductive strands and forms a PCB substrate with a passive electrical component (e.g., a capacitor and/or inductor) therein. The passive electrical component(s) includes electrically isolated conductive strand segments separated by at least one of the dielectric resin material and the dielectric strands.

Abstract: A magnetically coupled RJ-45 modular jack assembly for Ethernet applications including a coil pack comprised of a plurality of magnetic circuits. Various numbers of the magnetic circuits may be coupled together in series by way of a variety of wires which may then be soldered directly to a printed circuit board. In order to increase the robustness of the magnetic circuit connection, each group of magnetic circuits coupled together in series, may be encapsulated in an encapsulation material. Additionally, during encapsulation, numerous of the groups of magnet circuits may be encapsulated allowing a plurality of magnetic series to be grouped together further increasing the robustness of the magnetic circuits.

Abstract: In some embodiments, the invention includes a termination card having a substrate having groups of fingers on a first side of the substrate and groups of fingers on a second side of the substrate and wherein some of the groups of fingers on the first side and some of the groups of fingers on the second side are connected through module connectors, and others of the groups of fingers on the first side are coupled to on module terminations on the first side.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system includes a first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to on module terminations of the second module; and a second path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to on module terminations of the first module.

Abstract: Disclosed is a foolproof polarity indication of poled electronics parts or devices to be given to a printed circuit board to assure that poled electronics parts and/or devices be correctly mounted in respect of their polarities to meet occasional requirements dependent on different specifications. Each pair of terminal holes are allotted to a given poled electronics part or device. Two symbols representative of such electronics part or device are arranged side by side on either side of the line drawn from one to the other terminal hole. The poled electronics part or device symbols are of reversed polarities. This dual symbol arrangement is effective to draw workers' attention in mounting electrode components in terms of their polarities. When extra components or dummy ones are combined with such a poled component, they are encircled by a boundary line, thereby showing the correct polarity direction of the poled component in respect of whether it is enclosed or not.

Abstract: The present invention provides an ancillary electrical component in very close proximity to a semiconductor device, preferably mounted directly to the semiconductor device. In one preferred embodiment, the ancillary electrical component is a capacitor. In a preferred embodiment, a terminal is provided on the semiconductor device such that the capacitor can be electrically connected directly to the terminals, as by soldering or with conductive epoxy. Connecting the capacitor between terminals of a power loop provides superior noise and transient suppression. The very short path between the capacitor and the active circuit provides for extremely low inductance, allowing for the use of relatively small capacitors. The semiconductor device then is connected to an electronic device such as a PC board for further connection to other circuitry.

Abstract: A method and apparatus to mount a capacitor plate to a substrate, under a component. One embodiment of the invention involves a method to assemble a capacitor plate on a substrate. A second embodiment of the invention involves a method to fabricate a capacitor plate. A third embodiment of the invention involves an assembled substrate with a capacitor plate on the second side of the assembled substrate, under an electrical contact area of a component on the first side of the assembled substrate.

Abstract: The invention relates to an integrated circuit assembly and a method of making same. The method according to the invention comprising providing a flex substrate having one or more dielectric tape layers, assembling one or more semiconductor chips to said flex substrate, said semiconductor chips having an active surface and a plurality of contact pads on said active surface, providing one or more conductive layers on said flex substrate, said conductive layers forming the electrical connections required for the assembly, electrically connecting the contact pads to the conductive layers.

Abstract: An electric component package having a base and a lid, the base and lid defining a hermetically sealed cavity therebetween for accommodating an electric component. The base includes at least one conductive via extending therethrough, allowing control and/or input/output (I/O) ports associated with the electric component to be coupled to the conducive vias to pass signals between the sealed cavity and the exterior of the package without passing through the junction between the base and lid. The electric component package can be produced at the wafer level using conventional silicon wafer integrated circuit manufacturing machinery prior to separating the wafer into a plurality of devices.

Abstract: A printed circuit board and method for reducing the impedance within the reference path and/or saving space within the printed circuit board. In one embodiment of the present invention, a printed circuit board comprises a plurality of conductive layers. The printed circuit board further comprises two or more vias for interconnecting two or more conductive layers. The printed circuit board further comprises an electrical component embedded in a particular via between two conductive layers to reduce the impedance within the reference path and/or save space within the printed circuit board.

Abstract: In a circuit board having a multilayer structure comprising a ground pattern and a power-supply pattern both, for example, by forming a plurality of slits along each side of the ground pattern or the power-supply pattern, a long thin conduction path connecting a corner and a side center of the ground pattern is formed and resistive elements are placed in the middles of the conduction path to short, circuit the corner and a side center of the ground pattern. Therefore, portions corresponding to an antinode and a node or antinode and an antinode of a standing wave are short-circuited. The standing wave is generated when electric power is supplied to ICs and LSIs mounted on the circuit board. Thus, noise sources caused by the standing wave cancel each other. As a result, the occurrence of an antiresonance phenomenon and an increase in impedance of the power supplying system caused by the standing wave can be suppressed.

Abstract: A circuit comprising is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.

Abstract: A decoupling capacitor structure and its use in a circuit board mounting an ASIC is provided. The decoupling capacitor structure is arranged so that parasitic inductance caused by the connection to the decoupling capacitor and the decoupling capacitor itself is reduced. The circuit boards include at least two voltage planes. An ASIC having active device(s) is connected to one face of the circuit board. A decoupling capacitor structure is provided having at least two conductive plates in a dielectric material and is connected directly or indirectly to the ASIC. Vias extend from the conductive plates through the dielectric material to connect to circuit board vias on a second face of the printed circuit board or to the ASIC. The decoupling capacitor vias are parallel to each other; and each via connected to one conductive plate is located adjacent a via connected to another conductive plate to minimize voltage deviation.

Abstract: The invention provides an electronic circuit unit that is suitable for miniaturization and excellent in high frequency characteristic. Capacitors and a wiring pattern are formed on an alumina substrate by means of thin film forming technique, and a part of the wiring pattern is served as the connection land for mounting a bare chip of a transistor. Among the capacitors, the top electrode of the capacitor is served also as a part of the connection land, and the bottom side collector electrode of the bare chip is connected to the connection land by use of conductive adhesive. Top electrodes of the residual capacitors are served as the bonding pad, and the base electrode and the emitter electrode on the top side of the bare chip are connected to the top electrodes of the respective capacitors by a wire.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: A non-contact type IC card includes a plane coil comprising a conductor line wound several times on substantially the same surface. The plane coil has respective terminals at the innermost and outermost ends. A semiconductor element has electrode terminals electrically connected to the terminals of the plane coil, respectively. A resin-filled portion is defined by a part of the circumference of the plane coil where spaces between adjacent loops of conductor line of the plane coil are filled with light-setting resin to maintain predetermined intervals between the adjacent conductors lines of the plane coil.

Abstract: A package with a Power Supply In Package (PSIP) feature may include a charge pump external to the die in order to take advantage of a smaller die size. The die may be mounted on a substrate with an array of solder balls of a Ball Grid Array. The package may have substantially the same size as a package without PSIP capability. In one embodiment, the passive components may be mounted on the die using epoxy. In another embodiment, the reduced-size passive components may be mounted on the substrate of the ball grid array in a region free of solder balls.