Abstract: A device includes a base plate, a first cell, a second cell, and a housing in which the-first cell and the second cell are arranged. The first cell and the second cell each include at least one capacitor. The device also includes a first metal plate configured connected to a capacitor in the first cell and second metal plate connected to a capacitor in the second cell. The first and second metal plates each having at least one hole configured to receive the conductive fastening element. The device also includes an electrically conductive fastening element connected through the hole in the first metal plate and the hole in the second metal plate such that the first metal plate and the second metal plate are-electrically connected to one another and mechanically attached to one another and to the base plate.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: An array capacitor is described for use with an integrated circuit (IC) mounted on an IC package. The array capacitor includes a number of first conductive layers interleaved with a number of second conductive layers and a number of dielectric layers separating adjacent conductive layers. The array capacitor further includes a number of first conductive vias to electrically connect the first conductive layers and a number of second conductive vias to electrically connect the second conductive layers. The array capacitor is provided with openings which are configured to enable pins from an IC package to pass through.

Abstract: Provided is a printed circuit board having air vents and a semiconductor package that uses the printed circuit board having the air vents. The printed circuit board includes a substrate layer having a circuit pattern and a protection layer formed on the substrate layer, a molding region on which at least one semiconductor chip is mounted and for which a molding for the semiconductor chip is performed, and a plurality of air vents extending towards edges of the printed circuit board from the molding region.

Abstract: Vias are used in multilayer printed circuit boards to route electrical interconnects between layers. Some via constructions embodiments result in the formation of a via-stub section. Via stub sections can distort signals passing through the interconnect and decrease the usable bandwidth of the interconnect. To minimize distortion and increase bandwidth, one or more terminating elements can be attached to the unterminated end of the via-stub section. The impedance terminating element may include, by way of non-limiting example, one or more resistors, capacitors, and/or inductors between the via stub and a ground layer. The impedance terminating element may be formed internally to the PCB or mounted to the PCB surface.

Abstract: The present invention is to provide a small-sized electronic component module in which RF units of a mobile phone for multi-band and multi-system are integrated at low cost. In the RF module, an RF transceiver LSI, a SAW chip, and chip components are mounted on a module board. The SAW chip is mounted on the module board so that a cavity is formed between itself and the module board, and the SAW chip and other components such as the RF transceiver LSI and the chip components are adhered to the module board at their peripheral portions by a sheet-like sealing material, and they are directly covered with the sheet-like sealing material from outside thereof.

Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes a package which is configured to be sandwiched between the IC device and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: A process for stabilizing an electrical component having a body and electrical leads projecting from the body and received in through-holes defined in a substrate, while avoiding disadvantages associated with dispensing a hot-melt adhesive during assembly of an electrical package, involves steps of providing a circuit substrate having through-holes for receiving the leads of a leaded electrical component, providing an electrical component having a body and leads extending from the body, positioning a preformed hot-melt adhesive on the circuit substrate or on the electrical component, positioning the electrical component on the circuit substrate so that the leads extend into the through-holes and so that the preformed hot-melt adhesive is positioned between and fills the gap between the body of the electrical component and the substrate, and activating and solidifying the hot-melt adhesive to securely adhere the body of the electrical component to the substrate.

Abstract: A compatible circuit for integrated circuits (ICs) includes three input terminals coupled to corresponding pins of an IC, and three function terminals corresponding to the three input terminals. Each input terminal coupled to the three function terminals via three transmission lines, each transmission line has an open segment, and each input terminal is electrically coupled to a corresponding function terminal by selectively mounting a connection component on the open segment of the corresponding transmission line according to a specification of the IC.

Abstract: A method for building a device having fluidic and electrical functions, comprising: mounting a building part with fluidic and electrical functions on a substrate that is provided with a fluidic circuit; fluidically connecting the building part with the substrate; electrically connecting the building part with the substrate; and mechanically connecting the building part with the substrate, wherein use is made of flip-chip technology; and a seal is made by means of a gasket. With such a method a hybrid microfluidic system can be built in which materials and processes for realizing the various connections (fluidic and mechanical and electrical) can be selected in principle independently of each other so the individual processes can be optimized independently of each other in a large measure. With the application of flip-chip technology, great accuracy in the positioning of the building parts can be achieved. The electrical connection is made by means of a current material and a well-developed process.

Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.

Abstract: Disclosed are apparatus and methodology for providing land grid feedthrough capacitor designs having broad applicability to signal and power filtering technologies. Such capacitor designs provide characteristics for use in decoupling applications involving both signal level and power level environments. Low equivalent series inductance (ESL) is provided by current cancellation techniques involving opposite current flow in power or signal and ground current paths through the device.

Abstract: A communication radio-frequency module is provided that has a semiconductor device to which an antenna element is connected. This communication radio-frequency module includes: a supporting body that has a waveguide formed therein; a wiring board that is fixed onto a surface of the supporting body; the semiconductor device that is flip-chip mounted onto the wiring board by ultrasonic bonding; and the antenna element that is disposed on the other surface of the supporting body. In this module, the wiring board includes a board core member that is made of a resin material, and the supporting body includes a supporting body core member that is also made of a resin material.

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area.

Abstract: There is provided a variable device circuit according to the present invention, including: a substrate; at least one movable switch device formed on a first principal surface of the substrate; at least one fixed capacitor device formed on the first principal surface of the substrate; at least one variable capacitor device formed on the first principal surface of the substrate; at least one variable inductor device formed on the first principal surface of the substrate; and wiring lines for electrically connecting the devices to one another, the wiring lines being formed on the first principal surface of the substrate; wherein electrical connections among the devices can be selected by operation of the movable switch device, whereby achieving stable, low-loss circuit characteristics with lower manufacturing cost.

Abstract: A semiconductor apparatus comprises a substrate, a semiconductor chip fixedly secured on one side of the substrate, a spirally shaped coil formed on the other side of the substrate and electrically connected to the semiconductor chip, and a conductive pattern formed on a surface of the one side of the substrate facing to the semiconductor chip for stabilizing an inductance characteristic of the coil.

Abstract: A wiring board is comprised of a core board, a capacitor, a conductor containing portion and a laminated wiring portion. The core board has an accommodation hole. The capacitor has a through hole therein and is accommodated in the accommodation hole. The conductor containing portion has a current supplying conductor and is disposed in the through hole so as to be surrounded by the capacitor. The laminated wiring portion includes a component mounting region in which a first connection terminal electrically connected to the current supplying conductor is provided. Further, second connection terminals are disposed so as to sandwich the first connection terminal therebetween.

Abstract: The present invention is to provide an electronic component where positional accuracy for arranging members constituting a circuit element such as a resister element and the like is mitigated and corrosion of a terminal electrode caused by sulfur in the atmosphere is reduced.

Abstract: An electronic system with integrated circuit device and passive component is disclosed. One embodiment provides a printed circuit board, a method for fabricating an electronic system, and an electronic system, including at least one integrated circuit device and at least one passive component, wherein the passive component is arranged at least partially underneath the integrated circuit device.

Abstract: An expanding high speed transport interface hardware method for motherboard is provided. In the method, a mezzanine card is provided and the mezzanine card has a chip socket. An expanding hardware with high speed transport interface is installed in the chip socket of the mezzanine card. In addition, the mezzanine card is inserted into an idle CPU socket in a motherboard with plural CPU structure to make the mezzanine card electrically connect with the second CPU socket, so that the mezzanine card and the expanding hardware become components of the motherboard. Finally, the motherboard is activated to detect the mezzanine card and the expanding hardware and set the CPU bus as a data transmission path between the mezzanine card and the expanding hardware so as to expand interface hardware for the idle CPU socket. Besides, more design choices and opportunities are provided for the manufacturers of motherboard and peripheral.

Abstract: An integrated circuit includes a positive lead defining a first pocket and a negative lead spaced apart from the positive lead that defines a second pocket that is aligned with the first pocket. The first and second pockets are adapted to receive and hold an electrical device such as a capacitor therein.

Abstract: Backplanes for display devices and systems incorporating such backplanes are described. Pixel electrodes are disposed in an array of rows and columns on a substrate. The pixel electrodes may include electrode extensions. Data lines having a substantially constant width are arranged in relation to the pixel electrodes. Enable lines are configured to carry signals that control current flow between the data lines and the pixel electrodes. Each enable line has a substantially constant width and crosses a row of pixel electrodes and electrode extensions. The backplane design may include storage capacitors at the crossings of the enable lines and the pixel electrodes.

Abstract: A direct connection multi-chip semiconductor element structure is proposed. A plurality of semiconductor chips are mounted and supported on a metal heat sink, such that heat generated by the chips during operation can be dissipated via the heat sink. A circuit structure is extended from the chips to provide direct electrical extension for the chips and improve the electrical performances. And exposed electrical connection terminals can be formed in the circuit structure extended from the chips to be directly electrically connected to an external electronic device.

Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: A capacitive interposer, electronic package having the capacitive interposer and electronic device with the electronic package is described. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates.

Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract: A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in first ordered channels of adjacent transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in first ordered channels of adjacent receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern.

Abstract: Methods of making metal/dielectric/metal structures include casting copper slurry onto a fugitive substrate to form the first electrode and subsequently casting dielectric and copper slurries onto the first electrode, removing the fugitive substrate and co-firing the structure, wherein the dielectric comprises glass in an amount that is less than 20% by weight of the total inorganic composition and the dielectric achieves substantially complete densification. Alternatively, a metal tape and a dielectric tape, comprising glass in the above amount, may be formed and laminated together to form a metal/dielectric/metal green tape structure, which is co-fired, such that the structure achieves substantially complete densification.

Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A DC power plane structure applied in multi-layer circuit board is provided. The DC power plane structure includes a first circuit area for receiving a DC power, a noise filter with one end electrically connected to a DC power output end of the first circuit area, and a second circuit area which is electrically isolated from the first circuit area. The second circuit area has a band gap structure, and the DC power input end of the band gap structure is electrically connected to the other end of the noise filter for inhibiting high-frequency noise generated between layers of the multi-layer circuit board.

Abstract: One embodiment of the present invention provides capacitive decoupling on the surface of a semiconductor die, instead of providing the decoupling on a package or printed circuit board to which the semiconductor die is attached. In this embodiment, a surface of a semiconductor die includes exposed power and ground conductors, which are electrically coupled to internal power and ground nodes within the semiconductor die. To provide the wafer-level decoupling, a plurality of bypass capacitors are electrically coupled between pairs of exposed power and ground conductors, so that the plurality of bypass capacitors reduce voltage noise between the power and ground conductors on the semiconductor die.

Abstract: An electronic control apparatus includes an exclusive power source line for a charge pump circuit which is discriminated from a common power source line. The exclusive power source line is connected to the common power source wiring via a via-hole va having an impedance larger than that of the exclusive source line. Similarly, the electronic control apparatus includes an exclusive ground line for the charge pump circuit which is discriminated from a common ground line. The exclusive ground line is connected to the common ground via an additional via-hole vb. Furthermore, a noise-suppressing capacitor C is connected between the exclusive power source and around lines.

Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.

Abstract: An assembly includes a substrate, a chip mounted on the substrate, a voltage controlled oscillator circuit including an inductor and further circuit elements. The inductor is mounted on or in the substrate, and the further circuit elements are mounted on or in the chip. An assembly is disclosed that includes a substrate including a first metallization plane and a second metallization plane, a chip mounted on the substrate, and an inductor mounted on or in the substrate. The inductor includes a first inductor portion in the first metallization plane and a second inductor portion in the second metallization plane. An assembly is also disclosed including a substrate, a chip mounted onto the substrate, and a transformer formed at least in part on or in the substrate.

Abstract: A memory module comprises a printed circuit board with a main surface bounded by a first side and a second side, the first side being longer than the second side, a first and a second generally rectangular memory device each having a long side and a short side, the first and second memory devices positioned on the main surface of the printed circuit board in such a way that the first memory device long side is generally parallel to the printed circuit board first side and the second memory device long side is generally perpendicular to the printed circuit board first side, and a first set of passive components connected to the first memory device and a second set of passive components connected to the second memory device, the first and second sets of passive components positioned on the main surface of the printed circuit board between the first memory device and interconnection pads.

Abstract: Circuit boards for lighting systems have identical LED landing zones printed on the board. Each zone includes at least two sets of LED contact pads. One pad set is configured to mate with contacts of an LED of a first structural type, e.g. from a first product line or manufacturer. The other pad set is configured to mate with contacts of an LED of a second type, e.g. from a different product line or manufacturer. The layout may enable an easy system re-design, e.g. to shift from one type of LED to another. Alternatively, the layout may enable one system to use LEDs of the two different types in a single LED set or array. Exemplary systems disclosed herein include an element for mixing light produced by LEDs mounted to the landing zones, such as an optical integrating cavity.

Abstract: In a flying capacitor type battery voltage detector on a circuit substrate, a large number of photo MOS switches having performance highly depending from temperature are dividedly disposed on front and back surfaces of the circuit substrate such that the photo MOS switches of the back surface are lying over the photo MOS switches of the front surface. Each of pairs of photo MOS switches connects a pair of surface lines with first and second floating lines to transmit an output voltage of each cell of a battery pack connected with the surface lines to a differential amplifier through a flying capacitor connected with the floating lines. Because of the division of the photo MOS switches on the surfaces of the circuit substrate, temperatures of the photo MOS switches have less dispersion, and an S/N ratio of each signal indicating the output voltage can be improved.

Abstract: A circuit board is formed by mounting at least one passive component on a first surface of a first laminate material; interconnecting the passive component to contact traces and vias of the first laminate material; and attaching a second laminate material to the first surface of the first laminate material utilizing a lamination process, the second laminate material sheet having at least one of a recess, a through-hole or both formed therein for accommodating the passive component in the second laminate.

Abstract: An article includes a mounting substrate, a passive component site on the mounting substrate, and an active component site on the mounting substrate. The article also includes a fluid flow barrier disposed local to the passive component site and spaced apart from the active component site. The fluid flow barrier can be a recess that resists fluid flow thereinto because of surface tension of the fluid when it meets the recess edge. The fluid flow barrier can include a boundary that diverts fluid flow due to the angle of the recess edge as the fluid approaches it. An embodiment also includes a packaging system that includes the article and at least one passive component. An embodiment also includes a method of assembling the article or the packaging system.

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract: A multilayer wiring substrate for providing a capacitor structure inside a multilayer wiring structure is disclosed. The multilayer wiring substrate includes a dielectric layer including a resin material mixed with an inorganic filler, wherein the inorganic filler is fabricated by mixing a paraelectric filler with an inorganic filler having a high dielectric constant.

Abstract: A method and system for reducing the release of high frequency electromagnetic energy into the environment is disclosed, wherein local regions of distributed capacitance are embedded within a printed circuit board (PCB) and adjacent the PCB conductive traces act as low pass filters and thus increase the rise and/or fall times occurring on such traces. The present invention increases very short rise and/or fall times (e.g., 200 picoseconds or less) without degrading or detrimentally affecting other signal characteristics. The present invention does not substantially affect the voltage amplitude and does not affect the bit period when lengthening the rise and/or fall time. Also, the present invention does not induce any timing jitter that may cause synchronization problems within the system.

Abstract: To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 ?m or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.

Abstract: A structural printed wiring board panel includes a multilayer printed wiring board having opposing, outer faces and interlayer interconnects that route RF, power and control signals. Connection areas are formed in or on at least on one face for connecting the interlayer interconnects and any electrical components. A metallic face sheet is secured onto at least one outer face, adding structural rigidity to the multilayer printed wiring board. A metallic face sheet can have apertures positioned to allow access to connection areas. RF components can be carried by a face sheet and operatively connected to connection areas. Antenna elements can be positioned on the same or an opposing face sheet and operatively connected to RF components to form a phased array printed wiring board (PWB) panel.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: A capacitor comprises a first conducting film 12 formed on a substrate 10, a first dielectric film 14 formed on the first conducting film, a second conducting film 18 formed on the first dielectric film, a second dielectric film 22 formed above the second conducting film, covering the edge of the second conducting film, a third conducting film 34 formed above the second dielectric film, covering a part of the second dielectric film covering the edge of the second conducting film. The capacitor further comprises an insulation film 28 covering the edge of the second conducing film or the part of the second dielectric film. An effective thickness of the insulation film between the second conducting film and the third conducing film in the region near the edge of the second conducting film can be increased, whereby concentration of electric fields in the region near the edge of the second conducting film. Consequently, the capacitor can have large capacitance without lowering voltage resistance.

Abstract: The present invention, roughly described, pertains to a small memory card that includes features which allow the memory card to be more easily handled by a user. In various embodiments, the memory card can include a chamfer and/or a raised portion that allows the memory card to be more easily grabbed by a human hand (or mechanical device) and also provides additional room to store passive devices such as capacitors and/or resistors. Because different electronic devices use different types of memory cards, an adaptor is provided that allows the memory cards disclosed herein to be used in ports or connectors on electronic devices that are meant for other types of memory cards.

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area.

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load 16.