Abstract: An integrated circuit module, decoupling capacitor assembly and method are disclosed. The integrated circuit module includes a substrate and integrated circuit die mounted on the substrate and having die pads and an exposed surface opposite from the substrate. A plurality of substrate bonding pads are positioned on the substrate adjacent the integrated circuit die. A decoupling capacitor assembly is mounted on each integrated circuit die and includes a capacitor carrier secured onto the exposed surface of the integrated circuit die and a decoupling capacitor carried by the capacitor carrier. A wire bond extends from the decoupling capacitor assembly to a die pad and from a die pad to a substrate bonding pad.

Abstract: A memory module includes a body with a plurality of memory chips mounted thereon and an elongated connector protruding from the body. The elongated connector includes a plurality of single in-line memory module (SIMM)-type contacts at first portions along an edge thereof and a plurality of dual in-line memory module (DIMM)-type contacts at second portions along the edge thereof. The plurality of SIMM-type contacts may be positioned at opposing end portions of the elongated connector, and the plurality of DIMM-type contacts may be positioned between the opposing end portions. Related memory systems including a system board having a socket therein configured to receive the memory module are also discussed.

Abstract: A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.

Abstract: A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract: A semiconductor package includes: a circuit board having a passive component embedded therein; and external terminals provided on a back surface of the circuit board. The passive component is provided at a different position from positions of the external terminals in a thickness direction of the circuit board.

Abstract: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: The present invention relates to a device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor; and at least one planar capacitor laminate; wherein said planar capacitor laminate serves as a low inductance path to supply a charge to said at least one embedded singulated capacitor; and wherein said at least one embedded singulated capacitor is connected in parallel to at least one of the said planar capacitor laminates; and wherein said power core is interconnected to at least one signal layer.

Abstract: An RF electronic component for mounting on a substrate includes a housing; and at least one electronic device having an input and/or output incorporated in the housing. At least one input/output terminal connects to a connection pad on the substrate; and an electrical transition provides an electrical connection between the input/output terminal and an input/output of an electronic device incorporated in the electronic component. The electrical transition comprises a side termination at least partially located on an outer surface of the housing; and an array of conductive through holes formed inside the housing at an offset from the side termination. The array is arranged so that the axes of the through holes are substantially mutually parallel and coplanar, and the array of through holes is connected to form a ground plane at the offset from the side termination.

Abstract: A power converter apparatus that includes a substrate, plate-like positive and negative interconnection members, capacitors, and a cover is disclosed. Pairs of groups of switching elements are mounted on the substrate. The cover is arranged over the substrate to encompass the switching elements, the positive interconnection member, the negative interconnection member, and the capacitor. The positive interconnection member and the negative interconnection member each have a terminal portion that is joined to a circuit pattern on the substrate by ultrasonic bonding.

Abstract: The present invention provides highly efficient system level EMI filtering in a dual feed Power Distribution Unit (PDU) using custom designed magnetic components that are uniquely designed to provide excellent performance under various load conditions. The PDU of the present invention includes filters for providing the necessary EMI filtering at all frequencies in the range between 200 Hz and 200 MHz under all load conditions including a single feed failure. Additionally, the present invention provides mechanisms for cooling EMI components using a combination of natural convection and conduction techniques at the board level to ensure no loss of EMI filtering performance. The present invention also includes blank panels made of formed Aluminum alloy sheet metal pieces or the like to direct air flow to components on printed wiring boards (PWB's) using air director plates.

Abstract: A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate.

Abstract: A power converter apparatus includes a substrate 22 on which switching elements Q, Q1 to Q6 are mounted, positive and negative terminal interconnection members 27, 28 mounted on the substrate, and a capacitor 17 having a positive terminal 17a connected to the main body of the positive terminal interconnection member 27 and a negative terminal 17b connected to the main body of the negative terminal interconnection member 28. The interconnection members each have a plate-like main body 27a, 28a that is located above and parallel to the substrate 22. The main bodies of the interconnection members are stacked to be close to each other while being electrically insulated from each other. Each of the positive terminal interconnection member and the negative terminal interconnection member further includes a plate-like extension 27b, 28b that extends from the corresponding main body toward the substrate, and a terminal portion 27c, 28c that extends from the extension and is joined to the substrate.

Abstract: Substrate structure embodiments generally have first and second sides and are configured to form at least one opening that communicates between the first and second sides. A circuit path is carried on the first side and extended over the opening wherein the circuit path has a near side facing the substrate and has a far side facing away from the substrate. A circuit element has at least one bonding pad and is inserted into the opening after which the conductive bump is arranged to join the pad to the path. In another embodiment, the bump joins the pad to the near side of the path. In another embodiment, the path defines a hole and the bump fills the hole. In yet another system embodiment, the opening comprises a recess and associated vias. These embodiments may also have a second conductive circuit path carried on the first side and having a near side facing the substrate and a far side facing away from the substrate.

Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.

Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.

Abstract: Embodiments of the present invention provide a computer system that reduces voltage noise for a processor chip. The computer system includes a package which is configured to be sandwiched between the processor chip and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: An electronic device includes an insulative substrate, a spiral inductor formed by an interconnection layer provided on a first surface of the insulative layer, a first chip that is mounted on a second surface of the insulative layer opposite to the first surface and is electrically connected to a passive circuit including the spiral inductor, the first chip having an electrically conductive substrate, and a first protrusion that is provided on one of the first and second surface of the insulative substrate and protrudes therefrom, the first protrusion being electrically connected to one of the passive circuit and the first chip to an external circuit.

Abstract: A power shunt for use within a semiconductor device of a type having a motherboard and an integrated circuit package electrically coupled to the motherboard and of a type having a spaced portion located between the motherboard and the package. The power shunt comprises a capacitor within the spaced portion between the motherboard and the package of the semiconductor device. The capacitor includes a conductive layer of a first type, a conductive layer of a second type, and a dielectric layer that electrically isolates the first type conductive layer from the second type conductive layer, wherein said first type conductive layer and second type conductive layer form a conductive bridge between the motherboard and the package. The arrangement of the capacitor fulfills the dual function of providing decoupling capacitance with the capability of supplying an additional path of current between the motherboard and package to the die load.

Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.

Abstract: A semiconductor package is obtained by separately preparing a board having, as formed on the surface thereof, an interconnect pattern containing a fine pattern having a narrow interconnect pitch adapted to connection with a high-pin-count device, and a board having, as formed on the surface thereof, an interconnect pattern containing no fine pattern but only a rough pattern having a wide interconnect pitch adapted to connection with a low-pin-count device; by mounting the devices respectively on these boards; and by stacking these boards.

Abstract: An apparatus comprising a printed circuit board having a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels; a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel; and an impedance matching terminal electrically coupled to the stub and to a ground. A process comprising providing a printed circuit board including a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels, and a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel and being designed to receive a signal from a component attached to the printed circuit board; and coupling an impedance matching terminal to the stub and to a ground.

Abstract: An electronic element module and an electronic device using the same are provided. The electronic element module includes a circuit board and a plurality of electronic elements. In one embodiment, the circuit board has a plurality of leg-holes. Each of the electronic elements includes a body and a plurality of legs that connected to the body. Wherein, the bodies of the electronic elements are glued each other, and the legs of the electronic elements are partially plugged in the leg-holes. In another one embodiment, the circuit board has a plurality of contacts. The electronic element is disposed on the circuit board with a gap therebetween. The electronic element has a plurality of terminals that electrically connect to the contacts of the circuit board correspondingly. Otherwise, the gap is filled with glue.

Abstract: An assembled circuit comprising an inductive component, a connecting conductor, and a first electronic component is disclosed. The connecting conductor is adapted to wrap a first surface of the inductive component. The first electronic component stacks on the inductive component. The assembled circuit is electrically connected to the carrier via the connecting conductor.

Abstract: A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of the ground plane. An active component is attached to the first side.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: Structure of embedded electronic elements in a PCB (printed circuit board) and the method for embedding the structure include assembling the electronic elements (such as a capacitor, a resistor, a diode) on the PCB, and then laminating other circuit layers. A group of electrodes of the electronic elements are aligned to a group of junctions on the PCB, respectively; the electronic elements are assembled on the group of junctions on the PCB; and then a metal layer is laminated on the PCB using gel film (dielectric gel) in which the PCB includes already embedded electronic elements.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: Disclosed is a printed circuit board (PCB) and a method of fabricating the same. A contact portion is formed on an internal layer of the multi-layered PCB. A groove is formed so as to expose the contact portion of the internal layer. A chip package is mounted on the PCB while being flip-chip bonded to the exposed contact portion of the internal layer.

Abstract: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Abstract: A method for improving EBG (electromagnetic bandgap) structures is provided. First, a multi-layer board having at least one EBG unit is provided. Then, a maximum input impedance of the EBG unit under a predetermined frequency band is measured, in which a frequency corresponding to the maximum input impedance is a resonance frequency, and a capacitance is determined based on the resonance frequency. Besides, a minimum input impedance of the EBG unit is measured, and a logarithmic value corresponding to the maximum input impedance and a logarithmic value corresponding to the minimum input impedance are obtained so as to determine a resistance. Finally, an electronic device having the capacitance and the resistance is coupled to the EBG unit in parallel.

Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: The invention achieves stable performance, such as low parasitic capacitance generated at conductive components. Components having a low dielectric constant of 4 or less are disposed on a base member. Functional films partitioned by the low-dielectric-constant components are also provided.

Abstract: In a communication unit 100, a ground layer section 101 which is a sheet-like conductive material and a power-source layer section 102 which is a sheet-like conductive material are laid out in such a way that their one sides face each other, a voltage is applied in such a way that the power-source layer section 102 has a predetermined reference electric potential to the ground layer section 101, a plurality of conductive layer sections 103 which are sheet-like conductive materials are laid out between the ground layer section 101 and the power-source layer section 102, each conductive layer section 103 and the power-source layer section 102 are coupled together by a pull resistor section 104, a transmission communication element transmits a signal by changing the electric potential of the conductive layer section 103 connected to that communication element with respect to the ground layer section 101, and a reception communication element receives the signal by directly or indirectly detecting a change in ele

Abstract: A package (16) for electrically connecting one or more integrated circuits (12) to a printed circuit board (14) includes a substrate body (16A), a pinout (16B), and a support assembly (18). The substrate body (16A) includes at least one insulating layer (222), and at least one patterned conductive layer (220) that is electrically connected to the integrated circuit (12) and the printed circuit board (14). The pinout (16B) extends between the substrate body (16A) and the printed circuit board (14), and the pinout (16B) electrically and mechanically connects the substrate body (16A) to the printed circuit board (14). The support assembly (18) includes at least one support (38) that extends between the substrate body (16A) and the printed circuit board (14) to support the substrate body (16A) relative to the printed circuit board (14). The support (38) includes a passive electrical component (19) that is electrically connected to the at least one patterned conductive layer (220).

Abstract: A multilayer wiring board includes a first insulating film and a first patterned metal wiring film extending along a first major surface thereof, and a second insulating film a second patterned metal wiring film extending along a second major surface thereof. The wiring board includes solid metal interconnects connecting the first patterned metal wiring film to the second patterned metal wiring film, the interconnects extending through at least one of the first and second insulating films, and a microelectronic element disposed between the first and second patterned wiring films, the microelectronic element having bond pads conductively connected to the first patterned metal wiring films. The wiring board also includes a plurality of external contacts exposed at one or more external surfaces of the multilayer wiring board, the contacts being conductively connected to at least one of the first and second patterned metal wiring films.

Abstract: In a method of preparing a circuit pattern on a printed circuit board, reflow wiring is performed by printing the circuit pattern on an insulative board with an electroconductive coating material and printing a cream solder in a wiring pattern portion of the circuit pattern to form a metal conductor. Other portions of the printed, electroconductive coating material are arranged to function as any one of a resistor (R), a capacitor (C), and a coil (L), by taking advantage of the resistance and electrostatic capacitance of the electroconductive coating material.

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract: An embodiment of an electronic component includes a circuit element disposed within a package, which includes a surface and at least one standoff protruding from the surface. For example, where the circuit element is an inductor in a power supply, the standoff may allow one to mount the inductor component over another component, such as a transistor component. Therefore, the layout area of such a power supply may be smaller than the layout area of a power supply in which the inductor and transistor components are mounted side by side.

Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.

Abstract: A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions.

Abstract: A manufacturing method for an electronic apparatus and manufacturing apparatus are provided. The manufacturing method includes applying to a surface of a sheet an adhesive to be charged into a space between a mounting board and an electronic component mounted on the mounting board, bringing the one surface of the sheet into contact with a back surface of the electronic component mounted on the mounting board and charging the adhesive into the space by bringing the adhesive into contact with a peripheral portion of the electronic component under a low pressure, and pressing a heating head against the other surface of the sheet and heating the sheet with the heating head via the sheet to set the adhesive under atmospheric pressure, in a state that the sheet is in contact with the electronic component.

Abstract: An exemplary ball grid array package for a semiconductor device includes an integrated circuit on a substrate, and a first bus on the substrate, the first bus including first portions that extend substantially parallel to the integrated circuit, interleaved with second portions that extend substantially toward the integrated circuit, each second portion having an end contiguous with a first portion and another end contiguous with a another first portion. A first set of wires connects the first bus with a first plurality of nodes on the integrated circuit. The package also includes a second bus and a second set of wires.

Abstract: Embodiments of the present invention provide a computer system that reduces voltage noise for a processor chip. The computer system includes a package which is configured to be sandwiched between the processor chip and a circuit board. This package has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the processor chip. A plurality of bypass capacitors are integrated into the package and are coupled between the power and ground connections for the processor chip, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.

Abstract: A semiconductor device mounting board, a method of manufacturing the same, a method of inspecting the same, and a semiconductor package are provided. The semiconductor device mounting board is capable of implementing a high-density and fine structure corresponding to a narrowing pitch and has high mounting reliability. A semiconductor device mounting board includes a wiring construction film including an insulating layer and a wiring layer, and a first electrode pattern disposed on one surface of the wiring construction film in which a periphery of a side surface of the electrode pattern is in contact with the insulating layer. At least a rear surface of the first electrode pattern is not in contact with the insulating layer.

Abstract: A component having an inductor to at least partially compensate for a capacitance in a circuit of the component, is described herein.

Abstract: A device includes a base plate, a first cell, a second cell, and a housing in which the-first cell and the second cell are arranged. The first cell and the second cell each include at least one capacitor. The device also includes a first metal plate configured connected to a capacitor in the first cell and second metal plate connected to a capacitor in the second cell. The first and second metal plates each having at least one hole configured to receive the conductive fastening element. The device also includes an electrically conductive fastening element connected through the hole in the first metal plate and the hole in the second metal plate such that the first metal plate and the second metal plate are-electrically connected to one another and mechanically attached to one another and to the base plate.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.