Abstract: Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.

Abstract: A coil component includes a support member, an internal coil supported by the support member and including a plurality of coil patterns, and external electrodes connected to the internal coil and including a first layer in contact with the internal coil and a second layer disposed on the first layer. The second layer is a composite layer including a conductive material and a resin. The support member includes first and second surfaces facing the external electrodes, respectively, and one or more of at least a portion of the first surface and at least a portion of the second surface are configured as cut surfaces.

Abstract: A coil component includes a body, including a coil and a support member supporting the coil, and an external electrode disposed on an external surface of the body. The coil component includes a machined surface formed on a boundary surface between a portion of the support member, removed in the vicinity of a junction portion between the external electrode and the coil, and the remainder of the support member. A cavity, from which the portion of the support member has been removed, is filled with a magnetic material, or an insulating layer is disposed in the cavity.

Abstract: In an electronic device that employs high-speed differential signaling on one or more pairs of conductors in a flexible printed circuit, RF chokes are placed in the differential signal path and mounted directly on the flexible printed circuit which is used to interconnect a peripheral device, such as an image sensor, through a connector to another device component such as a main printed circuit board. The RF chokes are configured to suppress common-mode noise propagating in the differential pairs of conductors. In one illustrative embodiment, the RF chokes are located on the flexible printed circuit adjacent to the peripheral device to suppress common-mode noise near its source. In another illustrative embodiment, the RF chokes are mounted adjacent to the connector to suppress the common-mode noise before it has an opportunity to escape the flexible printed circuit at the major discontinuity presented by the connector.

Abstract: Disclosed herein is a power electronic circuit having a reference ground and a differential mode loop unit. The differential mode loop unit has a capacitance component, a switch and an electronic component, wherein the capacitance component has a first end, the switch has a first end connecting in series with the capacitance component, the electronic component has a first end, the electronic component connects in series with the capacitance component and the switch, the capacitance component and switch are packaged in a power module, the power module has a trace and at least one output pin connected to reference ground, wherein the first end of the switch or the first end of the electronic component is only connected to the first end of the capacitance component through the trace, and the first end of the capacitance component is connected to reference ground through the output pin.

Abstract: An inductively coupled power and data transmission system include a main power source, apparel having an electrical conductor in electrical communication with the main power source, the apparel having a first inductively couplable power and data transmission sub-system to regulate power to the primary coil or coils and transmission of power and data by the primary coil or coils and reception of data by the primary coil or coils, and an independent device having a second inductively couplable power and data transmission sub-system so as to regulate reception of power and data by the secondary coil or coils and transmission of data from a secondary processor by the secondary coil or coils. The first and second primary coils transfer said power and data during inductive coupling, at electromagnetic radiation frequencies, between the first primary coil or coils and the secondary coil or coils.

Abstract: A circuit module of a battery pack includes a pattern resistor having conductivity; a temperature sensor that is adjacent to the pattern resistor and that senses a temperature of the pattern resistor; and a current detecting unit that is electrically connected to both ends of the pattern resistor, that is electrically connected to the temperature sensor, and that detects a current flowing in the pattern resistor based on a voltage across the ends of the pattern resistor and a temperature of the pattern resistor.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: A component is configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component includes a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: A planar transformer assembly, for use in charging capacitors of an ICD, includes windings arranged to minimize voltage across intervening dielectric layers. Each secondary winding of a preferred plurality of secondary windings is arranged relative to a primary winding, in a hierarchical fashion, such that the DC voltage, with respect to ground, of a first secondary winding, of the plurality of secondary windings, is lower than that of a second secondary winding, with respect to ground, wherein the first secondary winding is in closest proximity to the primary winding. The primary winding and each secondary winding are preferably formed on a corresponding plurality of dielectric layers.

Abstract: A hybrid integrated circuit in a wafer level package for an implantable medical device includes one or more passive component windings formed, at least in part, along one or more routing layers of the package. The windings may be primary and secondary windings of a transformer, wherein all or part of a magnetic core thereof is embedded in a component layer of the wafer level package. If the core includes a part bonded to a surface of the package, that part of the core may be E-shaped with legs extending into the routing layers, and, in some cases, through the routing layers. Routing layers may be formed on both sides of the component layer to accommodate the transformer windings, in some instances.

Abstract: A system includes a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component includes a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.

Abstract: The present technology relates to fused capacitor structures provided with a leadframe design configured to accepting a plurality of selectively placed fuses. The leadframe and fuse configuration enables construction of fused capacitors exhibiting low Equivalent Series Resistance (ESR) and allows construction of a variety of fuse configuration using a single leadframe design.

Abstract: A wiring board including a first rigid wiring board including a conductor and having an accommodation portion, the accommodation portion having wall surfaces, a second rigid wiring board accommodated in the accommodation portion and including a conductor electrically connected to the conductor of the first rigid wiring board, the second rigid wiring board having side surfaces, an insulation layer formed on the first rigid wiring board and the second rigid wiring board, and a metal film having a solid pattern formed directly on a boundary portion formed between the wall surfaces of the accommodation portion and the side surfaces of the second rigid wiring board.

Abstract: A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.

Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a first conductive circuit formed on the first interlayer resin insulation layer, a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and the first conductive circuit and having an opening portion exposing a portion of the first conductive circuit, a second conductive circuit formed on the second interlayer resin insulation layer, a via conductor formed in the opening portion of the second interlayer resin insulation layer and connecting the first conductive circuit and the second conductive circuit, and a coating layer having a metal layer and a coating film and formed between the first conductive circuit and the second interlayer resin insulation layer. The metal layer is formed on the surface of the first conductive circuit and the coating film is formed on the metal layer.

Abstract: A circuit board includes an outer conductive layer, a number of inner conductive layers, at least one group of vias defined through the outer conductive layer and the inner conductive layers and electrically connected each conductive layers, at least one power supply element, and at least one electronic element. The at least one group of vias surrounds the at least one power supply element. When the least one power supply element outputs current to the at least one electronic element, a first portion of the output current flows to the inner conductive layers through the group of vias surrounding the at least one power supply element to be input to the at least one electronic element, and a second portion of the output current flows into the at least one electronic element through the outer conductive layer.

Abstract: The present invention relates to, for example, printed circuit boards having a thin film battery or other electrochemical cell between or within its layer or layers. The present invention also relates to, for example, electrochemical cells within a layer stack of a printed circuit board.

Abstract: This invention provides an electronic device including a casing and a circuit board. The casing has an opening. The circuit board is located in the casing and at least includes a conductive layer and a surface insulating layer. The conductive layer includes a signal transmission portion and a static induction portion. The static induction portion is electrically disconnected with the signal transmission portion at the conductive layer, and the static induction portion is closer to the opening than the signal transmission portion. The surface insulating layer covers the signal transmission portion on the circuit board and exposes the static induction portion.

Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.

Abstract: A multi-layer substrate includes a plurality of substrate main bodies, a plurality of layers which are alternately layered with the main bodies, a signal via hole which is connected with a signal line and includes a signal column which passes through at least one substrate main body; and a sub via hole which includes a sub column which surrounds the signal column, and a pair of sub pads which extend from end parts of the sub column to be formed to the layers, the layers which are formed with the sub pads being disposed in the same layer as the layers which are formed with the signal line of the signal via hole, or being disposed outside the layers which are formed with the signal line which is connected with the signal via hole.

Abstract: A PCB includes a number of insulation layers, a number of circuit layers, a signal-interfering component, and a signal-sensitive component. The circuit layers and the insulation layers are stacked alternately. The circuit layers include at least two first circuit layers, a second circuit layer, and a ground layer. The ground layer has a first side and a second side facing away the first side. The first circuit layers are positioned near the first side and include an outmost first circuit layer and at least one inner first circuit layer positioned between the outmost first circuit layer and the ground layer. The second circuit layer is positioned near the second side. The signal-interfering component is positioned on the outmost first circuit layer. The signal-sensitive component is positioned on the second circuit layer. Each inner first circuit layer defines a copper-remove area corresponding to an orthogonal projection of the signal-interfering component thereon.

Abstract: A wiring board has a first rigid wiring board having an accommodation section, a second rigid wiring board to be accommodated in the accommodation section, and an insulation layer formed on the first rigid wiring board and the second rigid wiring board. Here, a conductor of the first rigid wiring board and a conductor of the second rigid wiring board are electrically connected to each other, and at least either a side surface of the second rigid wiring board or a wall surface of the accommodation section has a concave-convex portion.

Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.

Abstract: A mezzanine board alignment and mounting device includes a multi-stage pin connected to a main board near a mezzanine board connector disposed on the main board. The multistage pin includes a base adapted to connect to the main board, a point distal to the base adapted to pass through an opening on a mezzanine board, and a support disposed between the base and the point. A diameter of the point widens towards the support. A diameter of the support is wider than a diameter of the opening. When the point is fully inserted through the opening in the mezzanine board, the mezzanine board is aligned properly to connect with the mezzanine board connector on the main board.

Abstract: A printed circuit board (PCB) includes first to fourth layers. A power supply is arranged on the first layer. An electronic component is arranged on the fourth layer. A first via and a second via extend through the PCB and are electrically connected to the electronic component. The PCB further includes third to seventh vias. A length of a transmission path of the current flows from the power supply to electronic component through the third via and the seventh via is almost the same as a length of a transmission path of the current flows from the power supply to the electronic component through the fourth to sixth vias.

Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.

Abstract: A circuitized substrate and method of making same in which quantities of thru-holes are formed within a dielectric interposer layer. The substrate includes two printed circuit board (PCB) layers bonded to opposing sides of the interposer with electrically conductive features of each PCB aligned with the interposer thru-holes. Resistive paste is positioned on the conductive features located adjacent the thru-holes to form controlled electrically resistive connections between conductive features of the two PCBs. A circuitized substrate assembly and method of making same are also disclosed.

Abstract: The stopband characteristics of an electromagnetic bandgap structure in a printed circuit board may be preserved by selectively forming slots in an additional conductive layer of the printed circuit board. For example, an electromagnetic bandgap structure may include a layer with a continuous conductive region and another layer with a periodically patterned region having a plurality of spaced-apart patches interconnected by branches. Additional conductive layers may be included within the printed circuit board without neutralizing the bandgap by forming slots in the conductive layers in general alignment with spaces between the patches.

Abstract: A printed circuit board includes a number of signal layers, a number of ground layers, a first transmission line, a second transmission line, a first via, and a second via. The first transmission is located on one of the number of signal layers. The second transmission line is located on another of the number of signal layers. The first and second vias pass through the printed circuit board. The first via is electrically coupled to the first and second transmission lines, and is isolated from the number of ground layers. The second via is electrically coupled to one or more of the number of ground layers, and is isolated from the other of the number of ground layers to increase an inductance, thus compensating capacitive nature of an open stub and improving signal integrity.

Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Abstract: A memory module includes an electronic printed circuit board with at least one contact strip, a plurality of integrated memory components, at least one first and one second buffer component, and a number of conductor tracks, which proceed from the contact strip and which are arranged on or in the printed circuit board. The conductor tracks include data lines, control lines and address lines. The conductor tracks lead from the contact strip to the buffer components or to one of the buffer components. The printed circuit board has conductor tracks that are interposed between the first buffer component and the second buffer component and that lead from the first buffer component to the second buffer component.

Abstract: A light-emitting diode (LED) module includes a plurality of LED units and a converter having a first side. The LED units respectively include a circuit board having a second side perpendicular to the first side and a third side parallel to the first side, a plurality of LEDs positioned on the circuit board, and a connector positioned on the second side proximal to the converter. The LED module further includes a plurality of flexible flat cables (FFCs) used to electrically connect the connectors to the converter, respectively.

Abstract: A power source terminal and a ground terminal for a semiconductor integrated circuit are connected to a conductor pattern through a capacitor. The conductor pattern is connected, through a filter, to a plane conductor connected to neither a ground plane nor a power source plane. Thus, a common mode noise arising from between the power source and the ground is caused to flow into the plane conductor. This reduces the common mode noise flowing in the ground and the power source of the printed wiring board, which relatively act as antennas.

Abstract: A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.

Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.

Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.

Abstract: A circuit board comprises a center segment distributing power and low-speed signaling, and outer segments for high-speed signaling. The segments use dielectric materials with different dielectric constants, with the outer segments supporting higher-speed signal transmission.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: A printed wiring board having an insulating base material; a wiring formed on at least one surface of the insulating base material, the wiring forming a predetermined circuit pattern; a first connection terminal portion formed on the surface and electrically connected to the wiring, the first connection terminal portion having a first width; a second connection terminal portion formed on the surface and electrically connected to the wiring, the second connection terminal portion having a second width; and a cover layer configured to cover the wiring and expose the first and the second connection terminal portion.

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.

Abstract: An integrated audio transducer with associated signal processing electronics is disclosed. A silicon audio transducer, such as a MEMS microphone or speaker, can be integrated with audio processing electronics in a single package. The audio processing electronics can be configured using control signals. The audio processing electronics can provide a single line serial data interface and a single line control interface. The audio transducers can be integrated with associated processing electronics. A silicon microphone can be integrated with an Analog to Digital Converter (ADC). The ADC output can be a single line serial interface. The ADC can be configured using a single line serial control interface. A speaker may be integrated with a Digital to Analog Converter (DAC). Audio transducers can also be integrated with more complex processing electronics. Audio processing parameters such as gain, dynamic range, and filter characteristics may be configured using the serial interface.