Abstract: A power semiconductor module includes a plastic housing, a plurality of connection elements for external main connections and control connections, and at least one ceramic substrate which is provided at least on its top side with a structured metalization. The at least one ceramic substrate is fitted with semiconductor components and is inserted into a bottom opening of the plastic housing. The connection elements for the external main connections and control connections are connected by detaching a part of the structured metalization from the at least one ceramic substrate and bending it vertically upward to form a grip tab so that the grip tab can be connected to a connection element through the use of a brazed joint or a welded joint. These measures ensure an excellent stability with regard to fluctuating thermal loads.

Abstract: An integrated circuit package and a method of manufacturing the package. A silicon chip is attached to the surface of a substrate or attached to the bottom surface of a cavity in the substrate so that the active surface of the chip is exposed. One or more build-up circuit structures are formed over the substrate. Each build-up circuit structure has at least one insulation layer, at least one patterned circuit layer and a plurality of via openings with conductive material therein so that bonding pads on the active surface of the chip connect electrically with the patterned circuit layer through the vias. To form a ball grid array package, solder balls may also be attached to the solder ball pads on the patterned circuit layer so that the bonding pads on the chip are electrically connected to an external circuit through the build-up circuit structure and the solder balls.

Abstract: A capacitor-mounted metal foil of the present invention is provided with a metal foil and a plurality of capacitors formed on the metal foil. Each of the capacitors includes a conductive layer disposed above the metal foil, and a dielectric layer disposed between the metal foil and the conductive layer.

Abstract: A method of designing an electronic component comprises: a) modeling a first material with respect to a characteristic of the first material in a sufficient detail to at least partially account for a first value for the characteristic; b) modeling a second material with respect to a characteristic of the second material in a sufficient detail to at least partially account for a second value for the characteristic; c) modeling an interface between the first material and the second material such that in at least some instances the characteristic of the interface does not have an obvious characteristic or obvious value of between the first value and the second value; and d) generating a set of evaluation data from the modeling of the interface.

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.

Abstract: A multilayer module includes a first active layer with a first edge and second active layer with a second edge. Each active layer includes a flexible, polymer substrate, at least one electronic element, and a plurality of electrically-conductive traces which provide electrical connection from the respective edge to the electronic element of the active layer. The second active layer is adhered to the first active layer so that the first edge and second edge are aligned with each other thereby forming a side of the multilayer module. The multilayer module further includes a plurality of electrically-conductive lines along the side of the multilayer module, the lines providing electrical connection to the traces.

Abstract: A multilayer printed circuit board is provided which includes a base member having a surface provided with a base wiring pattern, an inner buildup layer laminated on the base member and having a surface formed with an inner buildup wiring pattern, and an outer buildup layer laminated on the surface of the inner buildup layer and having a surface formed with an outer buildup wiring pattern. The wiring patterns are electrically connected to each other through vias. The inner buildup layer is formed of a resin material which is not reinforced by glass fibers, whereas the outer buildup layer is formed of a resin material reinforced by glass fibers.

Abstract: The invention relates to a multiple-component unit in which at least two passive components have been realized one above the other. A multiple-component unit thus comprises at least one resistor and at least one capacitor, or at least two capacitors. This space-saving construction allows for a miniaturization of circuits. A further miniaturization can be achieved in that the multiple-component units are not manufactured as discrete components, but are integrated into ICs.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: A wiring substrate includes an insulating layer (1) formed with a tapered through-hole (2), a first wiring layer (3) covering an upper surface of the insulating layer (1) therewith, a second wiring layer (4) covering a lower surface of the insulating layer therewith (1), and an electrically conductive layer (5) covering an inner surface (2a) of the through-hole (2) and closing the tapered through-hole (2) at a bottom of the tapered through-hole (2).

Abstract: A printed circuit board includes a ground layer, a power supply layer divided into a plurality of lands, a dielectric layer disposed so as to cover the plurality of lands of the power supply layer, and a conductor layer disposed so as to cover the dielectric layer. The plurality of divided lands are coupled to each other by electrostatic capacitors formed by each of the lands of the power supply layer and the conductor layer sandwiching the dielectric layer therebetween.

Abstract: A circuit sub-board for regulating constant power source and strengthening ground connections. The circuit sub-board is a double-layered printed circuit board having a large surface power-source layer and a ground-connection layer. The circuit sub-board is utilized to cover the insufficiently ground-covered main board signaling lines as well as insufficiently ground-connected power and ground signaling lines on the main board. With the installation of the circuit sub-board, signals can be transmitted more reliably and with less interference.

Abstract: In an electronic circuit equipment using a multilayer circuit board on which a semiconductor chip is mounted, a thin film capacitor is provided on the multilayer circuit board. Moreover, a first electrode of the thin film capacitor and a first wiring of the multilayer circuit board are electrically connected to each other, and a second electrode of the thin film capacitor and a second wiring of the multilayer circuit board are electrically connected to each other, respectively. Furthermore, a thin film dielectric of the thin film capacitor was grown epitaxially with the first electrode as its base. The employment of the multilayer circuit board makes it possible to provide the electronic circuit equipment using the multilayer circuit board that includes the built-in thin film capacitor having the high dielectric-constant thin film dielectric.

Abstract: An electronic chip device includes an interface support film having a support film and at least one flat conductive interface placed on the support film, as well as a microcircuit connected to the interface. The interface support film possesses such properties that it can be creased or folded on itself without deterioration. The support film possesses a thickness of less than 75 &mgr;m, the best results being obtained with a thickness of between 10 &mgr;m and 30 &mgr;m. Preferably the support film is selected from among polypropylene (PP), polyethylene (PE), polyethylene teraphtalate (PET). In one embodiment, the device includes a compensation film placed on the support film. The compensation film has a recess containing the microcircuit and its connections. The recess can contain a material to encapsulate the microcircuit and its connections.

Abstract: An integrated circuit package substrate. At least one insulating layer is formed between every two neighboring patterned wiring layers for isolation. At least a via is formed to penetrate through the insulating layers to electrically connect the patterned wiring layers. A capacitor is formed within at least one of the insulating layer. The capacitor has two electrodes insulated by a dielectric layer. One of the electrodes is connected to a power source, while the other is connected to ground.

Abstract: An improved method and means for decoupling a printed circuit board are disclosed. A power plane is included having a peripheral edge. The power plane includes a first region and a second region which is separate from and contiguous to the first region. The first region is located from the peripheral edge to a middle portion of the power plane. The first region includes a peripheral portion of the power plane. The second region includes only the middle portion of the power plane. A ground plane is coupled in parallel to the power plane. The ground plane has a peripheral edge. The ground plane includes a first region, and a second region which is separate from and contiguous to the first region. The first region includes the peripheral edge and includes a peripheral portion of the ground plane. The second region includes a middle portion of the ground plane. A first plurality of decoupling elements are connected to the first region of the power plane and to the first region of the ground plane.

Abstract: A multi-chip module includes bare IC chips mounted on respective areas of a printed wiring board. Outer electrode pads on the peripheries of the board are soldered to another printed wiring board such as a motherboard. Lead pads and the outer electrode pads are interconnected through a circuit pattern, through holes, and interstitial via holes. The circuit pattern is disposed on a die bonding surface of the bare IC chips for which insulation is not necessary.

Abstract: Compositions and methods are provided whereby electronic components may be produced that comprise a) a substrate layer; b) an insulator layer coupled to the substrate layer, wherein the insulator layer comprises at least two different kinds of embedded passive components; and c) at least one additional layer coupled to the insulator layer. A preferred method comprises a) imaging an insulator layer to create a first pattern on the insulator layer; b) etching the first pattern on the insulator layer to create a first compartment in the insulator layer; c) filling the first compartment with a first material to form a first passive component; d) imaging the insulator layer to create a second pattern on the insulator layer; e) etching the second pattern on the insulator layer to create a second compartment in the insulator layer; and f) filling the second compartment with a second material to form a second passive component.

Abstract: A small circuit board, preferably having or providing capacitance is mounted on the surface of a main circuit board opposite the surface where a BGA or other integrated circuit is mounted, and within the footprint defined the integrated circuit package. Preferably the small circuit board is formed from multiple interleaved conductive and dielectric layers to provide inherent capacitance in the circuit board itself. Capacitance provided by the small circuit board can be configured by selecting the number and/or size and/or placement of the conductive layers. Discrete devices can be mounted on the small circuit board if desired.

Abstract: A printed circuit board (10) including a layered transformer (1) has a stack of layers of a first magnetic layer (2), a first transformer coil (4), an insulating body (7), a second transformer coil (5) and a second magnetic layer (3), wherein each of the transformer coils (4,5) is embodied as a two-dimensional pattern of conductive tracks. The insulating body may comprise one of more channels (8,18,28) containing a magnetic material. Instead of one printed circuit board (10), the transformer (1) may be embodied in two printed circuit boards (60) as well, each comprising a magnetic layer (2) and a transformer coil (4). Said printed circuit boards may be included in a charger device (71) and a user device (72).

Abstract: An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 &mgr;m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. The interconnect layers where considered generally as a circular cylinder have a diameter m, and the intermediate connection layer where considered generally as circular has a diameter r, r<m is given where the connection members are high in characteristic impedance than the interconnect layers, and r<m is given where the connection members are low in characteristic impedance then the interconnect layers.

Abstract: A multi-layer circuit board is provided that simultaneously optimizes impedance and interference within the multi-layer circuit board and a controlled impedance connector to which it is attached. The multi-layer circuit board includes at least one signal circuit layer, a plurality of signal contacts grouped in differential pairs and located on one signal circuit layer, and a plurality of ground contacts located on at least one ground circuit layer. The signal contacts are arranged in a pattern, or matrix, in which differential pairs of signal contacts are staggered in rows of the pattern. In accordance with an embodiment of the present invention, each differential pair of the multi-layer circuit board is more tightly coupled to a ground contact than to any other signal contact. The multi-layer circuit board, also includes a plurality of signal trace segments arranged in pairs. Both signal trace segments of a pair are equal in length and connect to signal contacts via linear routing channels.

Abstract: A glass-ceramic wiring board includes an insulating substrate, a via disposed in the insulating substrate and a via interconnection filling the interior of the via. The via interconnection is sintered material having metal particles. The metal particles have a cross-sectional area per one metal particle surrounded by a metal particle boundary of less than 2000 &mgr;2, which can be determined by cutting, etching and examining a cross-section of the via.

Abstract: A multilayered wiring board comprising, at least, two wiring layers and an interlaminar insulating layer, in which said wiring board further has, incorporated therein, at least one capacitor element which comprises a sandwiched structure of a lower electrode-forming metallic layer having formed thereon at least one recess portion, a dielectric layer formed over the lower electrode-forming metallic layer, and an upper electrode-forming metallic layer formed over the dielectric layer, and its production process. The semiconductor device comprising the multilayered wiring board having mounted thereon a semiconductor element is also disclosed.

Abstract: An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.

Abstract: A contactless interconnecting system is provided between a computer chip package and a circuit board. The system includes a computer chip package having a silicon wafer mounted on a support structure which includes a wall with a substantially planar upper surface. The wall is fabricated of a dielectric material. A pattern of discrete terminal lands are disposed on the upper surface of the wall and are electrically coupled to the silicon wafer. A circuit board is juxtaposed below the wall of the chip package and includes a substantially planar upper surface having a pattern of discrete circuit pads aligned with the terminal lands.

Abstract: A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates.

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation off a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract: An integrated circuit package substrate. At least one insulating layer is formed between every two neighboring patterned wiring layers for isolation. At least a via is formed to penetrate through the insulating layers to electrically connect the patterned wiring layers. A capacitor is formed within at least one of the insulating layer. The capacitor has two electrodes insulated by a dielectric layer. One of the electrodes is connected to a power source, while the other is connected to ground.

Abstract: An electronic package and method of making the electronic package is provided. The package includes a semiconductor chip and an multi-layered interconnect structure. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip.

Abstract: Three or more, or two or more types of electronic components are formed on one substrate, and these electronic components form an aggregated planar surface on a surface of the substrate to attain the above object.

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed.

Abstract: The invention relates to a power module with a circuit arrangement provided with active semiconductor components and passive components and with a circuit substrate, whereby at least a portion of the active semiconductor components are soldered onto a DCB substrate and at least a portion of the passive components are printed in thick film technology on at least one ceramic substrate. The upper side of the DCB substrate is structured to form track conductors and connecting surfaces for receiving the active semiconductor components and passive components of the circuit arrangement. On the ceramic substrate, for each passive component, a first print layer is printed in thick film technology and at least one contact surface as additional print layer laterally adjoining the first print layer.

Abstract: Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.

Abstract: A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Abstract: A low temperature co-fired ceramic assembly (LTCC) with a constraining core to minimize shrinkage of outer ceramic layers during firing. The outer ceramic layers have high density circuit features. A ceramic core includes several ceramic layers. Several via holes are located in the first and second ceramic layers. Several low density circuit features are located on the ceramic layers that make up the core. Outer ceramic layers are placed top and bottom of the ceramic core. The outer ceramic layers have via holes and high density circuit features. The circuit features patterned on the ceramic layers include resistors, capacitors, circuit lines, vias, inductors, or bond pads. The ceramic core is fired first in a furnace. The outer layers are then laminated to the ceramic core and fired. The ceramic core controls the shrinkage rate of the outer ceramic layers during firing allowing higher density circuit features on the outer layers.

Abstract: First to fourth power wiring conductors and first to fourth ground wiring conductors are arranged on first to fourth insulating layers, respectively, and a first signal wiring conductor is arranged on the first or second insulating layer and a second signal wiring conductor is arranged on the third or fourth insulating layer.

Abstract: A method of forming a circuit board includes, a) providing a temporary substrate; b) depositing an uncured electrically insulative circuit board material over the temporary substrate, the circuit board material adhering to the temporary substrate; c) substantially curing the uncured circuit board material into at least one self supporting sheet; d) providing circuit traces atop the cured self supporting sheet; e) mounting an electronic circuit component atop the cured self supporting sheet in electrical communication with the circuit traces; and f) peeling the temporary substrate and cured self supporting sheet from one another.

Abstract: The present invention provides a method for producing a high-density multi-layer ceramic substrate with stable characteristics, the substrate incorporating therein a passive component such as a high-precision capacitor or inductor. The method comprises the steps of providing compact blocks containing a green ceramic functional material to form the passive components; providing a composite green laminate having a plurality of ceramic green sheets comprising a ceramic insulating material and in which the compact blocks are built in pre-disposed spaces and a paste containing a metal inducing, during firing, oxidation reaction accompanied by expansion is provided in space between inside walls of the spaces and the compact blocks; firing the composite green laminate in a state in which the laminate is sandwiched by the sheet-like supports formed of green ceramics that cannot be sintered at the sintering temperature, so as to prevent shrinkage of the laminate; and removing the unsintered sheet-like supports.

Abstract: Bare IC chips (201 through 203) are mounted on respective areas (101 through 103) of a printed wiring board (100). The outer electrode pads (105) on the peripheries of the board (100) are soldered to another printed wiring board (1) such as a mother board. Lead pads (107) and the outer electrode pads (105) are interconnected through a circuit pattern (109), through holes (111) and interstitial via holes (112). The circuit pattern (109) is disposed on a die bonding surface of the bare IC chips (201 and 202) for which insulation is not necessary. A multi-chip module is thus completed.

Abstract: A method for high resolution trimming of PCB components, such as capacitors, inductors, transmission lines, transformers, antennas, resistors, etc. The method includes drilling or milling the PCB to effect the electrical characteristics of the component. The actual component can be machined to reduce the size of the component, or electrical connections to the component can be severed. The method can be used to set the capacitance of a tuning capacitor for an oscillator circuit. The tuning capacitor is etched out of the conductive planes on opposing sides of the PCB. The dielectric substrate of the PCB acts as the dielectric for the capacitor. The conductive planes are also etched to define conductive traces and connection pads suitable for surface mounting and electrically connecting the various electrical components on the PCB. The area of the selectively etched capacitive plates has a capacitance that is predetermined.

Abstract: A method for producing a layer of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of selecting a core material from one of three iron/nickel alloys, namely either (i) 58% Fe/ 42% Ni; (ii) 60% Fe/39% Ni/1% Cu; or (iii) 60% Fe/38.7% Ni/.12% Mn/.07% Si; forming the core material into a panel suitable for an intended application; cleaning the panel in preparation for plating; plating the panel with copper; subjecting the plated panel to heat treatment; and circuitizing the panel as appropriate for the intended application.

Abstract: A multi-layered printed circuit board having a plurality of burried passive elements and a method for producing the circuit board wherein the passive elements can include resistors, capacitors and inductors. The method includes the steps of manufacturing individual layers of the multi-layer printed circuit board with electrical circuits thereon and subsequently screening polymer inks having resistive, dielectric or magnetic values to form the resistors, capacitors and inductors. Each layer of the circuit board is cured to dry the polymer ink and thereafter the individual layers are bonded together to form the multi-layer board.

Abstract: An electronic control module (40) includes a base plate (12) bent about first and second major bend axis (27, 28). The base plate includes first and second grooves (29, 30) formed at an upper surface (15a) coextensive with the first and second major bend axis (27, 28). A flexible film (18) is asymmetrically bonded by adhesive films (31, 32) about the first and second major bend axis (27, 28). The asymmetrical bonding of the flexible film (18) about the major bend axis (27, 28) causes non-bonded loop portions (35) of the flexible film (18) to assume a serpentine pattern and deflect away from the major bend axis (27, 28) when the base plate (12) is bent about the major bend axis (27, 28). The bonding arrangement of the flexible film (18) to the base plate (12) permits an electrical connector (36) to be attached to the backside of the electronic control module (40).

Abstract: An apparatus for modifying a printed circuit board comprised of a nonconductively adhering flexible circuitized substrate, the flexible circuitized substrate having a conductive circuit trace composed of one or more layers of thin wires sandwiched between two or more layers of flexible insulating protective material. The wires forming the circuit trace of the flexible substrate and the conductors forming the circuitry in and on the printed circuit board are electrically interconnected at appropriate predetermined positions by establishing conductive paths through portions of the insulating layers of the flexible circuitized substrate. Circuit components can also be affixed to either the flexible circuitized substrate or to the printed circuit board or to both after the flexible circuitized substrate has been affixed to the printed circuit board.