Abstract: An integrated circuit (IC) package having multiple ICs is provided. The IC package includes a printed circuit board (PCB) having a cutout region and a substrate disposed above the PCB. The substrate includes a first cavity on a first surface of the substrate. The IC package also includes a first IC disposed on a second surface of the substrate and in the cutout region of the PCB, The IC package further includes a second IC disposed above the substrate, and a first device disposed on the second IC and in the first cavity on the first surface of the substrate.

Abstract: A printed circuit board and a power copper surface configuration method are provided. The method includes the following steps: configuring a first power supply component, a second power supply component, a power sink component, a convergence copper surface portion, a first grounding copper surface portion and a second grounding copper surface portion; determining whether currents of the first and second power supply components flow to the power sink component through the convergence copper surface portion; when the currents of the first and second power supply components flow to the power sink component through the convergence copper surface portion, determining whether the convergence copper surface portion conforms to a current balancing design of the printed circuit board according to at least one of first and second tolerable difference values and an average current. When the convergence copper surface portion conforms to the current balancing design, the method is ended.

Abstract: The various structures forming communication paths on a printed circuit board can create several undesired effects, especially when high frequency signals are considered. Non-functional pads created during the manufacturing process have the potential to create an undesired effect, but when the overall collection of non-functional pads are carefully configured, an optimized communication path can be formed. More specifically, by selectively removing some collection of the non-functional pads, the high frequency characteristics of the communication paths can be optimized.

Abstract: In a method for manufacturing a multilayer substrate, conductive patterns to define mounting electrodes are formed on a principal surface of a first base layer, and conductive patterns are formed on principal surfaces of other base layers. The base layers are stacked such that the principal surface of the first base layer is the outermost surface. The stacked base layers are laminated by pressing an elastic body to the side of the first base layer to form a multilayer body. In the multilayer body, the conductive patterns are arranged such that the proportion of the conductive patterns in regions overlapping the conductive patterns on the first base layer as viewed in the stacking direction is lower than that in a region surrounding the regions overlapping the conductive patterns.

Abstract: A system may include an input engine and a symmetry verification engine. The input engine may access an electronic circuit design of an electronic design automation (EDA) tool as well as identify a particular net in the electronic circuit design. The a symmetry verification engine may identify a pair of differential signal vias in the electronic circuit design corresponding to the particular net and determine a verification area surrounding the pair of differential signal vias. The symmetry verification engine may also verify that a particular ground via within the verification area satisfies symmetry criteria with respect to the pair of differential signal vias.

Abstract: To achieve an even distribution of different types of connections, sets of connection cells have been devised having different ratios of signal, power and ground connections in which the signal connections are all within a maximum distance of a power and/or a ground connection. In addition, the shapes of the cells are such that the cells fit together in a repeatable array that fully covers the plane of the interface, i.e., an array that tiles the plane. Accordingly, to distribute the connections substantially uniformly across the interface, the ratio of the number of signal connections, power connections and ground connections is determined; a cell is selected from the set of cells that has approximately the same ratio of the number of signal connections, power connections and ground connections; and the selected cell is repeatedly used to allocate the signal, power and ground connections in accordance with the distribution of connections in the selected cell until all the connections are distributed.

Abstract: A multi-layer circuit member includes a conductive reference plane with first and second electrically connected regions. A pair of signal conductors are in proximity to the first region and a circuit component is in proximity to the second region. An area of increased impedance exists between the first and second electrically connected regions.

Abstract: A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art.

Abstract: Embodiments of provide an integrated circuit (IC) device. The IC device can include a substrate having first and second opposing surfaces, an IC die electrically coupled to the first surface of the substrate, a plurality of contact members coupled to the first surface of the substrate, and an interposer. The interposer can include a plurality of contact elements located on a first surface thereof, each conductive element being coupled to a respective one of the plurality of contact members, and an antenna formed using a conductive layer of the interposer, the antenna being electrically coupled to the IC die through at least one of the plurality of contact elements and at least one of the plurality of contact members.

Abstract: In general, the disclosure is directed to sealed enclosures and devices that include enclosures for protecting enclosed heat sensitive components from the heat generated by enclosed heat producing components. Heat producing components within the enclosure may be placed to achieve uniform distribution of heat produced by the heat producing components, to optimize the dissipation of heat from the heat producing components to the enclosure, and to minimize the heat experienced by the heat sensitive components. The exterior of the enclosure may be designed to increase thermal dissipation and to protect against thermal radiation.

Abstract: A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 ?m) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 ?m), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.

Abstract: A method of arranging a plurality of components of a circuit board for optimal heat dissipation and a circuit apparatus having a plurality of components arranged by performing the method are provided. The method includes arranging a predetermined number of the plurality of components in the order of size of the components in a heat dissipation area having a predetermined width on a virtual straight line connecting the air inlet unit and the air outlet unit.

Abstract: A semiconductor device effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.

Abstract: Electronic devices to output signals at different frequencies are mounted to a circuit board that has a group of layers, where the group of layers include reference plane layers and signal layers between the reference plane layers. A first signal layer has conductive traces having a first dimension to communicate the signals at a first frequency, and a second signal layer has conductive traces having a second, different dimension to communicate signals at a second, different frequency. The first and second signal layers are successive layers without any reference plane layer in between the first and second signal layers.

Abstract: A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

Abstract: The disclosed structure (10) is provided with: at least three conductors (111, 131, 151) which face one-another; a through-via (101) which passes through each of the conductors (111, 131, 151); openings (112, 152) which are provided so as to surround the circumference of the through-via (101); and conductor elements (121, 141) which are located in different layers to those in which the conductors (111, 131, 151) are located, and which are connected to the through-via (101). Facing opening 112 is conductor element 121, which is larger than said opening (112), and facing opening 152 is conductor element 141, which is larger than said opening (152).

Abstract: A structural body includes: a first conductor and a second conductor of which at least portions are opposite to each other; a third conductor, interposed between the first conductor and the second conductor, of which at least a portion is opposite to the first conductor and the second conductor, and has a first opening; an interconnect provided in the inside of the first opening; and a conductor via which is electrically connected to the first conductor and the second conductor and is electrically insulated from the third conductor, wherein the interconnect is opposite to the first conductor and the second conductor, one end thereof being electrically connected to the third conductor at an edge of the first opening and an other end thereof being formed as an open end.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: A printed circuit board (PCB) stackup includes conductive layers and insulating layers interleaved among the conductive layers. The conductive layers include one or more power layers, one or more ground layers, one or more high-frequency layers, and one or more low-frequency layers. One or more first signals having one or more first frequencies greater than a first threshold are communicated over the high-frequency layers. One or more second signals having one or more second frequencies less than a second threshold are communicated over the low-frequency layers. Each second frequency is less than each first frequency. The insulating layers include one or more core layers and one or more prepreg layers arranged in alternating fashion. Each insulating layer adjacent to any high-frequency layer has a first material type. Each insulating layer not adjacent to any high-frequency layer has a second material type different than the first material type.

Abstract: A signal line and a circuit board that can be easily bent in a U shape and prevent unwanted emission include a line portion includes a plurality of laminated line portion sheets made of a flexible material. Signal lines extend within the line portion in an x-axis direction. Ground lines are provided within the line portion on a positive direction side in a z-axis direction with respect to the signal lines and have line widths equal to or smaller than the line widths of the signal lines. Ground lines are provided within the line portion on a negative direction side in the z-axis direction with respect to the signal lines. The signal lines overlap the ground lines when seen in a planar view from the z-axis direction.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract: A platform for a military radio with a vehicle adapter amplifier has been developed. The apparatus includes a base for supporting dual AN/VRC-110 radio systems. The platform has a first power supply that includes a DC power converter for converting 110/220 alternating current into +28 Volt direct current and a second power supply that converts +28 Volt direct current into +6.75 Volts direct current, +13 Volts direct current and +200 Volt direct current. The platform includes a vehicle adapter power amplifier that provides range extension to said dual AN/VRC-110 radio systems.

Abstract: A circuit board includes a dielectric layer and a signal routing layer on the dielectric layer. The signal routing layer includes chip traces, connector traces, and signal traces connected with the chip traces and the connector traces. The dielectric layer includes a signal trace area for arraying the signal traces, a chip trace area for arraying the chip traces, and a connector trace area for arraying the connector traces. The dielectric coefficient of the signal trace area is smaller than the dielectric coefficient of the chip trace area and greater than the dielectric coefficient of the connector trace area.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: An electromagnetic bandgap structure and a printed circuit board that solve a mixed signal problem are disclosed. In accordance with embodiments of the present invention, the electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, stacked in the first metal layer; a second metal layer, stacked in the first dielectric layer, and having a holed formed at a position of the second dielectric layer; a second dielectric layer, stacked in the second metal layer; a metal plate, stacked in the second dielectric layer; a first via, penetrating the hole formed in the second metal layer and connecting the first metal layer and the metal plate; a third dielectric layer, stacked in the metal plate and the second dielectric layer; a third metal layer, stacked in the third dielectric layer; and a second via, connecting the second metal layer to the third metal layer.

Abstract: A component is configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component includes a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: A module is configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module includes a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts include first contacts having address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.

Abstract: The electrical card has power modules constituted by power components and by control components that are carried by strips fastened on a support plate comprising an electrical ground plate. The power components are connected firstly to control buses, and secondly to power buses carried by the support plate and extending in a layer adjacent to the electrical ground plate.

Abstract: A DC-DC converter includes an insulating substrate with an inductor provided on the top surface thereof, a switching control IC provided therein, and a ground electrode pattern provided on the bottom surface thereof. The ground electrode pattern includes a first pattern and a second pattern separated from each other and a bridge pattern that connects the first and second patterns to each other. A capacitor and the switching control IC is connected to each of the first and second patterns. The bridge pattern faces the inductor and has a smaller width than that of the first and second patterns.

Abstract: An improved multi-layered ceramic package includes a plurality of signal planes, each having one or more signal lines; a plurality of vias, each providing one of a voltage (Vdd) power connection or a ground (Gnd) connection; and at least one reference mesh plane adjacent to one or more signal planes. The reference mesh plane includes spaced mesh lines that are separated by spaces that alternate in a narrow-wide or wide-narrow pattern. A multi-layered ceramic package using the mesh plane with alternating spaces generates significantly lower far-end (FE) noise in the ceramic package than a conventional mesh plane with constant spaces. The noise is further reduced by placing shield lines on opposite sides of signal lines in the signal plane.

Abstract: A system includes a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component includes a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices.

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract: A multilayer substrate is configured by stacking conductive layers and insulation layers. The multilayer substrate includes a core that is one of the conductive layers and is thicker than any of other conductive layers, and a first signal line that is included in the conductive layers and is adjacent to the core so that a first insulation layer that is one of the insulation layers is interposed between the core and the first signal line, the first signal line being used for transmission of an RF signal. The core has a recess portion so as to face the first signal line.

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers by way of through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

Abstract: An electrical connector comprises a high voltage pad and a high voltage plate. When connected to another electrical connector, the two plates, which are at the same voltage as the pads, form a region of high voltage in which the field is low. The pads are positioned in that region. An electrostatic clamp of an EUV lithographic apparatus may have such a pad and plate, for connecting to the electrical connector. By placing the interconnection in a low field region, triple points (points of contact between a conductor, a solid insulator and a gas) may be present in that region.

Abstract: A wiring board including a first rigid wiring board including a conductor and having an accommodation portion, the accommodation portion having wall surfaces, a second rigid wiring board accommodated in the accommodation portion and including a conductor electrically connected to the conductor of the first rigid wiring board, the second rigid wiring board having side surfaces, an insulation layer formed on the first rigid wiring board and the second rigid wiring board, and a metal film having a solid pattern formed directly on a boundary portion formed between the wall surfaces of the accommodation portion and the side surfaces of the second rigid wiring board.

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: In a high-frequency switch module, a switch IC is mounted on a multilayer board to define a high-frequency switch module. The multilayer board includes two internal wirings and two internal ground electrodes. The internal ground electrodes are spaced apart from each other at an interval when viewed from a lamination direction of the multilayer board. The first internal wiring is located on the upper surface side of the first internal ground electrode, and is entirely separated from an RF wiring, and the first internal wiring includes a power supply wiring for supplying power to the switch IC. The second internal wiring is located on the upper surface side of the second internal ground electrode, and is entirely separated from the power supply wiring, and the second internal wiring includes a signal wiring through which an RF signal propagates.

Abstract: A circuit board assembly includes two external circuit boards, at least one electrical connector, at least one electronic component, and at least one hollow substrate. Each external circuit board includes an external electromagnetic shielding layer, a circuit layer and a dielectric layer. In each external circuit board, the dielectric layer is located between the external electromagnetic shielding layer and the circuit layer. The electrical connector is connected between the circuit layers located between the external electromagnetic shielding layers. The electronic component is disposed between the external circuit boards and connected with one of the circuit layers. The hollow substrate with plural openings is disposed between the external circuit boards. The electronic component and the electrical connector are located in the openings. Both a thickness of the electronic component and a height of the electrical connector are smaller than or equal to a thickness of the hollow substrate.

Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a first conductive circuit formed on the first interlayer resin insulation layer, a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and the first conductive circuit and having an opening portion exposing a portion of the first conductive circuit, a second conductive circuit formed on the second interlayer resin insulation layer, a via conductor formed in the opening portion of the second interlayer resin insulation layer and connecting the first conductive circuit and the second conductive circuit, and a coating layer having a metal layer and a coating film and formed between the first conductive circuit and the second interlayer resin insulation layer. The metal layer is formed on the surface of the first conductive circuit and the coating film is formed on the metal layer.

Abstract: A circuit board includes an outer conductive layer, a number of inner conductive layers, at least one group of vias defined through the outer conductive layer and the inner conductive layers and electrically connected each conductive layers, at least one power supply element, and at least one electronic element. The at least one group of vias surrounds the at least one power supply element. When the least one power supply element outputs current to the at least one electronic element, a first portion of the output current flows to the inner conductive layers through the group of vias surrounding the at least one power supply element to be input to the at least one electronic element, and a second portion of the output current flows into the at least one electronic element through the outer conductive layer.

Abstract: A system of dampening resonance is provided. In an embodiment, ground traces may be coupled to a common or ground plane via dampening elements such as resistors a predetermined distance from a non-dampened coupling. Ground terminals in a connector have with a separated electrical length that allows for a potential to exist between the ground terminal and a common ground. When the ground terminals are coupled to the ground traces, the dampening element, which may be a resistor, helps convert energy traveling over ground terminal into heat, thus reducing or preventing resonance conditions in the connector.

Abstract: A circuit board includes a substrate having upper and lower sides, and first and second conductive vias extending between the upper and lower sides. The first and second conductive vias include circular outer profiles. The circuit board also includes a differential pair of conductive traces, which includes a first conductive trace having first upper and lower segments disposed on the upper and lower sides, respectively. The first upper and lower segments are electrically connected together through the first conductive via. The first upper segment is curved around the second conductive via such that the first upper segment follows the circular outer profile of the second conductive via. The differential pair of conductive traces also includes a second conductive trace having second upper and lower segments disposed on the upper and lower sides, respectively. The second upper and lower segments are electrically connected together through the second conductive via.

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the etching and plating resists, and forming a wiring having a pad for wire-bonding an electrode of an electronic component and a conductive circuit thinner than the pad by removing the metal film exposed after the plating resist is removed, a solder-resist layer on the surface of the board and wiring, an opening in the layer exposing the pad and a portion of the circuit contiguous to the pad, and a metal coating on the pad and portion of the circuit exposed through the opening.

Abstract: Provided is a method for manufacturing a multilayer wiring board, whereby even if the multilayer wiring board suffers warping or irregularities, thin-film patterns with great uniformity that are to be used as a mask for forming a wiring layer can be obtained in a simple way. A primer-coated metal foil 20 composed of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, which is prepared by applying metal layers 12 and 13 onto the surfaces of a support base 11, and the primer-coated metal foil 20 and the double-face CCL 10 are bonded and the primer resin layer 21 is cured. A via Vb is thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed on the resulting metal layer 22. After that, the etched down metal-plate layer 30 and the metal layer 22 are patterned, and using the patterned layers as a mask, the primer resin layer 21 is patterned.

Abstract: A metal core substrate is provided. A first routing member is comprised of a first area of one sheet of metal core material; a first insulation layer formed on the first area; and a first circuit pattern made of a copper foil and formed on the first insulation layer. A second routing member comprised of: a second area of the one sheet of the metal core material, which is separated from the first area; a second insulation layer formed on the second area; and a second circuit pattern made of a copper foil and formed on the second insulation layer. A connecting member electrically connects the first routing member and the second routing member. The connecting member is comprised of a third area of the one sheet of the metal core material, which is interposed between the first area and the second area.

Abstract: A fingerprint sensing circuit for reducing noise and parasitic capacitive coupling is disclosed in one embodiment of the invention as including a plurality of transmitting elements to sequentially emit a probing signal. A digital ground is provided to ground digital components in the fingerprint sensing circuit. A quiet ground, separate from and quieter than the digital ground, is provided to ground transmitting elements that are not transmitting the probing signal. Similarly, control logic is provided to connect, to the quiet ground, transmitting elements that are not transmitting the probing signal, while disconnecting, from the quiet ground, transmitting elements that are emitting the probing signal. The quiet ground helps to reduce the adverse effects of parasitic capacitive coupling and noise on the inactive transmitting elements.