Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: A structure of a circuit board for improving the performance of routing traces is described as eliminating the resonant effects from the inner layers in a circuit board. For eliminating the stray capacitor effect between the planes in the circuit board, the present invention uses a method for etching an area of a power plane and the area is corresponding to a routing plane. Consequently, the routing trace can make good electric potential reference of a ground plane. Due to the reduction of the stray capacitor, the structure for improving the performance of routing traces of the invention can avoid the resonance effect and parasitic resonance in the circuit board as produced in a high-frequency situation in order to promote the quality of the circuit board.

Abstract: A protective circuit board for a battery pack for controlling charge and discharge states of the battery pack includes an insulation layer and a first signal pattern disposed inside the insulation layer. The circuit can further include a second signal pattern disposed inside the insulation layer. The circuit can include a first dummy pattern spaced from a first side of the first signal pattern and a second dummy pattern spaced from a second side of the first signal pattern.

Abstract: Provided is a multilayer printed wiring board in which power supply patterns are shortened to decrease an impedance and electromagnetic radiation noise. The multilayer printed wiring board includes: a power supply layer (1) having at least two power supply patterns (5) with different voltages formed thereon; and a conductor layer (2) overlaid on the power supply layer (1) via an insulator, and at least one of the power supply patterns (5) has a first pattern portion (10) and a second pattern portion (11) formed in a non-contact manner with each other, and the first pattern portion (10) and the second pattern portion (11) are electrically connected to each other via a relay portion (14) including a relay pattern (12) formed on the conductor layer (2) and through holes (13) for connecting the power supply layer (1) and the conductor layer (2) at both ends of the relay pattern (12).

Abstract: A component for insertion into a hole in a multiple-layer substrate enables impedance matching of the substrate. The component comprises a conductive ground core arranged to extend through multiple-layers of the substrate when the component is inserted, a dielectric layer laterally encasing the conductive ground core, and a signal conductor layer coupled lateral to the dielectric layer.

Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.

Abstract: A shielded flexible cable having a plurality of shielded electronic circuits in close proximity to one another such that signals transmitted on one of said plurality of shielded electronic circuits do not substantially interfere with signals transmitted on the other of said plurality of electronic circuits comprising a polyimide support member supporting a plurality of etched copper traces on a first side of said polyimide support member and a copper layer on a second side of said polyimide support member; said polyimide support member flexible along at least one axis; said plurality of etched copper traces and said copper layer substantially as flexible as said polyimide support member; a silver based material, including, for example, silver ink or silver film, surrounding a portion of each of said plurality of copper traces along substantially the entire length of each of said plurality of copper traces; said silver based material in electrical communication with (i) said copper layer via discontinuities in

Abstract: A chassis and associated telecommunication circuit card are disclosed. The chassis has heat dissipation and flame containment features while accommodating a high density of the circuitry cards. Embodiments include an inner housing with a double-layer middle floor dividing the chassis into top and bottom chambers. Each layer has partially aligned slots, and an air gap is provided between the two layers. Embodiments also include a double-layer mesh cover with an air gap existing between the two mesh layers. Projections and grooves are provided on the inner surfaces of the inner housing to receive circuit cards having a guide on one edge and a fin on another. The circuit card includes conductor structures such as multiple board layers with paired and segregated conductors. The circuit card also includes some components positioned to cooperate with the ventilation features of the chassis and includes some components chosen for low-power consumption or reduced flammability.

Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.

Abstract: An optical transmitter module is described. The optical transmitter module includes a lead pin for electrically connecting the inside and outside of a housing, and a flexible printed circuit board connected to the lead pin. The flexible printed circuit board has a signal pattern and two ground conductor patterns to be connected to an optical modulation element, a laser terminal pattern to be connected to a semiconductor laser, a Peltier terminal pattern to be connected to a Peltier element, and two covering conductive layers in addition to a layer on which such patterns are formed. The covering conductive layers cover all the patterns except for the signal pattern.

Abstract: There is provided a multi-layer printed wiring board that can perform impedance control, concurrently maintaining the flexibility of a flexible portion with one or more signal lines. Such a multi-layer printed wiring board includes a plurality of rigid board units; and a flexible board unit, connecting outer layers or inner layers of the plurality of rigid board units and extending over the outer layers or the inner layers of the plurality of rigid board units. The flexible board unit includes a signal layer sending signals between the plurality of rigid board units; ground layers sandwiching the signal layer; and intermediate layers each interposed between the signal layer and one of the ground layers.

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract: The present invention incorporates electronic components into an electronic core structure that may be readily hot laminated by existing processes. The structure may include multiple desired electronic components, such as a display, battery or other power source, integrated circuits, switches, magnetic stripe emulator, antenna, smart chips or other input devices. The structure includes laminated buffer layers to bridge layers and compensate for variation in electronic component dimensions. The structure may also incorporate battery packaging as part of the core layer structure and use printed electronic circuitry as part of the electronic core layers to impart the desired characteristics. A variety of components may be incorporated in the structure.

Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.

Abstract: A built-in capacitor type power feed device for an electrical component which solves the problems of the reduction in the noise margin of the power supply system accompanying the lower drive voltages of electrical components and the noise between the power supply and ground accompanying simultaneous switching waveforms, provided with a power supply for supplying power, a printed circuit board including a signal line pattern, a power bar having conductive projections provided in shapes and at positions corresponding to the shapes and positions of electrodes of the electrical component and provided outside of the printed circuit board, a ground bar provided outside of the printed circuit board, and a high dielectric layer provided at a part corresponding to the electrical component between the power bar and the ground bar, power from the power supply being fed to electrodes of the electrical component through the power bar and the ground bar.

Abstract: A system, method and apparatus for providing a printed circuit board having optimized power delivery planes and signal routing regions are disclosed. In one aspect, the present disclosure teaches a printed circuit board having two or more cores coupled together using a prepreg sheet having selected regions of increased permittivity. In combining the cores with the prepreg sheet, the regions of increased permittivity are preferably aligned with power delivery planes defined between respective cores. By increasing the permittivity within the power delivery planes, the greater the reduction in area of the cores needed for power delivery and the greater the area retained on the cores for providing signal routing. As a result, a printed circuit board incorporating teachings of the present disclosure may support more advanced and complex information handling system implementations.

Abstract: A capacitive interposer (caposer) is disposed inside an integrated circuit package between a die and an inside surface of the package. Conductive layers within the caposer constitute a bypass capacitor. In a through-hole caposer, micro-bumps on the die pass through through-holes in the caposer and contact corresponding landing pads on the package. As they pass through the caposer, power and ground micro-bumps make contact with the plates of the bypass capacitor. In a via caposer, power and ground micro-bumps on the die are coupled to power and ground landing pads on the package as well as to the plates of the bypass capacitor by power and ground vias that extend through the caposer. In signal redistribution caposer, conductors within the caposer redistribute signals between die micro-bumps and package landing pads. In an impedance matching caposer, termination structures within the caposer provide impedance matching to a printed circuit board trace.

Abstract: While gradually increasing the widths of signal lines (104a, 104b, 105a, 105b) of first and second groups of differential signal lines (104, 105) to suppress attenuation in the lines, the opening widths of slits (104s, 105s) formed in a GND layer (102) below the differential signal lines are similarly changed. Thereby, impedance matching is realized. Further, by alternately disposing a large-width side and a small-width side of the two groups of differential signal lines (104, 105), the total wiring area widths are reduced.

Abstract: An apparatus comprising a printed circuit board having a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels; a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel; and an impedance matching terminal electrically coupled to the stub and to a ground. A process comprising providing a printed circuit board including a front side and a back side, and having therein a plurality of conductive layers, each conductive layer including one or more signal channels, and a stub extending from the front side to the back side, the stub being electrically coupled to at least one signal channel and being designed to receive a signal from a component attached to the printed circuit board; and coupling an impedance matching terminal to the stub and to a ground.

Abstract: An embedded capacitor structure comprising a main body; at least one embedded capacitor, having a first electrode, a dielectric layer, and a second electrode, formed in the main body; and at least one via electrical connection formed in the main body; wherein at least one of the first and second electrodes is free from direct electrical connection to the via electrical connections.

Abstract: A method of connecting signal lines between an integrated circuit (IC) die and a carrier or external circuit, and corresponding apparatus. Techniques for adjusting magnetic coupling between terminated signal lines include splitting a return path for termination current and disposing one nearby on either side of the terminated signal line, creating two small termination current loops conducting in opposite directions; using separate terminating impedances, which may be unequal, to control current in each of the loops; and arranging major axes of the termination current loops for a signal to be perpendicular to those of the isolation-target signal. Capacitive coupling adjustments include routing ground potential termination current return connections nearby the signal connection to shield it from the isolated signal line, using dual overlapping connections to shield each return path, and adjusting dielectric material proximity to the signal paths.

Abstract: A multilayer module includes a parts-containing module whose circuit board has been mounted at one surface with an electronic component and the electronic component is covered with a resin layer. Connection terminals are provided either at the resin layer or at the other surface of the circuit board, and a through hole is provided for connection between the two surfaces of the module. Also included is a module, which is provided with connection terminals at a place corresponding to the connection terminal, and the through hole for connection between the connection terminals and electronic component. An insulation layer is disposed between conductor layers, the insulation layer having a conductive bond for connection between connection terminals, respectively. Locations of a through hole and an electronic component in the module are not restricted by a location of the through hole.

Abstract: A printed circuit board includes a first layer including a first power portion and a first ground portion isolated from each other, and a second layer including a second power portion and a second ground portion isolated from each other. The second layer is spaced from the first layer. The second ground portion is arranged below the first power portion. The second power portion is arranged below the first ground portion. One portion of the first power portion overlaps one portion of the second power portion, and one portion of the first ground portion overlaps one portion of the second ground portion to provide a zero-intensity electric field between the first layer and the second layer. The first power portion is coupled to the second power portion via a first via. The first ground portion is coupled to the second ground portion via a second via.

Abstract: A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

Abstract: A wiring board includes a plurality of via pads disposed on a ceramic sub-core accommodated in a core board. A Cu-plated layer is formed on the surface of a conductor pad and serves as a processed face, i.e., a face to which Cu surface chemical processing is applied in order to improve the adhesion between the surface of the Cu-plated layer and that of an adjacent polymer material. The lowermost dielectric layer of a laminated wiring portion, and a via conductor formed in the dielectric layer, are in electrical contact with the processed face.

Abstract: In a semiconductor device such as a high-frequency power amplifier module, a plurality of amplifying means are formed on a semiconductor chip which is mounted on a main surface of a wiring substrate, and electrodes of the semiconductor chip are electrically connected by wires to electrodes of the wiring substrate. In order to make the high-frequency power amplifier module small in size, a substrate-side bonding electrode electrically connected to a wire set at a fixed reference electric potential is place at a location farther from a side of the semiconductor chip than a substrate-side output electrode electrically connected to an output wire. A substrate-side input electrode electrically connected to an input wire is located at a distance from the side of the semiconductor chip about equal to the distance from the side of the semiconductor chip to the substrate-side output electrode, or at a location farther from the side of the semiconductor chip than the substrate-side bonding electrode is.

Abstract: A printed circuit board wiring system including a printed wiring circuit board having a plurality of conductive layers, at least one electronic part mounted on one side of the circuit board and configured to output signals via signal lines, and an auxiliary wiring package mounted on the other side of the circuit board and including a plurality of conductive layers configured to allow the signal lines from the electronic part to pass therethrough so as to be connected to the circuit board. Further, a first set of signal lines are immediately drawn from the at least one electronic part using half of the plurality of conductive layers of the circuit board without passing through the auxiliary wiring package, and a second set of signal lines are drawn from the at least one electronic part through the circuit board and the auxiliary wiring package using the other half of the plurality of conductive layers of the circuit board.

Abstract: An apparatus and method that permits signal traces of different widths and the same impedance to be placed on the same layer of a printed circuit board (PCB). Alternatively, signal traces of different impedances but the same width may be placed on the same layer of the PCB. Ground and power planes are paired on adjacent layers of the PCB with a portion of the power plane relative to the ground plane removed. Signal traces of the same width and different impedances or vice-versa can be placed on the same layer because each signal trace is referenced to different planes.

Abstract: In a communication unit 100, a ground layer section 101 which is a sheet-like conductive material and a power-source layer section 102 which is a sheet-like conductive material are laid out in such a way that their one sides face each other, a voltage is applied in such a way that the power-source layer section 102 has a predetermined reference electric potential to the ground layer section 101, a plurality of conductive layer sections 103 which are sheet-like conductive materials are laid out between the ground layer section 101 and the power-source layer section 102, each conductive layer section 103 and the power-source layer section 102 are coupled together by a pull resistor section 104, a transmission communication element transmits a signal by changing the electric potential of the conductive layer section 103 connected to that communication element with respect to the ground layer section 101, and a reception communication element receives the signal by directly or indirectly detecting a change in ele

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.

Abstract: A low noise multilayer printed circuit board includes at least one ground layer and at least one power layer. The at least one ground layer is divided into a first area and a second area. The first area and the second area are connected by a first metal neckline. The at least one power layer is divided into a third area and a fourth area. The third area and the fourth area are connected by a second metal neckline. The first area corresponds to the third area. The second area corresponds to the fourth area. The location where the first and second areas are connected by the first metal neckline is different from that where the third and fourth areas are connected by the second metal neckline.

Abstract: A printed wiring board manufacturing process comprises forming a conductive metal layer on at least one surface of an insulating film with a sputtered metal layer in between, selectively etching the conductive metal layer and the sputtered metal layer to produce a wiring pattern, treating the laminated film with a first treatment liquid capable of dissolving nickel of the sputtered metal layer, and treating with a second treatment liquid capable of dissolving chrome of the sputtered metal layer and also capable of eliminating the sputtered metal layer in the insulating film to remove a superficial surface of the insulating film exposed from the wiring pattern together with the residual sputtered metals in the superficial surface. A printed wiring board comprises an insulating film and a wiring pattern, wherein the insulating film in an area exposed from the wiring pattern has a thickness smaller by 1 to 100 nm than that of an area under the wiring pattern.

Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.

Abstract: A light-emitting device (200) has a submount (100) and a plate for heat transfer (300) having a metallic plate (30). The submount (100) has a mount base (10), at least one light-emitting diode chip (5) mounted thereon and electrically conducting lines (12-17) formed on the mount base (10) to be connected electrically to the light-emitting diode chip (5). A first plane (11) of the mount base (10) of the submount (100) is bonded thermally to the first plate (300). For example, the plate is a circuit board having a metallic plate (30), and the submount (100) is bonded thermally to the metallic plate (30) of the one of the at least one plate (300). In an example, a second plate for heat transfer is also bonded thermally to a second plane of the mount base (100) for providing a plurality of heat transfer paths.

Abstract: A circuit board which has a high speed digital circuit in close proximity to a sensitive analog structure has a grounded, conductive band interposed between them and a ground plane with two separate, grounded portions, with a first of the portions underlying the digital circuit and a second portion underlying the analog structure. In an exemplary embodiment, the circuit board has a high density of analog-to-digital converter integrated circuits, each with two analog input signals and ten parallel high speed digital output signals corresponding to each input signal. A grounded, conductive band is placed on the board between the inputs and outputs of the integrated circuit, and a ground plane is provide which has separate, interleaved analog and digital areas, with the digital area underlying only portions of the board having digital signals and structures and the analog area underlying only portions of the board having analog signals and structures.

Abstract: A multilayered printed circuit board includes a first surface layer that includes a semiconductor integrated circuit, a second surface layer that includes a bypass capacitor and that is opposite to the first surface layer, a main power supply wiring layer, and a ground layer between the first and second surface layers. In the multilayered printed circuit board, one terminal of the bypass capacitor is connected to a midpoint of a wiring path from the main power supply wiring layer to a power supply terminal of the semiconductor integrated circuit, and an impedance of a first wiring path from the main power supply wiring layer to the terminal of the bypass capacitor is higher than an impedance of a second wiring path from the terminal of the bypass capacitor to the power supply terminal of the semiconductor integrated circuit.

Abstract: An LCD capable of preventing and electrostatic discharge is provided. The LCD includes a liquid crystal panel for displaying an image, a PCB on which electronic devices are mounted to generate signals for driving the liquid crystal panel, and a protective pattern formed around an electronic device of the electronic devices, which is vulnerable to an electrostatic discharge.

Abstract: A multilayer printed wiring board (10) includes: a build-up layer (30) that is formed on a core substrate (20) and has a conductor pattern (32) disposed on an upper surface; a low elastic modulus layer (40) that is formed on the build-up layer (30); lands (52) that are disposed on an upper surface of the low elastic modulus layer (40) and connected via solder bumps (66) to a IC chip (70); and conductor posts (50) that pass through the low elastic modulus layer (40) and electrically connect lands (52) with conductor patterns (32). The conductor posts (50) have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer (40), is greater than or equal to the aspect ratio Rasp of internal conductor posts (50b), which are positioned at internal portions of the low elastic modulus layer (40).

Abstract: A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.

Abstract: There is discolsed a cable modem device capable of reducing unnecessary signals inputted into a circuit substrate which processes signals and signal terminals from the outside and unnecessary radiation generated by the circuit substrate, the device having a hexahedral shield case which shields a circuit substrate, and a plurality of terminals for use in input/output of the signals with respect to the circuit substrate. Each of the terminals has a noise filter function, and is fixed to the shield case.

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract: The present invention provides shielded printed circuit boards and electronic devices. The printed circuit board may comprise an internal network of grounded conductive elements that are coupleable to an EMI shield that is mounted on the printed circuit board. The network of grounded conductive elements are coupleable to a grounded layer and to the EMI shield and provides improved EMI shielding through the volume of the printed circuit board below an electronic component mounted on the printed circuit board.

Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Abstract: A first power supply layer spreads over an insulating layer outside an island of a second power supply layer. A first ground layer spreads over an insulating layer outside an island of a second ground layer. First and second electrically-conductive pieces are interposed between the first and second power supply layers as well as between the first and second ground layers. A capacitor is interposed between the first and second electrically-conductive pieces. Power supply noise is forced to inevitably pass through the electrically-conductive pieces. The power supply noise thus reliably flows into the capacitor through the first and second electrically-conductive pieces. A printed wiring board is in this manner allowed to enjoy a sufficient suppression of the power supply noise.

Abstract: A circuit board and a circuit apparatus using the same are provided, which have an improved heat radiation capability near through holes piercing through its metal substrate so as to address a requirement as to heat radiation capability. The circuit apparatus has the circuit board in which a metal substrate having pierced holes is formed as a core member. Protrusions are formed at the top ends of the pierced holes, and round corners are formed at the bottom ends of the same. Insulating layers are formed on both sides of the metal substrate, and wiring pattern layers are formed on the respective insulating layers. The insulator formed on one side of the metal substrate and the insulator formed on the other side of the metal substrate are extended to inside the pierced holes. The joining surface between the extended portions is shifted off the center position of the metal substrate in the thickness direction, toward the same side as where the protrusions are formed.

Abstract: A power transfer pad, having: a non-conductive board having a top and a bottom; a plurality of conductive substrate sections disposed across the top of the non-conductive board; at least one conducting element disposed on each of the conductive substrate sections; a plurality of electrical contacts on the bottom of the non-conductive board, wherein each of the electrical contacts on the bottom of the non-conductive board are in electrical communication with one of the conductive substrate sections on the top of the non-conductive board.

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.