Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract: A mask programmable NOR ROM circuit includes serially connected ROM transistors. A drain of a topmost ROM transistor is connected to a bit line and a source of a bottommost ROM transistor is connected to a source line. A source of one ROM transistor is solely connected with a drain of an immediately adjacent ROM transistor. The ROM transistors are programmed by placing a resist mask having openings for selectively modifying a first threshold voltage level of chosen ROM transistors by implanting a threshold voltage modifying impurity. A selected ROM transistor is read by connecting the source line to a sense amplifier circuit and setting the bit line to a read biasing voltage level. The gate of the selected ROM transistor is set to a moderately high read voltage level. The gates of all unselected ROM transistor is set to a very high read voltage level.

Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.

Abstract: A memory cell (10) includes a resistive structure (1), and at least two electrodes (2) coupled to the resistive structure (1), wherein: the resistive structure (1) includes hydrogen, and the resistive structure (1) includes a material that exhibits a hydrogen ion mobility value of at least 10?8cm2/Vs.

Abstract: A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.

Abstract: A bit line decoder for sensing states of memory cells of a memory array includes R first sub-decoders that communicate with R memory sub-arrays of the memory array, respectively, where R is an integer greater than 1. Each of the R first sub-decoders includes D control devices that communicate with S bit lines of the memory array, where D and S are integers greater than 2, and S>D, (S-1) of the D control devices are connected in series with each other forming (S-2) junctions. The (S-2) junctions are directly connected to (S-2) of the S bit lines. R isolation circuits each have first ends that communicate with the R first sub-decoders, respectively, and second ends. The second ends of a first of the R isolation circuits communicate with corresponding second ends of (R-1) of the R isolation circuits. A second sub-decoder communicates with one of the R first sub-decoders via the second ends of the R isolation circuits.

Abstract: A precharge voltage supply circuit and a semiconductor device using the same are disclosed. The semiconductor device includes a first comparator for comparing a precharge voltage with a first reference voltage having a first voltage level and outputting a first compare signal as a result of the comparison, a second comparator for comparing the precharge voltage with a second reference voltage having a second voltage level and outputting a second compare signal as a result of the comparison, a decoder configured to receive and decode the first compare signal and the second compare signal and output a plurality of control signals as a result of the decoding, and a precharge voltage supply circuit configured to receive the plurality of control signals and supply the precharge voltage.

Abstract: A bit line decoder for sensing states of memory cells of a memory array includes a first sub-decoder that (i) is adjacent to the memory array and (ii) includes D control devices arranged in a first of two levels of the bit line decoder. The D control devices selectively communicate with a first set of S of B bit lines of the memory array and are connected to each other in series forming (D?1) junctions. (S?2) of the S bit lines are directly connected to the (D?1) junctions, where log2D>2, S=(D+1), And S<B, and where D, S, and B are integers. A control module generates first and second control signals. The first control signals deselect two of the D control devices. An isolation circuit includes a plurality of isolation devices, each isolation device having (i) first ends that communicate with the first sub-decoder and (ii) second ends. The first ends selectively communicate with the second ends based on the second control signals.

Abstract: A bit line decoder includes control devices that selectively communicate with bit lines and that are arranged in a multi-level configuration having a plurality of levels. Each of the levels includes a plurality of the control devices connected to each other in series forming one or more junctions. Each of the one or more junctions in one of the levels is directly connected to a respective one of the bit lines. A control module selects from the bit lines a first bit line and a second bit line associated with a memory cell when determining a state of the memory cell and generates first control signals that deselect one or more of the control devices at each of the levels. When the one or more control devices at each of the levels are deselected, a first group of the bit lines including the first bit line is charged to a first potential and a second group of the bit lines including the second bit line is charged to a second potential.

Abstract: In a semiconductor integrated circuit device having a volatile memory high-speed operation is enabled and the density of the memory can be enhanced. The volatile memory includes a word line, a complementary bit line having bit lines, a plurality of common source lines, and a memory cell that is coupled with the word line and the complementary bit lines. The memory cell includes transistors. The gate electrodes of the transistors are coupled with the word line, and the drain electrode of one of the transistors is coupled with one of the bit lines. The drain electrode of the other transistor is coupled with the other bit line. The respective source electrodes of the transistors are coupled with any one of the common source lines, or brought in a floating state, thereby storing storage information in the memory cell.

Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.

Abstract: In accordance with an embodiment of the present invention, a semiconductor memory device includes an array of thyristor-based memory formed in a silicon-on-insulator (SOI) supporting substrate. A portion of the supporting structure of the SOI substrate has a density of dopants sufficient to assist delivery of a bias to the backside of an insulating layer beneath a thyristor of the thyristor-based semiconductor memory. By enabling biasing of the substrate at the backside of the insulating layer beneath the thyristor, a back-gate control is available for controlling or compensating the gain of a component bipolar device of the thyristor with respect to temperature.

Abstract: In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values.

Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.

Abstract: A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

Abstract: A one time programmable read only memory disposed on a substrate of a first conductive type is provided. A gate structure is disposed on the substrate. A first doped region and a second doped region are disposed in the substrate at respective sides of the gate structure, and the first doped region and the second doped region are of a second conductive type which is different from the first conductive type. A third doped region of the first conductive type is disposed in the substrate and is adjacent to the second doped region, and a junction is formed between the third doped region and the second doped region. A metal silicide layer is disposed on the substrate. An clearance is formed in the metal silicide layer, and the clearance at least exposes the junction.

Abstract: A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.

Abstract: A Read Only Memory (ROM) device includes a ROM array, a row address decoder, a column address decoder, a column multiplexer, and a control circuit. Data is stored in bit cells in the ROM array. The control circuit generates control signals for reading the ROM. The row address decoder selects a word line. The column address decoder enables a bit line. The data is sensed from a bit cell corresponding to the selected word line and the enabled bit line by a corresponding sense amplifier and delivered on a data output pin of the ROM. The control signals for enabling the bit line and the sense amplifier operate at a higher voltage than supply voltage of the ROM. This reduces the ROM read time.

Abstract: A method of operating a FinFET fuse includes providing the FinFET fuse including a drain, a gate, a source, and a channel between the drain and the source; and applying a program voltage to one of the source and the drain of the FinFET fuse to cause a punch-through in the channel of the FinFET fuse. The method further includes determining a program state of the FinFET fuse.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) transistor serves as an electrically-programmable antifuse. The antifuse transistor has source, drain, gate, and substrate terminals. The gate has an associated gate oxide. In its unprogrammed state, the gate oxide is intact and the antifuse has a relatively high resistance. During programming, the gate oxide breaks down, so in its programmed state the antifuse transistor has a relatively low resistance. The antifuse transistor can be programmed by injecting hot carriers into the substrate of the device in the vicinity of the drain. Because there are more hot carriers at the drain than at the substrate, the gate oxide is stressed asymmetrically, which enhances programming efficiency. Feedback can be used to assist in turning the antifuse transistor on to inject the hot carriers.

Abstract: A write-once memory can be written only once to each memory cell; therefore, a defective bit cannot be detected by an actual inspection of writing. Accordingly, as described above, the measures, in which a redundant circuit is provided and the defective bit is modified before shipping, cannot be taken; thus, it is difficult to provide a memory with few defects. It is an object of the present invention to provide a write-once memory where the probability of a defect is reduced considerably. A nonvolatile memory that can be written only once includes a redundant memory cell, a first circuit which allocates an address to the redundant memory cell, a second circuit which outputs a determination signal that expresses whether writing is performed normally or not, and a third circuit, to which the determination signal is inputted, which controls the first circuit and the second circuit.

Abstract: One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

Abstract: By activating a word line and a bit line in parallel with a storage transistor set to OFF, the potential conditions of the charge line, and the word line, and the bit line are controlled so that the potential of a body region is increased by a leak current flowing from a connecting node to the body region in a period until the storage transistor is turned ON.

Abstract: A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second field effect transistors, fourth and fifth field effect transistors serially connected between the first and second power source terminals, and a sixth field effect transistor having a gate connected to the word line and used for data transfer between a second bit line and the drains of the fourth and fifth field effect transistors. The threshold voltages of the first and fourth field effect transistors are different from each other and the magnitude relation thereof is determined according to ROM data.

Abstract: A semiconductor memory device includes a memory core which receives a specific stress item and a pattern item from an external source, a switch part which provides the power supplied from an external source and a switch control part which controls the switch part. The memory core responds to the specific stress item to be tested for stability, and the switch control part isolates the switch part if the specific stress item is supplied to the memory core two or more times.

Abstract: A method of generating a ROM bit cell array layout is provided, the method comprising the steps of: inputting a predetermined memory architecture having a predetermined positioning of bit lines and virtual ground lines, said memory architecture comprising a plurality of columns of memory cells, each column of memory cells being located between its own associated bit line and its own associated virtual ground line, and adjacent memory cells in each column of memory cells sharing a common connection to either said associated bit line or said associated virtual ground line; evaluating a possible range of width of active area of each of said columns of memory cells, in dependence on said predetermined positioning of bit lines and virtual ground lines; selecting a final width of active area in dependence on at least one performance characteristic associated with said final width of active area; and generating said ROM bit cell array layout according to said final width of active area.

Abstract: In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.

Abstract: Embodiments relate to a manufacturing method of a one time programmable (OTP) memory device including: forming a common source in a linear configuration on a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate at both sides of the source; forming a gate over the gate dielectric layer; forming a spacer between the gates and at both side walls of the gate; and forming a drain on the semiconductor substrate at both sides of the spacer. With embodiments, the OTP memory device can be formed together with the logic part using the logic process and can increase the storage capacity of the OTP memory device by improving density of memory arrays.

Abstract: A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.

Abstract: An apparatus and method for providing a read-only memory (ROM) bit cell having one each of a PMOS transistor and an NMOS transistor, which has reduced static and dynamic electric power losses, are described. In particular, the bit cell does not require a pre-charge transistor. The sense amplifier for determining the voltages on ROM bit lines may be a digital inverter, address decoding may be simplified since there are no timing requirements with respect to transistor pre-charge, and chips containing a plurality of ROM bit cell may be readily programmed. In one embodiment of the invention, each bit cell includes one PMOS transistor having its source in electrical connection with a voltage source, its drain connected or unconnected to a bit line, and its gate connected to an inverted version of the word line signal; and one NMOS transistor having its source connected to a lower voltage source, its drain connected or disconnected to the bit line, and its gate connected to the word line.

Abstract: According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices.

Abstract: A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.

Abstract: A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with multiple transistors. The arrangement of the ROM is such that the word line of a selected row is pulled down to a ground voltage (Vgnd). Non-selected word lines are kept at a supply voltage VDD to ensure that unwanted rows will not have any sub-threshold current (as Vds=0). So during read “1” operation (that is when bit line (BL) is high) load cells would not leak unnecessarily. Thus the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse including a first conductor including a first cutting target region, and a second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on the semiconductor substrate, wherein a flowing-out region is formed of the first conductor flowing toward outside between the first cutting target region and the second cutting target region in a condition of cutting the electrical fuse.

Abstract: A nonvolatile memory, such as a write-once memory, includes a memory cell array that has first memory cells and at least one second memory cell. The memory also includes a first writing circuit that is capable of writing data to the first memory cells and the second memory cell, a second writing circuit, and a verify circuit which is capable of confirming whether the data is normally stored in the first memory cells. When the writing of data to one of the first memory cells fails, the second writing circuit is arranged to assign an address of the one of the first memory cells to the second memory cell. The first memory cells and the second memory cell are arranged to irreversibly change their electrical resistance when the data is stored in them. The first memory cells and the second memory cell include an organic compound layer interposed between a pair of electrodes.

Abstract: For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.

Abstract: The invention relates to a nonvolatile two-transistor semiconductor memory cell and an associated fabrication method, source and drain regions (2) for a selection transistor (AT) and a memory transistor (ST) being formed in a substrate (1). The memory transistor (ST) has a first insulation layer (3), a charge storage layer (4), a second insulation layer (5) and a memory transistor control layer (6), while the selection transistor (AT) has a first insulation layer (3?) and a selection transistor control layer (4*). By using different materials for the charge storage layer (4) and the selection transistor control layer (4*), it is possible to significantly improve the charge retention properties of the memory cell by adapting the substrate doping with electrical properties remaining the same.

Abstract: A memory bitcell comprises first (102) and second (103) transistors and a cantilever module (104) having two states. The first transistor (102) is arranged to communicate a first signal to the input of the cantilever module (104) upon receipt of a second signal. The second transistor (103) is arranged to bypass the cantilever module (104) upon receipt of a third signal (RST). The memory bitcell is operable such that the state of the cantilever (104) can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal.

Abstract: A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit.

Abstract: An embodiment of a device for memorization of a memory bit is provided, comprising a bistable circuit having complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract: A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.

Abstract: Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors.

Abstract: A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

Abstract: There is provided a semiconductor storage device including a substrate area, a first and a second isolation area, a first well area where the first transistor is placed, a second well area where the second transistor to output a first voltage to bring the first transistor into non-conduction is placed, and a third well area where the third transistor to output a second voltage to bring the first transistor into conduction is placed. The second and third well areas and the second isolation area are formed between two of the first well area, the second isolation area is formed between the second well area and one of the first well area, and the third well area is formed between the second well area and another one of the first well area.

Abstract: This invention provides a semiconductor memory device in which standby current is suppressed to a small level. A ROM device includes memory cells for reading data corresponding to impedance between a terminal connected to bit lines and a source terminal and source power lines connected to the source terminal. In this ROM device, bias voltage is applied between the terminals of selected memory cells.

Abstract: The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

Abstract: The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.

Abstract: The invention concerns a ROM comprising a set of memory points arranged in rows and columns, each memory point capable of storing two bits of data and comprising a single switch controllable to connect together first and second terminals of said switch, each of said first and second terminals being connected to one of first, second and third conductive lines, wherein said switch is connected via said first and second terminals between said first and second lines to encode a first data value, between said first and third lines to encode a second data value, between said second and third lines to encode a third data value, and both of said first and second terminals being connected to the same one of said first, second and third lines to encode a fourth data value.

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Abstract: A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.